12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2bfee95bbSGrant Likely /* 3bfee95bbSGrant Likely * Support for 'media5200-platform' compatible boards. 4bfee95bbSGrant Likely * 5bfee95bbSGrant Likely * Copyright (C) 2008 Secret Lab Technologies Ltd. 6bfee95bbSGrant Likely * 7bfee95bbSGrant Likely * Description: 8bfee95bbSGrant Likely * This code implements support for the Freescape Media5200 platform 9bfee95bbSGrant Likely * (built around the MPC5200 SoC). 10bfee95bbSGrant Likely * 11bfee95bbSGrant Likely * Notable characteristic of the Media5200 is the presence of an FPGA 12bfee95bbSGrant Likely * that has all external IRQ lines routed through it. This file implements 13bfee95bbSGrant Likely * a cascaded interrupt controller driver which attaches itself to the 14bfee95bbSGrant Likely * Virtual IRQ subsystem after the primary mpc5200 interrupt controller 15bfee95bbSGrant Likely * is initialized. 16bfee95bbSGrant Likely */ 17bfee95bbSGrant Likely 18bfee95bbSGrant Likely #undef DEBUG 19bfee95bbSGrant Likely 20bfee95bbSGrant Likely #include <linux/irq.h> 21bfee95bbSGrant Likely #include <linux/interrupt.h> 22bfee95bbSGrant Likely #include <linux/io.h> 23e6f6390aSChristophe Leroy #include <linux/of_address.h> 24e6f6390aSChristophe Leroy #include <linux/of_irq.h> 25bfee95bbSGrant Likely #include <asm/time.h> 26bfee95bbSGrant Likely #include <asm/machdep.h> 27bfee95bbSGrant Likely #include <asm/mpc52xx.h> 28bfee95bbSGrant Likely 29ce6d73c9SUwe Kleine-König static const struct of_device_id mpc5200_gpio_ids[] __initconst = { 30bfee95bbSGrant Likely { .compatible = "fsl,mpc5200-gpio", }, 31bfee95bbSGrant Likely { .compatible = "mpc5200-gpio", }, 32bfee95bbSGrant Likely {} 33bfee95bbSGrant Likely }; 34bfee95bbSGrant Likely 35bfee95bbSGrant Likely /* FPGA register set */ 36bfee95bbSGrant Likely #define MEDIA5200_IRQ_ENABLE (0x40c) 37bfee95bbSGrant Likely #define MEDIA5200_IRQ_STATUS (0x410) 38bfee95bbSGrant Likely #define MEDIA5200_NUM_IRQS (6) 39bfee95bbSGrant Likely #define MEDIA5200_IRQ_SHIFT (32 - MEDIA5200_NUM_IRQS) 40bfee95bbSGrant Likely 41bfee95bbSGrant Likely struct media5200_irq { 42bfee95bbSGrant Likely void __iomem *regs; 43bfee95bbSGrant Likely spinlock_t lock; 44bae1d8f1SGrant Likely struct irq_domain *irqhost; 45bfee95bbSGrant Likely }; 46bfee95bbSGrant Likely struct media5200_irq media5200_irq; 47bfee95bbSGrant Likely 488a2df7a0SLennert Buytenhek static void media5200_irq_unmask(struct irq_data *d) 49bfee95bbSGrant Likely { 50bfee95bbSGrant Likely unsigned long flags; 51bfee95bbSGrant Likely u32 val; 52bfee95bbSGrant Likely 53bfee95bbSGrant Likely spin_lock_irqsave(&media5200_irq.lock, flags); 54bfee95bbSGrant Likely val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 55476eb491SGrant Likely val |= 1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d)); 56bfee95bbSGrant Likely out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); 57bfee95bbSGrant Likely spin_unlock_irqrestore(&media5200_irq.lock, flags); 58bfee95bbSGrant Likely } 59bfee95bbSGrant Likely 608a2df7a0SLennert Buytenhek static void media5200_irq_mask(struct irq_data *d) 61bfee95bbSGrant Likely { 62bfee95bbSGrant Likely unsigned long flags; 63bfee95bbSGrant Likely u32 val; 64bfee95bbSGrant Likely 65bfee95bbSGrant Likely spin_lock_irqsave(&media5200_irq.lock, flags); 66bfee95bbSGrant Likely val = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 67476eb491SGrant Likely val &= ~(1 << (MEDIA5200_IRQ_SHIFT + irqd_to_hwirq(d))); 68bfee95bbSGrant Likely out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, val); 69bfee95bbSGrant Likely spin_unlock_irqrestore(&media5200_irq.lock, flags); 70bfee95bbSGrant Likely } 71bfee95bbSGrant Likely 72bfee95bbSGrant Likely static struct irq_chip media5200_irq_chip = { 73b27df672SThomas Gleixner .name = "Media5200 FPGA", 748a2df7a0SLennert Buytenhek .irq_unmask = media5200_irq_unmask, 758a2df7a0SLennert Buytenhek .irq_mask = media5200_irq_mask, 768a2df7a0SLennert Buytenhek .irq_mask_ack = media5200_irq_mask, 77bfee95bbSGrant Likely }; 78bfee95bbSGrant Likely 79bd0b9ac4SThomas Gleixner static void media5200_irq_cascade(struct irq_desc *desc) 80bfee95bbSGrant Likely { 81ec775d0eSThomas Gleixner struct irq_chip *chip = irq_desc_get_chip(desc); 822c899658SMarc Zyngier int val; 83bfee95bbSGrant Likely u32 status, enable; 84bfee95bbSGrant Likely 85bfee95bbSGrant Likely /* Mask off the cascaded IRQ */ 86239007b8SThomas Gleixner raw_spin_lock(&desc->lock); 878a2df7a0SLennert Buytenhek chip->irq_mask(&desc->irq_data); 88239007b8SThomas Gleixner raw_spin_unlock(&desc->lock); 89bfee95bbSGrant Likely 90bfee95bbSGrant Likely /* Ask the FPGA for IRQ status. If 'val' is 0, then no irqs 91bfee95bbSGrant Likely * are pending. 'ffs()' is 1 based */ 92bfee95bbSGrant Likely status = in_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE); 93bfee95bbSGrant Likely enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS); 94bfee95bbSGrant Likely val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT); 95bfee95bbSGrant Likely if (val) { 962c899658SMarc Zyngier generic_handle_domain_irq(media5200_irq.irqhost, val - 1); 972c899658SMarc Zyngier /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i\n", 982c899658SMarc Zyngier * __func__, virq, status, enable, val - 1); 99bfee95bbSGrant Likely */ 100bfee95bbSGrant Likely } 101bfee95bbSGrant Likely 102bfee95bbSGrant Likely /* Processing done; can reenable the cascade now */ 103239007b8SThomas Gleixner raw_spin_lock(&desc->lock); 1048a2df7a0SLennert Buytenhek chip->irq_ack(&desc->irq_data); 10598488db9SThomas Gleixner if (!irqd_irq_disabled(&desc->irq_data)) 1068a2df7a0SLennert Buytenhek chip->irq_unmask(&desc->irq_data); 107239007b8SThomas Gleixner raw_spin_unlock(&desc->lock); 108bfee95bbSGrant Likely } 109bfee95bbSGrant Likely 110bae1d8f1SGrant Likely static int media5200_irq_map(struct irq_domain *h, unsigned int virq, 111bfee95bbSGrant Likely irq_hw_number_t hw) 112bfee95bbSGrant Likely { 113bfee95bbSGrant Likely pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw); 114ec775d0eSThomas Gleixner irq_set_chip_data(virq, &media5200_irq); 115ec775d0eSThomas Gleixner irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq); 116212d786dSThomas Gleixner irq_set_status_flags(virq, IRQ_LEVEL); 117bfee95bbSGrant Likely return 0; 118bfee95bbSGrant Likely } 119bfee95bbSGrant Likely 120bae1d8f1SGrant Likely static int media5200_irq_xlate(struct irq_domain *h, struct device_node *ct, 12140d50cf7SRoman Fietze const u32 *intspec, unsigned int intsize, 122bfee95bbSGrant Likely irq_hw_number_t *out_hwirq, 123bfee95bbSGrant Likely unsigned int *out_flags) 124bfee95bbSGrant Likely { 125bfee95bbSGrant Likely if (intsize != 2) 126bfee95bbSGrant Likely return -1; 127bfee95bbSGrant Likely 128bfee95bbSGrant Likely pr_debug("%s: bank=%i, number=%i\n", __func__, intspec[0], intspec[1]); 129bfee95bbSGrant Likely *out_hwirq = intspec[1]; 130bfee95bbSGrant Likely *out_flags = IRQ_TYPE_NONE; 131bfee95bbSGrant Likely return 0; 132bfee95bbSGrant Likely } 133bfee95bbSGrant Likely 1349f70b8ebSGrant Likely static const struct irq_domain_ops media5200_irq_ops = { 135bfee95bbSGrant Likely .map = media5200_irq_map, 136bfee95bbSGrant Likely .xlate = media5200_irq_xlate, 137bfee95bbSGrant Likely }; 138bfee95bbSGrant Likely 139bfee95bbSGrant Likely /* 140bfee95bbSGrant Likely * Setup Media5200 IRQ mapping 141bfee95bbSGrant Likely */ 142bfee95bbSGrant Likely static void __init media5200_init_irq(void) 143bfee95bbSGrant Likely { 144bfee95bbSGrant Likely struct device_node *fpga_np; 145bfee95bbSGrant Likely int cascade_virq; 146bfee95bbSGrant Likely 147bfee95bbSGrant Likely /* First setup the regular MPC5200 interrupt controller */ 148bfee95bbSGrant Likely mpc52xx_init_irq(); 149bfee95bbSGrant Likely 150bfee95bbSGrant Likely /* Now find the FPGA IRQ */ 151bfee95bbSGrant Likely fpga_np = of_find_compatible_node(NULL, NULL, "fsl,media5200-fpga"); 152bfee95bbSGrant Likely if (!fpga_np) 153bfee95bbSGrant Likely goto out; 154b7c670d6SRob Herring pr_debug("%s: found fpga node: %pOF\n", __func__, fpga_np); 155bfee95bbSGrant Likely 156bfee95bbSGrant Likely media5200_irq.regs = of_iomap(fpga_np, 0); 157bfee95bbSGrant Likely if (!media5200_irq.regs) 158bfee95bbSGrant Likely goto out; 159bfee95bbSGrant Likely pr_debug("%s: mapped to %p\n", __func__, media5200_irq.regs); 160bfee95bbSGrant Likely 161bfee95bbSGrant Likely cascade_virq = irq_of_parse_and_map(fpga_np, 0); 162bfee95bbSGrant Likely if (!cascade_virq) 163bfee95bbSGrant Likely goto out; 164bfee95bbSGrant Likely pr_debug("%s: cascaded on virq=%i\n", __func__, cascade_virq); 165bfee95bbSGrant Likely 166bfee95bbSGrant Likely /* Disable all FPGA IRQs */ 167bfee95bbSGrant Likely out_be32(media5200_irq.regs + MEDIA5200_IRQ_ENABLE, 0); 168bfee95bbSGrant Likely 169bfee95bbSGrant Likely spin_lock_init(&media5200_irq.lock); 170bfee95bbSGrant Likely 171a8db8cf0SGrant Likely media5200_irq.irqhost = irq_domain_add_linear(fpga_np, 172a8db8cf0SGrant Likely MEDIA5200_NUM_IRQS, &media5200_irq_ops, &media5200_irq); 173bfee95bbSGrant Likely if (!media5200_irq.irqhost) 174bfee95bbSGrant Likely goto out; 175bfee95bbSGrant Likely pr_debug("%s: allocated irqhost\n", __func__); 176bfee95bbSGrant Likely 177*593d7b89SLiang He of_node_put(fpga_np); 178*593d7b89SLiang He 179ec775d0eSThomas Gleixner irq_set_handler_data(cascade_virq, &media5200_irq); 180ec775d0eSThomas Gleixner irq_set_chained_handler(cascade_virq, media5200_irq_cascade); 181bfee95bbSGrant Likely 182bfee95bbSGrant Likely return; 183bfee95bbSGrant Likely 184bfee95bbSGrant Likely out: 185bfee95bbSGrant Likely pr_err("Could not find Media5200 FPGA; PCI interrupts will not work\n"); 186*593d7b89SLiang He of_node_put(fpga_np); 187bfee95bbSGrant Likely } 188bfee95bbSGrant Likely 189bfee95bbSGrant Likely /* 190bfee95bbSGrant Likely * Setup the architecture 191bfee95bbSGrant Likely */ 192bfee95bbSGrant Likely static void __init media5200_setup_arch(void) 193bfee95bbSGrant Likely { 194bfee95bbSGrant Likely 195bfee95bbSGrant Likely struct device_node *np; 196bfee95bbSGrant Likely struct mpc52xx_gpio __iomem *gpio; 197bfee95bbSGrant Likely u32 port_config; 198bfee95bbSGrant Likely 199bfee95bbSGrant Likely if (ppc_md.progress) 200bfee95bbSGrant Likely ppc_md.progress("media5200_setup_arch()", 0); 201bfee95bbSGrant Likely 202bfee95bbSGrant Likely /* Map important registers from the internal memory map */ 203bfee95bbSGrant Likely mpc52xx_map_common_devices(); 204bfee95bbSGrant Likely 205bfee95bbSGrant Likely /* Some mpc5200 & mpc5200b related configuration */ 206bfee95bbSGrant Likely mpc5200_setup_xlb_arbiter(); 207bfee95bbSGrant Likely 208bfee95bbSGrant Likely np = of_find_matching_node(NULL, mpc5200_gpio_ids); 209bfee95bbSGrant Likely gpio = of_iomap(np, 0); 210bfee95bbSGrant Likely of_node_put(np); 211bfee95bbSGrant Likely if (!gpio) { 212bfee95bbSGrant Likely printk(KERN_ERR "%s() failed. expect abnormal behavior\n", 213bfee95bbSGrant Likely __func__); 214bfee95bbSGrant Likely return; 215bfee95bbSGrant Likely } 216bfee95bbSGrant Likely 217bfee95bbSGrant Likely /* Set port config */ 218bfee95bbSGrant Likely port_config = in_be32(&gpio->port_config); 219bfee95bbSGrant Likely 220bfee95bbSGrant Likely port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */ 221bfee95bbSGrant Likely port_config |= 0x01000000; 222bfee95bbSGrant Likely 223bfee95bbSGrant Likely out_be32(&gpio->port_config, port_config); 224bfee95bbSGrant Likely 225bfee95bbSGrant Likely /* Unmap zone */ 226bfee95bbSGrant Likely iounmap(gpio); 227bfee95bbSGrant Likely 228bfee95bbSGrant Likely } 229bfee95bbSGrant Likely 230bfee95bbSGrant Likely /* list of the supported boards */ 2319597abe0SAndi Kleen static const char * const board[] __initconst = { 232bfee95bbSGrant Likely "fsl,media5200", 233bfee95bbSGrant Likely NULL 234bfee95bbSGrant Likely }; 235bfee95bbSGrant Likely 236bfee95bbSGrant Likely /* 237bfee95bbSGrant Likely * Called very early, MMU is off, device-tree isn't unflattened 238bfee95bbSGrant Likely */ 239bfee95bbSGrant Likely static int __init media5200_probe(void) 240bfee95bbSGrant Likely { 24156571384SBenjamin Herrenschmidt return of_device_compatible_match(of_root, board); 242bfee95bbSGrant Likely } 243bfee95bbSGrant Likely 244bfee95bbSGrant Likely define_machine(media5200_platform) { 245bfee95bbSGrant Likely .name = "media5200-platform", 246bfee95bbSGrant Likely .probe = media5200_probe, 247bfee95bbSGrant Likely .setup_arch = media5200_setup_arch, 248ba508762SOliver O'Halloran .discover_phbs = mpc52xx_setup_pci, 249bfee95bbSGrant Likely .init = mpc52xx_declare_of_platform_devices, 250bfee95bbSGrant Likely .init_IRQ = media5200_init_irq, 251bfee95bbSGrant Likely .get_irq = mpc52xx_get_irq, 252bfee95bbSGrant Likely .restart = mpc52xx_restart, 253bfee95bbSGrant Likely .calibrate_decr = generic_calibrate_decr, 254bfee95bbSGrant Likely }; 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