1 /*
2  * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
3  *
4  * Author: John Rigby <jrigby@freescale.com>
5  *
6  * Description:
7  * MPC512x Shared code
8  *
9  * This is free software; you can redistribute it and/or modify it
10  * under the terms of the GNU General Public License as published by
11  * the Free Software Foundation; either version 2 of the License, or
12  * (at your option) any later version.
13  */
14 
15 #include <linux/clk.h>
16 #include <linux/kernel.h>
17 #include <linux/io.h>
18 #include <linux/irq.h>
19 #include <linux/of_platform.h>
20 #include <linux/fsl-diu-fb.h>
21 #include <linux/memblock.h>
22 #include <sysdev/fsl_soc.h>
23 
24 #include <asm/cacheflush.h>
25 #include <asm/machdep.h>
26 #include <asm/ipic.h>
27 #include <asm/prom.h>
28 #include <asm/time.h>
29 #include <asm/mpc5121.h>
30 #include <asm/mpc52xx_psc.h>
31 
32 #include "mpc512x.h"
33 
34 static struct mpc512x_reset_module __iomem *reset_module_base;
35 
36 static void __init mpc512x_restart_init(void)
37 {
38 	struct device_node *np;
39 	const char *reset_compat;
40 
41 	reset_compat = mpc512x_select_reset_compat();
42 	np = of_find_compatible_node(NULL, NULL, reset_compat);
43 	if (!np)
44 		return;
45 
46 	reset_module_base = of_iomap(np, 0);
47 	of_node_put(np);
48 }
49 
50 void __noreturn mpc512x_restart(char *cmd)
51 {
52 	if (reset_module_base) {
53 		/* Enable software reset "RSTE" */
54 		out_be32(&reset_module_base->rpr, 0x52535445);
55 		/* Set software hard reset */
56 		out_be32(&reset_module_base->rcr, 0x2);
57 	} else {
58 		pr_err("Restart module not mapped.\n");
59 	}
60 	for (;;)
61 		;
62 }
63 
64 struct fsl_diu_shared_fb {
65 	u8		gamma[0x300];	/* 32-bit aligned! */
66 	struct diu_ad	ad0;		/* 32-bit aligned! */
67 	phys_addr_t	fb_phys;
68 	size_t		fb_len;
69 	bool		in_use;
70 };
71 
72 /* receives a pixel clock spec in pico seconds, adjusts the DIU clock rate */
73 static void mpc512x_set_pixel_clock(unsigned int pixclock)
74 {
75 	struct device_node *np;
76 	struct clk *clk_diu;
77 	unsigned long epsilon, minpixclock, maxpixclock;
78 	unsigned long offset, want, got, delta;
79 
80 	/* lookup and enable the DIU clock */
81 	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
82 	if (!np) {
83 		pr_err("Could not find DIU device tree node.\n");
84 		return;
85 	}
86 	clk_diu = of_clk_get(np, 0);
87 	if (IS_ERR(clk_diu)) {
88 		/* backwards compat with device trees that lack clock specs */
89 		clk_diu = clk_get_sys(np->name, "ipg");
90 	}
91 	of_node_put(np);
92 	if (IS_ERR(clk_diu)) {
93 		pr_err("Could not lookup DIU clock.\n");
94 		return;
95 	}
96 	if (clk_prepare_enable(clk_diu)) {
97 		pr_err("Could not enable DIU clock.\n");
98 		return;
99 	}
100 
101 	/*
102 	 * convert the picoseconds spec into the desired clock rate,
103 	 * determine the acceptable clock range for the monitor (+/- 5%),
104 	 * do the calculation in steps to avoid integer overflow
105 	 */
106 	pr_debug("DIU pixclock in ps - %u\n", pixclock);
107 	pixclock = (1000000000 / pixclock) * 1000;
108 	pr_debug("DIU pixclock freq  - %u\n", pixclock);
109 	epsilon = pixclock / 20; /* pixclock * 0.05 */
110 	pr_debug("DIU deviation      - %lu\n", epsilon);
111 	minpixclock = pixclock - epsilon;
112 	maxpixclock = pixclock + epsilon;
113 	pr_debug("DIU minpixclock    - %lu\n", minpixclock);
114 	pr_debug("DIU maxpixclock    - %lu\n", maxpixclock);
115 
116 	/*
117 	 * check whether the DIU supports the desired pixel clock
118 	 *
119 	 * - simply request the desired clock and see what the
120 	 *   platform's clock driver will make of it, assuming that it
121 	 *   will setup the best approximation of the requested value
122 	 * - try other candidate frequencies in the order of decreasing
123 	 *   preference (i.e. with increasing distance from the desired
124 	 *   pixel clock, and checking the lower frequency before the
125 	 *   higher frequency to not overload the hardware) until the
126 	 *   first match is found -- any potential subsequent match
127 	 *   would only be as good as the former match or typically
128 	 *   would be less preferrable
129 	 *
130 	 * the offset increment of pixelclock divided by 64 is an
131 	 * arbitrary choice -- it's simple to calculate, in the typical
132 	 * case we expect the first check to succeed already, in the
133 	 * worst case seven frequencies get tested (the exact center and
134 	 * three more values each to the left and to the right) before
135 	 * the 5% tolerance window is exceeded, resulting in fast enough
136 	 * execution yet high enough probability of finding a suitable
137 	 * value, while the error rate will be in the order of single
138 	 * percents
139 	 */
140 	for (offset = 0; offset <= epsilon; offset += pixclock / 64) {
141 		want = pixclock - offset;
142 		pr_debug("DIU checking clock - %lu\n", want);
143 		clk_set_rate(clk_diu, want);
144 		got = clk_get_rate(clk_diu);
145 		delta = abs(pixclock - got);
146 		if (delta < epsilon)
147 			break;
148 		if (!offset)
149 			continue;
150 		want = pixclock + offset;
151 		pr_debug("DIU checking clock - %lu\n", want);
152 		clk_set_rate(clk_diu, want);
153 		got = clk_get_rate(clk_diu);
154 		delta = abs(pixclock - got);
155 		if (delta < epsilon)
156 			break;
157 	}
158 	if (offset <= epsilon) {
159 		pr_debug("DIU clock accepted - %lu\n", want);
160 		pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
161 			 pixclock, got, delta, epsilon);
162 		return;
163 	}
164 	pr_warn("DIU pixclock auto search unsuccessful\n");
165 
166 	/*
167 	 * what is the most appropriate action to take when the search
168 	 * for an available pixel clock which is acceptable to the
169 	 * monitor has failed?  disable the DIU (clock) or just provide
170 	 * a "best effort"?  we go with the latter
171 	 */
172 	pr_warn("DIU pixclock best effort fallback (backend's choice)\n");
173 	clk_set_rate(clk_diu, pixclock);
174 	got = clk_get_rate(clk_diu);
175 	delta = abs(pixclock - got);
176 	pr_debug("DIU pixclock want %u, got %lu, delta %lu, eps %lu\n",
177 		 pixclock, got, delta, epsilon);
178 }
179 
180 static enum fsl_diu_monitor_port
181 mpc512x_valid_monitor_port(enum fsl_diu_monitor_port port)
182 {
183 	return FSL_DIU_PORT_DVI;
184 }
185 
186 static struct fsl_diu_shared_fb __attribute__ ((__aligned__(8))) diu_shared_fb;
187 
188 static inline void mpc512x_free_bootmem(struct page *page)
189 {
190 	BUG_ON(PageTail(page));
191 	BUG_ON(page_ref_count(page) > 1);
192 	free_reserved_page(page);
193 }
194 
195 static void mpc512x_release_bootmem(void)
196 {
197 	unsigned long addr = diu_shared_fb.fb_phys & PAGE_MASK;
198 	unsigned long size = diu_shared_fb.fb_len;
199 	unsigned long start, end;
200 
201 	if (diu_shared_fb.in_use) {
202 		start = PFN_UP(addr);
203 		end = PFN_DOWN(addr + size);
204 
205 		for (; start < end; start++)
206 			mpc512x_free_bootmem(pfn_to_page(start));
207 
208 		diu_shared_fb.in_use = false;
209 	}
210 	diu_ops.release_bootmem	= NULL;
211 }
212 
213 /*
214  * Check if DIU was pre-initialized. If so, perform steps
215  * needed to continue displaying through the whole boot process.
216  * Move area descriptor and gamma table elsewhere, they are
217  * destroyed by bootmem allocator otherwise. The frame buffer
218  * address range will be reserved in setup_arch() after bootmem
219  * allocator is up.
220  */
221 static void __init mpc512x_init_diu(void)
222 {
223 	struct device_node *np;
224 	struct diu __iomem *diu_reg;
225 	phys_addr_t desc;
226 	void __iomem *vaddr;
227 	unsigned long mode, pix_fmt, res, bpp;
228 	unsigned long dst;
229 
230 	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-diu");
231 	if (!np) {
232 		pr_err("No DIU node\n");
233 		return;
234 	}
235 
236 	diu_reg = of_iomap(np, 0);
237 	of_node_put(np);
238 	if (!diu_reg) {
239 		pr_err("Can't map DIU\n");
240 		return;
241 	}
242 
243 	mode = in_be32(&diu_reg->diu_mode);
244 	if (mode == MFB_MODE0) {
245 		pr_info("%s: DIU OFF\n", __func__);
246 		goto out;
247 	}
248 
249 	desc = in_be32(&diu_reg->desc[0]);
250 	vaddr = ioremap(desc, sizeof(struct diu_ad));
251 	if (!vaddr) {
252 		pr_err("Can't map DIU area desc.\n");
253 		goto out;
254 	}
255 	memcpy(&diu_shared_fb.ad0, vaddr, sizeof(struct diu_ad));
256 	/* flush fb area descriptor */
257 	dst = (unsigned long)&diu_shared_fb.ad0;
258 	flush_dcache_range(dst, dst + sizeof(struct diu_ad) - 1);
259 
260 	res = in_be32(&diu_reg->disp_size);
261 	pix_fmt = in_le32(vaddr);
262 	bpp = ((pix_fmt >> 16) & 0x3) + 1;
263 	diu_shared_fb.fb_phys = in_le32(vaddr + 4);
264 	diu_shared_fb.fb_len = ((res & 0xfff0000) >> 16) * (res & 0xfff) * bpp;
265 	diu_shared_fb.in_use = true;
266 	iounmap(vaddr);
267 
268 	desc = in_be32(&diu_reg->gamma);
269 	vaddr = ioremap(desc, sizeof(diu_shared_fb.gamma));
270 	if (!vaddr) {
271 		pr_err("Can't map DIU area desc.\n");
272 		diu_shared_fb.in_use = false;
273 		goto out;
274 	}
275 	memcpy(&diu_shared_fb.gamma, vaddr, sizeof(diu_shared_fb.gamma));
276 	/* flush gamma table */
277 	dst = (unsigned long)&diu_shared_fb.gamma;
278 	flush_dcache_range(dst, dst + sizeof(diu_shared_fb.gamma) - 1);
279 
280 	iounmap(vaddr);
281 	out_be32(&diu_reg->gamma, virt_to_phys(&diu_shared_fb.gamma));
282 	out_be32(&diu_reg->desc[1], 0);
283 	out_be32(&diu_reg->desc[2], 0);
284 	out_be32(&diu_reg->desc[0], virt_to_phys(&diu_shared_fb.ad0));
285 
286 out:
287 	iounmap(diu_reg);
288 }
289 
290 static void __init mpc512x_setup_diu(void)
291 {
292 	int ret;
293 
294 	/*
295 	 * We do not allocate and configure new area for bitmap buffer
296 	 * because it would requere copying bitmap data (splash image)
297 	 * and so negatively affect boot time. Instead we reserve the
298 	 * already configured frame buffer area so that it won't be
299 	 * destroyed. The starting address of the area to reserve and
300 	 * also it's length is passed to memblock_reserve(). It will be
301 	 * freed later on first open of fbdev, when splash image is not
302 	 * needed any more.
303 	 */
304 	if (diu_shared_fb.in_use) {
305 		ret = memblock_reserve(diu_shared_fb.fb_phys,
306 				       diu_shared_fb.fb_len);
307 		if (ret) {
308 			pr_err("%s: reserve bootmem failed\n", __func__);
309 			diu_shared_fb.in_use = false;
310 		}
311 	}
312 
313 	diu_ops.set_pixel_clock		= mpc512x_set_pixel_clock;
314 	diu_ops.valid_monitor_port	= mpc512x_valid_monitor_port;
315 	diu_ops.release_bootmem		= mpc512x_release_bootmem;
316 }
317 
318 void __init mpc512x_init_IRQ(void)
319 {
320 	struct device_node *np;
321 
322 	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-ipic");
323 	if (!np)
324 		return;
325 
326 	ipic_init(np, 0);
327 	of_node_put(np);
328 
329 	/*
330 	 * Initialize the default interrupt mapping priorities,
331 	 * in case the boot rom changed something on us.
332 	 */
333 	ipic_set_default_priority();
334 }
335 
336 /*
337  * Nodes to do bus probe on, soc and localbus
338  */
339 static const struct of_device_id of_bus_ids[] __initconst = {
340 	{ .compatible = "fsl,mpc5121-immr", },
341 	{ .compatible = "fsl,mpc5121-localbus", },
342 	{ .compatible = "fsl,mpc5121-mbx", },
343 	{ .compatible = "fsl,mpc5121-nfc", },
344 	{ .compatible = "fsl,mpc5121-sram", },
345 	{ .compatible = "fsl,mpc5121-pci", },
346 	{ .compatible = "gpio-leds", },
347 	{},
348 };
349 
350 static void __init mpc512x_declare_of_platform_devices(void)
351 {
352 	if (of_platform_bus_probe(NULL, of_bus_ids, NULL))
353 		printk(KERN_ERR __FILE__ ": "
354 			"Error while probing of_platform bus\n");
355 }
356 
357 #define DEFAULT_FIFO_SIZE 16
358 
359 const char *mpc512x_select_psc_compat(void)
360 {
361 	if (of_machine_is_compatible("fsl,mpc5121"))
362 		return "fsl,mpc5121-psc";
363 
364 	if (of_machine_is_compatible("fsl,mpc5125"))
365 		return "fsl,mpc5125-psc";
366 
367 	return NULL;
368 }
369 
370 const char *mpc512x_select_reset_compat(void)
371 {
372 	if (of_machine_is_compatible("fsl,mpc5121"))
373 		return "fsl,mpc5121-reset";
374 
375 	if (of_machine_is_compatible("fsl,mpc5125"))
376 		return "fsl,mpc5125-reset";
377 
378 	return NULL;
379 }
380 
381 static unsigned int __init get_fifo_size(struct device_node *np,
382 					 char *prop_name)
383 {
384 	const unsigned int *fp;
385 
386 	fp = of_get_property(np, prop_name, NULL);
387 	if (fp)
388 		return *fp;
389 
390 	pr_warn("no %s property in %pOF node, defaulting to %d\n",
391 		prop_name, np, DEFAULT_FIFO_SIZE);
392 
393 	return DEFAULT_FIFO_SIZE;
394 }
395 
396 #define FIFOC(_base) ((struct mpc512x_psc_fifo __iomem *) \
397 		    ((u32)(_base) + sizeof(struct mpc52xx_psc)))
398 
399 /* Init PSC FIFO space for TX and RX slices */
400 static void __init mpc512x_psc_fifo_init(void)
401 {
402 	struct device_node *np;
403 	void __iomem *psc;
404 	unsigned int tx_fifo_size;
405 	unsigned int rx_fifo_size;
406 	const char *psc_compat;
407 	int fifobase = 0; /* current fifo address in 32 bit words */
408 
409 	psc_compat = mpc512x_select_psc_compat();
410 	if (!psc_compat) {
411 		pr_err("%s: no compatible devices found\n", __func__);
412 		return;
413 	}
414 
415 	for_each_compatible_node(np, NULL, psc_compat) {
416 		tx_fifo_size = get_fifo_size(np, "fsl,tx-fifo-size");
417 		rx_fifo_size = get_fifo_size(np, "fsl,rx-fifo-size");
418 
419 		/* size in register is in 4 byte units */
420 		tx_fifo_size /= 4;
421 		rx_fifo_size /= 4;
422 		if (!tx_fifo_size)
423 			tx_fifo_size = 1;
424 		if (!rx_fifo_size)
425 			rx_fifo_size = 1;
426 
427 		psc = of_iomap(np, 0);
428 		if (!psc) {
429 			pr_err("%s: Can't map %pOF device\n",
430 				__func__, np);
431 			continue;
432 		}
433 
434 		/* FIFO space is 4KiB, check if requested size is available */
435 		if ((fifobase + tx_fifo_size + rx_fifo_size) > 0x1000) {
436 			pr_err("%s: no fifo space available for %pOF\n",
437 				__func__, np);
438 			iounmap(psc);
439 			/*
440 			 * chances are that another device requests less
441 			 * fifo space, so we continue.
442 			 */
443 			continue;
444 		}
445 
446 		/* set tx and rx fifo size registers */
447 		out_be32(&FIFOC(psc)->txsz, (fifobase << 16) | tx_fifo_size);
448 		fifobase += tx_fifo_size;
449 		out_be32(&FIFOC(psc)->rxsz, (fifobase << 16) | rx_fifo_size);
450 		fifobase += rx_fifo_size;
451 
452 		/* reset and enable the slices */
453 		out_be32(&FIFOC(psc)->txcmd, 0x80);
454 		out_be32(&FIFOC(psc)->txcmd, 0x01);
455 		out_be32(&FIFOC(psc)->rxcmd, 0x80);
456 		out_be32(&FIFOC(psc)->rxcmd, 0x01);
457 
458 		iounmap(psc);
459 	}
460 }
461 
462 void __init mpc512x_init_early(void)
463 {
464 	mpc512x_restart_init();
465 	if (IS_ENABLED(CONFIG_FB_FSL_DIU))
466 		mpc512x_init_diu();
467 }
468 
469 void __init mpc512x_init(void)
470 {
471 	mpc5121_clk_init();
472 	mpc512x_declare_of_platform_devices();
473 	mpc512x_psc_fifo_init();
474 }
475 
476 void __init mpc512x_setup_arch(void)
477 {
478 	if (IS_ENABLED(CONFIG_FB_FSL_DIU))
479 		mpc512x_setup_diu();
480 }
481 
482 /**
483  * mpc512x_cs_config - Setup chip select configuration
484  * @cs: chip select number
485  * @val: chip select configuration value
486  *
487  * Perform chip select configuration for devices on LocalPlus Bus.
488  * Intended to dynamically reconfigure the chip select parameters
489  * for configurable devices on the bus.
490  */
491 int mpc512x_cs_config(unsigned int cs, u32 val)
492 {
493 	static struct mpc512x_lpc __iomem *lpc;
494 	struct device_node *np;
495 
496 	if (cs > 7)
497 		return -EINVAL;
498 
499 	if (!lpc) {
500 		np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-lpc");
501 		lpc = of_iomap(np, 0);
502 		of_node_put(np);
503 		if (!lpc)
504 			return -ENOMEM;
505 	}
506 
507 	out_be32(&lpc->cs_cfg[cs], val);
508 	return 0;
509 }
510 EXPORT_SYMBOL(mpc512x_cs_config);
511