1 /* 2 * Copyright (C) 2013 DENX Software Engineering 3 * 4 * Gerhard Sittig, <gsi@denx.de> 5 * 6 * common clock driver support for the MPC512x platform 7 * 8 * This is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/clkdev.h> 18 #include <linux/device.h> 19 #include <linux/errno.h> 20 #include <linux/io.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 24 #include <asm/mpc5121.h> 25 #include <dt-bindings/clock/mpc512x-clock.h> 26 27 #include "mpc512x.h" /* our public mpc5121_clk_init() API */ 28 29 /* helpers to keep the MCLK intermediates "somewhere" in our table */ 30 enum { 31 MCLK_IDX_MUX0, 32 MCLK_IDX_EN0, 33 MCLK_IDX_DIV0, 34 MCLK_MAX_IDX, 35 }; 36 37 #define NR_PSCS 12 38 #define NR_MSCANS 4 39 #define NR_SPDIFS 1 40 #define NR_OUTCLK 4 41 #define NR_MCLKS (NR_PSCS + NR_MSCANS + NR_SPDIFS + NR_OUTCLK) 42 43 /* extend the public set of clocks by adding internal slots for management */ 44 enum { 45 /* arrange for adjacent numbers after the public set */ 46 MPC512x_CLK_START_PRIVATE = MPC512x_CLK_LAST_PUBLIC, 47 /* clocks which aren't announced to the public */ 48 MPC512x_CLK_DDR, 49 MPC512x_CLK_MEM, 50 MPC512x_CLK_IIM, 51 /* intermediates in div+gate combos or fractional dividers */ 52 MPC512x_CLK_DDR_UG, 53 MPC512x_CLK_SDHC_x4, 54 MPC512x_CLK_SDHC_UG, 55 MPC512x_CLK_SDHC2_UG, 56 MPC512x_CLK_DIU_x4, 57 MPC512x_CLK_DIU_UG, 58 MPC512x_CLK_MBX_BUS_UG, 59 MPC512x_CLK_MBX_UG, 60 MPC512x_CLK_MBX_3D_UG, 61 MPC512x_CLK_PCI_UG, 62 MPC512x_CLK_NFC_UG, 63 MPC512x_CLK_LPC_UG, 64 MPC512x_CLK_SPDIF_TX_IN, 65 /* intermediates for the mux+gate+div+mux MCLK generation */ 66 MPC512x_CLK_MCLKS_FIRST, 67 MPC512x_CLK_MCLKS_LAST = MPC512x_CLK_MCLKS_FIRST 68 + NR_MCLKS * MCLK_MAX_IDX, 69 /* internal, symbolic spec for the number of slots */ 70 MPC512x_CLK_LAST_PRIVATE, 71 }; 72 73 /* data required for the OF clock provider registration */ 74 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; 75 static struct clk_onecell_data clk_data; 76 77 /* CCM register access */ 78 static struct mpc512x_ccm __iomem *clkregs; 79 static DEFINE_SPINLOCK(clklock); 80 81 /* SoC variants {{{ */ 82 83 /* 84 * tell SoC variants apart as they are rather similar yet not identical, 85 * cache the result in an enum to not repeatedly run the expensive OF test 86 * 87 * MPC5123 is an MPC5121 without the MBX graphics accelerator 88 * 89 * MPC5125 has many more differences: no MBX, no AXE, no VIU, no SPDIF, 90 * no PATA, no SATA, no PCI, two FECs (of different compatibility name), 91 * only 10 PSCs (of different compatibility name), two SDHCs, different 92 * NFC IP block, output clocks, system PLL status query, different CPMF 93 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet 94 * those differences can get folded into this clock provider support 95 * code and don't warrant a separate highly redundant implementation 96 */ 97 98 static enum soc_type { 99 MPC512x_SOC_MPC5121, 100 MPC512x_SOC_MPC5123, 101 MPC512x_SOC_MPC5125, 102 } soc; 103 104 static void mpc512x_clk_determine_soc(void) 105 { 106 if (of_machine_is_compatible("fsl,mpc5121")) { 107 soc = MPC512x_SOC_MPC5121; 108 return; 109 } 110 if (of_machine_is_compatible("fsl,mpc5123")) { 111 soc = MPC512x_SOC_MPC5123; 112 return; 113 } 114 if (of_machine_is_compatible("fsl,mpc5125")) { 115 soc = MPC512x_SOC_MPC5125; 116 return; 117 } 118 } 119 120 static bool soc_has_mbx(void) 121 { 122 if (soc == MPC512x_SOC_MPC5121) 123 return true; 124 return false; 125 } 126 127 static bool soc_has_axe(void) 128 { 129 if (soc == MPC512x_SOC_MPC5125) 130 return false; 131 return true; 132 } 133 134 static bool soc_has_viu(void) 135 { 136 if (soc == MPC512x_SOC_MPC5125) 137 return false; 138 return true; 139 } 140 141 static bool soc_has_spdif(void) 142 { 143 if (soc == MPC512x_SOC_MPC5125) 144 return false; 145 return true; 146 } 147 148 static bool soc_has_pata(void) 149 { 150 if (soc == MPC512x_SOC_MPC5125) 151 return false; 152 return true; 153 } 154 155 static bool soc_has_sata(void) 156 { 157 if (soc == MPC512x_SOC_MPC5125) 158 return false; 159 return true; 160 } 161 162 static bool soc_has_pci(void) 163 { 164 if (soc == MPC512x_SOC_MPC5125) 165 return false; 166 return true; 167 } 168 169 static bool soc_has_fec2(void) 170 { 171 if (soc == MPC512x_SOC_MPC5125) 172 return true; 173 return false; 174 } 175 176 static int soc_max_pscnum(void) 177 { 178 if (soc == MPC512x_SOC_MPC5125) 179 return 10; 180 return 12; 181 } 182 183 static bool soc_has_sdhc2(void) 184 { 185 if (soc == MPC512x_SOC_MPC5125) 186 return true; 187 return false; 188 } 189 190 static bool soc_has_nfc_5125(void) 191 { 192 if (soc == MPC512x_SOC_MPC5125) 193 return true; 194 return false; 195 } 196 197 static bool soc_has_outclk(void) 198 { 199 if (soc == MPC512x_SOC_MPC5125) 200 return true; 201 return false; 202 } 203 204 static bool soc_has_cpmf_0_bypass(void) 205 { 206 if (soc == MPC512x_SOC_MPC5125) 207 return true; 208 return false; 209 } 210 211 static bool soc_has_mclk_mux0_canin(void) 212 { 213 if (soc == MPC512x_SOC_MPC5125) 214 return true; 215 return false; 216 } 217 218 /* }}} SoC variants */ 219 /* common clk API wrappers {{{ */ 220 221 /* convenience wrappers around the common clk API */ 222 static inline struct clk *mpc512x_clk_fixed(const char *name, int rate) 223 { 224 return clk_register_fixed_rate(NULL, name, NULL, 0, rate); 225 } 226 227 static inline struct clk *mpc512x_clk_factor( 228 const char *name, const char *parent_name, 229 int mul, int div) 230 { 231 int clkflags; 232 233 clkflags = CLK_SET_RATE_PARENT; 234 return clk_register_fixed_factor(NULL, name, parent_name, clkflags, 235 mul, div); 236 } 237 238 static inline struct clk *mpc512x_clk_divider( 239 const char *name, const char *parent_name, u8 clkflags, 240 u32 __iomem *reg, u8 pos, u8 len, int divflags) 241 { 242 divflags |= CLK_DIVIDER_BIG_ENDIAN; 243 return clk_register_divider(NULL, name, parent_name, clkflags, 244 reg, pos, len, divflags, &clklock); 245 } 246 247 static inline struct clk *mpc512x_clk_divtable( 248 const char *name, const char *parent_name, 249 u32 __iomem *reg, u8 pos, u8 len, 250 const struct clk_div_table *divtab) 251 { 252 u8 divflags; 253 254 divflags = CLK_DIVIDER_BIG_ENDIAN; 255 return clk_register_divider_table(NULL, name, parent_name, 0, 256 reg, pos, len, divflags, 257 divtab, &clklock); 258 } 259 260 static inline struct clk *mpc512x_clk_gated( 261 const char *name, const char *parent_name, 262 u32 __iomem *reg, u8 pos) 263 { 264 int clkflags; 265 u8 gateflags; 266 267 clkflags = CLK_SET_RATE_PARENT; 268 gateflags = CLK_GATE_BIG_ENDIAN; 269 return clk_register_gate(NULL, name, parent_name, clkflags, 270 reg, pos, gateflags, &clklock); 271 } 272 273 static inline struct clk *mpc512x_clk_muxed(const char *name, 274 const char **parent_names, int parent_count, 275 u32 __iomem *reg, u8 pos, u8 len) 276 { 277 int clkflags; 278 u8 muxflags; 279 280 clkflags = CLK_SET_RATE_PARENT; 281 muxflags = CLK_MUX_BIG_ENDIAN; 282 return clk_register_mux(NULL, name, 283 parent_names, parent_count, clkflags, 284 reg, pos, len, muxflags, &clklock); 285 } 286 287 /* }}} common clk API wrappers */ 288 289 /* helper to isolate a bit field from a register */ 290 static inline int get_bit_field(uint32_t __iomem *reg, uint8_t pos, uint8_t len) 291 { 292 uint32_t val; 293 294 val = in_be32(reg); 295 val >>= pos; 296 val &= (1 << len) - 1; 297 return val; 298 } 299 300 /* get the SPMF and translate it into the "sys pll" multiplier */ 301 static int get_spmf_mult(void) 302 { 303 static int spmf_to_mult[] = { 304 68, 1, 12, 16, 20, 24, 28, 32, 305 36, 40, 44, 48, 52, 56, 60, 64, 306 }; 307 int spmf; 308 309 spmf = get_bit_field(&clkregs->spmr, 24, 4); 310 return spmf_to_mult[spmf]; 311 } 312 313 /* 314 * get the SYS_DIV value and translate it into a divide factor 315 * 316 * values returned from here are a multiple of the real factor since the 317 * divide ratio is fractional 318 */ 319 static int get_sys_div_x2(void) 320 { 321 static int sysdiv_code_to_x2[] = { 322 4, 5, 6, 7, 8, 9, 10, 14, 323 12, 16, 18, 22, 20, 24, 26, 30, 324 28, 32, 34, 38, 36, 40, 42, 46, 325 44, 48, 50, 54, 52, 56, 58, 62, 326 60, 64, 66, 327 }; 328 int divcode; 329 330 divcode = get_bit_field(&clkregs->scfr2, 26, 6); 331 return sysdiv_code_to_x2[divcode]; 332 } 333 334 /* 335 * get the CPMF value and translate it into a multiplier factor 336 * 337 * values returned from here are a multiple of the real factor since the 338 * multiplier ratio is fractional 339 */ 340 static int get_cpmf_mult_x2(void) 341 { 342 static int cpmf_to_mult_x36[] = { 343 /* 0b000 is "times 36" */ 344 72, 2, 2, 3, 4, 5, 6, 7, 345 }; 346 static int cpmf_to_mult_0by[] = { 347 /* 0b000 is "bypass" */ 348 2, 2, 2, 3, 4, 5, 6, 7, 349 }; 350 351 int *cpmf_to_mult; 352 int cpmf; 353 354 cpmf = get_bit_field(&clkregs->spmr, 16, 4); 355 if (soc_has_cpmf_0_bypass()) 356 cpmf_to_mult = cpmf_to_mult_0by; 357 else 358 cpmf_to_mult = cpmf_to_mult_x36; 359 return cpmf_to_mult[cpmf]; 360 } 361 362 /* 363 * some of the clock dividers do scale in a linear way, yet not all of 364 * their bit combinations are legal; use a divider table to get a 365 * resulting set of applicable divider values 366 */ 367 368 /* applies to the IPS_DIV, and PCI_DIV values */ 369 static const struct clk_div_table divtab_2346[] = { 370 { .val = 2, .div = 2, }, 371 { .val = 3, .div = 3, }, 372 { .val = 4, .div = 4, }, 373 { .val = 6, .div = 6, }, 374 { .div = 0, }, 375 }; 376 377 /* applies to the MBX_DIV, LPC_DIV, and NFC_DIV values */ 378 static const struct clk_div_table divtab_1234[] = { 379 { .val = 1, .div = 1, }, 380 { .val = 2, .div = 2, }, 381 { .val = 3, .div = 3, }, 382 { .val = 4, .div = 4, }, 383 { .div = 0, }, 384 }; 385 386 static int get_freq_from_dt(char *propname) 387 { 388 struct device_node *np; 389 const unsigned int *prop; 390 int val; 391 392 val = 0; 393 np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-immr"); 394 if (np) { 395 prop = of_get_property(np, propname, NULL); 396 if (prop) 397 val = *prop; 398 of_node_put(np); 399 } 400 return val; 401 } 402 403 static void mpc512x_clk_preset_data(void) 404 { 405 size_t i; 406 407 for (i = 0; i < ARRAY_SIZE(clks); i++) 408 clks[i] = ERR_PTR(-ENODEV); 409 } 410 411 /* 412 * - receives the "bus frequency" from the caller (that's the IPS clock 413 * rate, the historical source of clock information) 414 * - fetches the system PLL multiplier and divider values as well as the 415 * IPS divider value from hardware 416 * - determines the REF clock rate either from the XTAL/OSC spec (if 417 * there is a device tree node describing the oscillator) or from the 418 * IPS bus clock (supported for backwards compatibility, such that 419 * setups without XTAL/OSC specs keep working) 420 * - creates the "ref" clock item in the clock tree, such that 421 * subsequent code can create the remainder of the hierarchy (REF -> 422 * SYS -> CSB -> IPS) from the REF clock rate and the returned mul/div 423 * values 424 */ 425 static void mpc512x_clk_setup_ref_clock(struct device_node *np, int bus_freq, 426 int *sys_mul, int *sys_div, 427 int *ips_div) 428 { 429 struct clk *osc_clk; 430 int calc_freq; 431 432 /* fetch mul/div factors from the hardware */ 433 *sys_mul = get_spmf_mult(); 434 *sys_mul *= 2; /* compensate for the fractional divider */ 435 *sys_div = get_sys_div_x2(); 436 *ips_div = get_bit_field(&clkregs->scfr1, 23, 3); 437 438 /* lookup the oscillator clock for its rate */ 439 osc_clk = of_clk_get_by_name(np, "osc"); 440 441 /* 442 * either descend from OSC to REF (and in bypassing verify the 443 * IPS rate), or backtrack from IPS and multiplier values that 444 * were fetched from hardware to REF and thus to the OSC value 445 * 446 * in either case the REF clock gets created here and the 447 * remainder of the clock tree can get spanned from there 448 */ 449 if (!IS_ERR(osc_clk)) { 450 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); 451 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); 452 calc_freq *= *sys_mul; 453 calc_freq /= *sys_div; 454 calc_freq /= 2; 455 calc_freq /= *ips_div; 456 if (bus_freq && calc_freq != bus_freq) 457 pr_warn("calc rate %d != OF spec %d\n", 458 calc_freq, bus_freq); 459 } else { 460 calc_freq = bus_freq; /* start with IPS */ 461 calc_freq *= *ips_div; /* IPS -> CSB */ 462 calc_freq *= 2; /* CSB -> SYS */ 463 calc_freq *= *sys_div; /* SYS -> PLL out */ 464 calc_freq /= *sys_mul; /* PLL out -> REF == OSC */ 465 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); 466 } 467 } 468 469 /* MCLK helpers {{{ */ 470 471 /* 472 * helper code for the MCLK subtree setup 473 * 474 * the overview in section 5.2.4 of the MPC5121e Reference Manual rev4 475 * suggests that all instances of the "PSC clock generation" are equal, 476 * and that one might re-use the PSC setup for MSCAN clock generation 477 * (section 5.2.5) as well, at least the logic if not the data for 478 * description 479 * 480 * the details (starting at page 5-20) show differences in the specific 481 * inputs of the first mux stage ("can clk in", "spdif tx"), and the 482 * factual non-availability of the second mux stage (it's present yet 483 * only one input is valid) 484 * 485 * the MSCAN clock related registers (starting at page 5-35) all 486 * reference "spdif clk" at the first mux stage and don't mention any 487 * "can clk" at all, which somehow is unexpected 488 * 489 * TODO re-check the document, and clarify whether the RM is correct in 490 * the overview or in the details, and whether the difference is a 491 * clipboard induced error or results from chip revisions 492 * 493 * it turns out that the RM rev4 as of 2012-06 talks about "can" for the 494 * PSCs while RM rev3 as of 2008-10 talks about "spdif", so I guess that 495 * first a doc update is required which better reflects reality in the 496 * SoC before the implementation should follow while no questions remain 497 */ 498 499 /* 500 * note that this declaration raises a checkpatch warning, but 501 * it's the very data type dictated by <linux/clk-provider.h>, 502 * "fixing" this warning will break compilation 503 */ 504 static const char *parent_names_mux0_spdif[] = { 505 "sys", "ref", "psc-mclk-in", "spdif-tx", 506 }; 507 508 static const char *parent_names_mux0_canin[] = { 509 "sys", "ref", "psc-mclk-in", "can-clk-in", 510 }; 511 512 enum mclk_type { 513 MCLK_TYPE_PSC, 514 MCLK_TYPE_MSCAN, 515 MCLK_TYPE_SPDIF, 516 MCLK_TYPE_OUTCLK, 517 }; 518 519 struct mclk_setup_data { 520 enum mclk_type type; 521 bool has_mclk1; 522 const char *name_mux0; 523 const char *name_en0; 524 const char *name_div0; 525 const char *parent_names_mux1[2]; 526 const char *name_mclk; 527 }; 528 529 #define MCLK_SETUP_DATA_PSC(id) { \ 530 MCLK_TYPE_PSC, 0, \ 531 "psc" #id "-mux0", \ 532 "psc" #id "-en0", \ 533 "psc" #id "_mclk_div", \ 534 { "psc" #id "_mclk_div", "dummy", }, \ 535 "psc" #id "_mclk", \ 536 } 537 538 #define MCLK_SETUP_DATA_MSCAN(id) { \ 539 MCLK_TYPE_MSCAN, 0, \ 540 "mscan" #id "-mux0", \ 541 "mscan" #id "-en0", \ 542 "mscan" #id "_mclk_div", \ 543 { "mscan" #id "_mclk_div", "dummy", }, \ 544 "mscan" #id "_mclk", \ 545 } 546 547 #define MCLK_SETUP_DATA_SPDIF { \ 548 MCLK_TYPE_SPDIF, 1, \ 549 "spdif-mux0", \ 550 "spdif-en0", \ 551 "spdif_mclk_div", \ 552 { "spdif_mclk_div", "spdif-rx", }, \ 553 "spdif_mclk", \ 554 } 555 556 #define MCLK_SETUP_DATA_OUTCLK(id) { \ 557 MCLK_TYPE_OUTCLK, 0, \ 558 "out" #id "-mux0", \ 559 "out" #id "-en0", \ 560 "out" #id "_mclk_div", \ 561 { "out" #id "_mclk_div", "dummy", }, \ 562 "out" #id "_clk", \ 563 } 564 565 static struct mclk_setup_data mclk_psc_data[] = { 566 MCLK_SETUP_DATA_PSC(0), 567 MCLK_SETUP_DATA_PSC(1), 568 MCLK_SETUP_DATA_PSC(2), 569 MCLK_SETUP_DATA_PSC(3), 570 MCLK_SETUP_DATA_PSC(4), 571 MCLK_SETUP_DATA_PSC(5), 572 MCLK_SETUP_DATA_PSC(6), 573 MCLK_SETUP_DATA_PSC(7), 574 MCLK_SETUP_DATA_PSC(8), 575 MCLK_SETUP_DATA_PSC(9), 576 MCLK_SETUP_DATA_PSC(10), 577 MCLK_SETUP_DATA_PSC(11), 578 }; 579 580 static struct mclk_setup_data mclk_mscan_data[] = { 581 MCLK_SETUP_DATA_MSCAN(0), 582 MCLK_SETUP_DATA_MSCAN(1), 583 MCLK_SETUP_DATA_MSCAN(2), 584 MCLK_SETUP_DATA_MSCAN(3), 585 }; 586 587 static struct mclk_setup_data mclk_spdif_data[] = { 588 MCLK_SETUP_DATA_SPDIF, 589 }; 590 591 static struct mclk_setup_data mclk_outclk_data[] = { 592 MCLK_SETUP_DATA_OUTCLK(0), 593 MCLK_SETUP_DATA_OUTCLK(1), 594 MCLK_SETUP_DATA_OUTCLK(2), 595 MCLK_SETUP_DATA_OUTCLK(3), 596 }; 597 598 /* setup the MCLK clock subtree of an individual PSC/MSCAN/SPDIF */ 599 static void mpc512x_clk_setup_mclk(struct mclk_setup_data *entry, size_t idx) 600 { 601 size_t clks_idx_pub, clks_idx_int; 602 u32 __iomem *mccr_reg; /* MCLK control register (mux, en, div) */ 603 int div; 604 605 /* derive a few parameters from the component type and index */ 606 switch (entry->type) { 607 case MCLK_TYPE_PSC: 608 clks_idx_pub = MPC512x_CLK_PSC0_MCLK + idx; 609 clks_idx_int = MPC512x_CLK_MCLKS_FIRST 610 + (idx) * MCLK_MAX_IDX; 611 mccr_reg = &clkregs->psc_ccr[idx]; 612 break; 613 case MCLK_TYPE_MSCAN: 614 clks_idx_pub = MPC512x_CLK_MSCAN0_MCLK + idx; 615 clks_idx_int = MPC512x_CLK_MCLKS_FIRST 616 + (NR_PSCS + idx) * MCLK_MAX_IDX; 617 mccr_reg = &clkregs->mscan_ccr[idx]; 618 break; 619 case MCLK_TYPE_SPDIF: 620 clks_idx_pub = MPC512x_CLK_SPDIF_MCLK; 621 clks_idx_int = MPC512x_CLK_MCLKS_FIRST 622 + (NR_PSCS + NR_MSCANS) * MCLK_MAX_IDX; 623 mccr_reg = &clkregs->spccr; 624 break; 625 case MCLK_TYPE_OUTCLK: 626 clks_idx_pub = MPC512x_CLK_OUT0_CLK + idx; 627 clks_idx_int = MPC512x_CLK_MCLKS_FIRST 628 + (NR_PSCS + NR_MSCANS + NR_SPDIFS + idx) 629 * MCLK_MAX_IDX; 630 mccr_reg = &clkregs->out_ccr[idx]; 631 break; 632 default: 633 return; 634 } 635 636 /* 637 * this was grabbed from the PPC_CLOCK implementation, which 638 * enforced a specific MCLK divider while the clock was gated 639 * during setup (that's a documented hardware requirement) 640 * 641 * the PPC_CLOCK implementation might even have violated the 642 * "MCLK <= IPS" constraint, the fixed divider value of 1 643 * results in a divider of 2 and thus MCLK = SYS/2 which equals 644 * CSB which is greater than IPS; the serial port setup may have 645 * adjusted the divider which the clock setup might have left in 646 * an undesirable state 647 * 648 * initial setup is: 649 * - MCLK 0 from SYS 650 * - MCLK DIV such to not exceed the IPS clock 651 * - MCLK 0 enabled 652 * - MCLK 1 from MCLK DIV 653 */ 654 div = clk_get_rate(clks[MPC512x_CLK_SYS]); 655 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); 656 out_be32(mccr_reg, (0 << 16)); 657 out_be32(mccr_reg, (0 << 16) | ((div - 1) << 17)); 658 out_be32(mccr_reg, (1 << 16) | ((div - 1) << 17)); 659 660 /* 661 * create the 'struct clk' items of the MCLK's clock subtree 662 * 663 * note that by design we always create all nodes and won't take 664 * shortcuts here, because 665 * - the "internal" MCLK_DIV and MCLK_OUT signal in turn are 666 * selectable inputs to the CFM while those who "actually use" 667 * the PSC/MSCAN/SPDIF (serial drivers et al) need the MCLK 668 * for their bitrate 669 * - in the absence of "aliases" for clocks we need to create 670 * individial 'struct clk' items for whatever might get 671 * referenced or looked up, even if several of those items are 672 * identical from the logical POV (their rate value) 673 * - for easier future maintenance and for better reflection of 674 * the SoC's documentation, it appears appropriate to generate 675 * clock items even for those muxers which actually are NOPs 676 * (those with two inputs of which one is reserved) 677 */ 678 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( 679 entry->name_mux0, 680 soc_has_mclk_mux0_canin() 681 ? &parent_names_mux0_canin[0] 682 : &parent_names_mux0_spdif[0], 683 ARRAY_SIZE(parent_names_mux0_spdif), 684 mccr_reg, 14, 2); 685 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated( 686 entry->name_en0, entry->name_mux0, 687 mccr_reg, 16); 688 clks[clks_idx_int + MCLK_IDX_DIV0] = mpc512x_clk_divider( 689 entry->name_div0, 690 entry->name_en0, CLK_SET_RATE_GATE, 691 mccr_reg, 17, 15, 0); 692 if (entry->has_mclk1) { 693 clks[clks_idx_pub] = mpc512x_clk_muxed( 694 entry->name_mclk, 695 &entry->parent_names_mux1[0], 696 ARRAY_SIZE(entry->parent_names_mux1), 697 mccr_reg, 7, 1); 698 } else { 699 clks[clks_idx_pub] = mpc512x_clk_factor( 700 entry->name_mclk, 701 entry->parent_names_mux1[0], 702 1, 1); 703 } 704 } 705 706 /* }}} MCLK helpers */ 707 708 static void mpc512x_clk_setup_clock_tree(struct device_node *np, int busfreq) 709 { 710 int sys_mul, sys_div, ips_div; 711 int mul, div; 712 size_t mclk_idx; 713 int freq; 714 715 /* 716 * developer's notes: 717 * - consider whether to handle clocks which have both gates and 718 * dividers via intermediates or by means of composites 719 * - fractional dividers appear to not map well to composites 720 * since they can be seen as a fixed multiplier and an 721 * adjustable divider, while composites can only combine at 722 * most one of a mux, div, and gate each into one 'struct clk' 723 * item 724 * - PSC/MSCAN/SPDIF clock generation OTOH already is very 725 * specific and cannot get mapped to composites (at least not 726 * a single one, maybe two of them, but then some of these 727 * intermediate clock signals get referenced elsewhere (e.g. 728 * in the clock frequency measurement, CFM) and thus need 729 * publicly available names 730 * - the current source layout appropriately reflects the 731 * hardware setup, and it works, so it's questionable whether 732 * further changes will result in big enough a benefit 733 */ 734 735 /* regardless of whether XTAL/OSC exists, have REF created */ 736 mpc512x_clk_setup_ref_clock(np, busfreq, &sys_mul, &sys_div, &ips_div); 737 738 /* now setup the REF -> SYS -> CSB -> IPS hierarchy */ 739 clks[MPC512x_CLK_SYS] = mpc512x_clk_factor("sys", "ref", 740 sys_mul, sys_div); 741 clks[MPC512x_CLK_CSB] = mpc512x_clk_factor("csb", "sys", 1, 2); 742 clks[MPC512x_CLK_IPS] = mpc512x_clk_divtable("ips", "csb", 743 &clkregs->scfr1, 23, 3, 744 divtab_2346); 745 /* now setup anything below SYS and CSB and IPS */ 746 747 clks[MPC512x_CLK_DDR_UG] = mpc512x_clk_factor("ddr-ug", "sys", 1, 2); 748 749 /* 750 * the Reference Manual discusses that for SDHC only even divide 751 * ratios are supported because clock domain synchronization 752 * between 'per' and 'ipg' is broken; 753 * keep the divider's bit 0 cleared (per reset value), and only 754 * allow to setup the divider's bits 7:1, which results in that 755 * only even divide ratios can get configured upon rate changes; 756 * keep the "x4" name because this bit shift hack is an internal 757 * implementation detail, the "fractional divider with quarters" 758 * semantics remains 759 */ 760 clks[MPC512x_CLK_SDHC_x4] = mpc512x_clk_factor("sdhc-x4", "csb", 2, 1); 761 clks[MPC512x_CLK_SDHC_UG] = mpc512x_clk_divider("sdhc-ug", "sdhc-x4", 0, 762 &clkregs->scfr2, 1, 7, 763 CLK_DIVIDER_ONE_BASED); 764 if (soc_has_sdhc2()) { 765 clks[MPC512x_CLK_SDHC2_UG] = mpc512x_clk_divider( 766 "sdhc2-ug", "sdhc-x4", 0, &clkregs->scfr2, 767 9, 7, CLK_DIVIDER_ONE_BASED); 768 } 769 770 clks[MPC512x_CLK_DIU_x4] = mpc512x_clk_factor("diu-x4", "csb", 4, 1); 771 clks[MPC512x_CLK_DIU_UG] = mpc512x_clk_divider("diu-ug", "diu-x4", 0, 772 &clkregs->scfr1, 0, 8, 773 CLK_DIVIDER_ONE_BASED); 774 775 /* 776 * the "power architecture PLL" was setup from data which was 777 * sampled from the reset config word, at this point in time the 778 * configuration can be considered fixed and read only (i.e. no 779 * longer adjustable, or no longer in need of adjustment), which 780 * is why we don't register a PLL here but assume fixed factors 781 */ 782 mul = get_cpmf_mult_x2(); 783 div = 2; /* compensate for the fractional factor */ 784 clks[MPC512x_CLK_E300] = mpc512x_clk_factor("e300", "csb", mul, div); 785 786 if (soc_has_mbx()) { 787 clks[MPC512x_CLK_MBX_BUS_UG] = mpc512x_clk_factor( 788 "mbx-bus-ug", "csb", 1, 2); 789 clks[MPC512x_CLK_MBX_UG] = mpc512x_clk_divtable( 790 "mbx-ug", "mbx-bus-ug", &clkregs->scfr1, 791 14, 3, divtab_1234); 792 clks[MPC512x_CLK_MBX_3D_UG] = mpc512x_clk_factor( 793 "mbx-3d-ug", "mbx-ug", 1, 1); 794 } 795 if (soc_has_pci()) { 796 clks[MPC512x_CLK_PCI_UG] = mpc512x_clk_divtable( 797 "pci-ug", "csb", &clkregs->scfr1, 798 20, 3, divtab_2346); 799 } 800 if (soc_has_nfc_5125()) { 801 /* 802 * XXX TODO implement 5125 NFC clock setup logic, 803 * with high/low period counters in clkregs->scfr3, 804 * currently there are no users so it's ENOIMPL 805 */ 806 clks[MPC512x_CLK_NFC_UG] = ERR_PTR(-ENOTSUPP); 807 } else { 808 clks[MPC512x_CLK_NFC_UG] = mpc512x_clk_divtable( 809 "nfc-ug", "ips", &clkregs->scfr1, 810 8, 3, divtab_1234); 811 } 812 clks[MPC512x_CLK_LPC_UG] = mpc512x_clk_divtable("lpc-ug", "ips", 813 &clkregs->scfr1, 11, 3, 814 divtab_1234); 815 816 clks[MPC512x_CLK_LPC] = mpc512x_clk_gated("lpc", "lpc-ug", 817 &clkregs->sccr1, 30); 818 clks[MPC512x_CLK_NFC] = mpc512x_clk_gated("nfc", "nfc-ug", 819 &clkregs->sccr1, 29); 820 if (soc_has_pata()) { 821 clks[MPC512x_CLK_PATA] = mpc512x_clk_gated( 822 "pata", "ips", &clkregs->sccr1, 28); 823 } 824 /* for PSCs there is a "registers" gate and a bitrate MCLK subtree */ 825 for (mclk_idx = 0; mclk_idx < soc_max_pscnum(); mclk_idx++) { 826 char name[12]; 827 snprintf(name, sizeof(name), "psc%d", mclk_idx); 828 clks[MPC512x_CLK_PSC0 + mclk_idx] = mpc512x_clk_gated( 829 name, "ips", &clkregs->sccr1, 27 - mclk_idx); 830 mpc512x_clk_setup_mclk(&mclk_psc_data[mclk_idx], mclk_idx); 831 } 832 clks[MPC512x_CLK_PSC_FIFO] = mpc512x_clk_gated("psc-fifo", "ips", 833 &clkregs->sccr1, 15); 834 if (soc_has_sata()) { 835 clks[MPC512x_CLK_SATA] = mpc512x_clk_gated( 836 "sata", "ips", &clkregs->sccr1, 14); 837 } 838 clks[MPC512x_CLK_FEC] = mpc512x_clk_gated("fec", "ips", 839 &clkregs->sccr1, 13); 840 if (soc_has_pci()) { 841 clks[MPC512x_CLK_PCI] = mpc512x_clk_gated( 842 "pci", "pci-ug", &clkregs->sccr1, 11); 843 } 844 clks[MPC512x_CLK_DDR] = mpc512x_clk_gated("ddr", "ddr-ug", 845 &clkregs->sccr1, 10); 846 if (soc_has_fec2()) { 847 clks[MPC512x_CLK_FEC2] = mpc512x_clk_gated( 848 "fec2", "ips", &clkregs->sccr1, 9); 849 } 850 851 clks[MPC512x_CLK_DIU] = mpc512x_clk_gated("diu", "diu-ug", 852 &clkregs->sccr2, 31); 853 if (soc_has_axe()) { 854 clks[MPC512x_CLK_AXE] = mpc512x_clk_gated( 855 "axe", "csb", &clkregs->sccr2, 30); 856 } 857 clks[MPC512x_CLK_MEM] = mpc512x_clk_gated("mem", "ips", 858 &clkregs->sccr2, 29); 859 clks[MPC512x_CLK_USB1] = mpc512x_clk_gated("usb1", "csb", 860 &clkregs->sccr2, 28); 861 clks[MPC512x_CLK_USB2] = mpc512x_clk_gated("usb2", "csb", 862 &clkregs->sccr2, 27); 863 clks[MPC512x_CLK_I2C] = mpc512x_clk_gated("i2c", "ips", 864 &clkregs->sccr2, 26); 865 /* MSCAN differs from PSC with just one gate for multiple components */ 866 clks[MPC512x_CLK_BDLC] = mpc512x_clk_gated("bdlc", "ips", 867 &clkregs->sccr2, 25); 868 for (mclk_idx = 0; mclk_idx < ARRAY_SIZE(mclk_mscan_data); mclk_idx++) 869 mpc512x_clk_setup_mclk(&mclk_mscan_data[mclk_idx], mclk_idx); 870 clks[MPC512x_CLK_SDHC] = mpc512x_clk_gated("sdhc", "sdhc-ug", 871 &clkregs->sccr2, 24); 872 /* there is only one SPDIF component, which shares MCLK support code */ 873 if (soc_has_spdif()) { 874 clks[MPC512x_CLK_SPDIF] = mpc512x_clk_gated( 875 "spdif", "ips", &clkregs->sccr2, 23); 876 mpc512x_clk_setup_mclk(&mclk_spdif_data[0], 0); 877 } 878 if (soc_has_mbx()) { 879 clks[MPC512x_CLK_MBX_BUS] = mpc512x_clk_gated( 880 "mbx-bus", "mbx-bus-ug", &clkregs->sccr2, 22); 881 clks[MPC512x_CLK_MBX] = mpc512x_clk_gated( 882 "mbx", "mbx-ug", &clkregs->sccr2, 21); 883 clks[MPC512x_CLK_MBX_3D] = mpc512x_clk_gated( 884 "mbx-3d", "mbx-3d-ug", &clkregs->sccr2, 20); 885 } 886 clks[MPC512x_CLK_IIM] = mpc512x_clk_gated("iim", "csb", 887 &clkregs->sccr2, 19); 888 if (soc_has_viu()) { 889 clks[MPC512x_CLK_VIU] = mpc512x_clk_gated( 890 "viu", "csb", &clkregs->sccr2, 18); 891 } 892 if (soc_has_sdhc2()) { 893 clks[MPC512x_CLK_SDHC2] = mpc512x_clk_gated( 894 "sdhc-2", "sdhc2-ug", &clkregs->sccr2, 17); 895 } 896 897 if (soc_has_outclk()) { 898 size_t idx; /* used as mclk_idx, just to trim line length */ 899 for (idx = 0; idx < ARRAY_SIZE(mclk_outclk_data); idx++) 900 mpc512x_clk_setup_mclk(&mclk_outclk_data[idx], idx); 901 } 902 903 /* 904 * externally provided clocks (when implemented in hardware, 905 * device tree may specify values which otherwise were unknown) 906 */ 907 freq = get_freq_from_dt("psc_mclk_in"); 908 if (!freq) 909 freq = 25000000; 910 clks[MPC512x_CLK_PSC_MCLK_IN] = mpc512x_clk_fixed("psc_mclk_in", freq); 911 if (soc_has_mclk_mux0_canin()) { 912 freq = get_freq_from_dt("can_clk_in"); 913 clks[MPC512x_CLK_CAN_CLK_IN] = mpc512x_clk_fixed( 914 "can_clk_in", freq); 915 } else { 916 freq = get_freq_from_dt("spdif_tx_in"); 917 clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed( 918 "spdif_tx_in", freq); 919 freq = get_freq_from_dt("spdif_rx_in"); 920 clks[MPC512x_CLK_SPDIF_TX_IN] = mpc512x_clk_fixed( 921 "spdif_rx_in", freq); 922 } 923 924 /* fixed frequency for AC97, always 24.567MHz */ 925 clks[MPC512x_CLK_AC97] = mpc512x_clk_fixed("ac97", 24567000); 926 927 /* 928 * pre-enable those "internal" clock items which never get 929 * claimed by any peripheral driver, to not have the clock 930 * subsystem disable them late at startup 931 */ 932 clk_prepare_enable(clks[MPC512x_CLK_DUMMY]); 933 clk_prepare_enable(clks[MPC512x_CLK_E300]); /* PowerPC CPU */ 934 clk_prepare_enable(clks[MPC512x_CLK_DDR]); /* DRAM */ 935 clk_prepare_enable(clks[MPC512x_CLK_MEM]); /* SRAM */ 936 clk_prepare_enable(clks[MPC512x_CLK_IPS]); /* SoC periph */ 937 clk_prepare_enable(clks[MPC512x_CLK_LPC]); /* boot media */ 938 } 939 940 /* 941 * registers the set of public clocks (those listed in the dt-bindings/ 942 * header file) for OF lookups, keeps the intermediates private to us 943 */ 944 static void mpc5121_clk_register_of_provider(struct device_node *np) 945 { 946 clk_data.clks = clks; 947 clk_data.clk_num = MPC512x_CLK_LAST_PUBLIC + 1; /* _not_ ARRAY_SIZE() */ 948 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); 949 } 950 951 /* 952 * temporary support for the period of time between introduction of CCF 953 * support and the adjustment of peripheral drivers to OF based lookups 954 */ 955 static void mpc5121_clk_provide_migration_support(void) 956 { 957 958 /* 959 * pre-enable those clock items which are not yet appropriately 960 * acquired by their peripheral driver 961 * 962 * the PCI clock cannot get acquired by its peripheral driver, 963 * because for this platform the driver won't probe(), instead 964 * initialization is done from within the .setup_arch() routine 965 * at a point in time where the clock provider has not been 966 * setup yet and thus isn't available yet 967 * 968 * so we "pre-enable" the clock here, to not have the clock 969 * subsystem automatically disable this item in a late init call 970 * 971 * this PCI clock pre-enable workaround only applies when there 972 * are device tree nodes for PCI and thus the peripheral driver 973 * has attached to bridges, otherwise the PCI clock remains 974 * unused and so it gets disabled 975 */ 976 clk_prepare_enable(clks[MPC512x_CLK_PSC3_MCLK]);/* serial console */ 977 if (of_find_compatible_node(NULL, "pci", "fsl,mpc5121-pci")) 978 clk_prepare_enable(clks[MPC512x_CLK_PCI]); 979 } 980 981 /* 982 * those macros are not exactly pretty, but they encapsulate a lot 983 * of copy'n'paste heavy code which is even more ugly, and reduce 984 * the potential for inconsistencies in those many code copies 985 */ 986 #define FOR_NODES(compatname) \ 987 for_each_compatible_node(np, NULL, compatname) 988 989 #define NODE_PREP do { \ 990 of_address_to_resource(np, 0, &res); \ 991 snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \ 992 } while (0) 993 994 #define NODE_CHK(clkname, clkitem, regnode, regflag) do { \ 995 struct clk *clk; \ 996 clk = of_clk_get_by_name(np, clkname); \ 997 if (IS_ERR(clk)) { \ 998 clk = clkitem; \ 999 clk_register_clkdev(clk, clkname, devname); \ 1000 if (regnode) \ 1001 clk_register_clkdev(clk, clkname, np->name); \ 1002 did_register |= DID_REG_ ## regflag; \ 1003 pr_debug("clock alias name '%s' for dev '%s' pointer %p\n", \ 1004 clkname, devname, clk); \ 1005 } else { \ 1006 clk_put(clk); \ 1007 } \ 1008 } while (0) 1009 1010 /* 1011 * register source code provided fallback results for clock lookups, 1012 * these get consulted when OF based clock lookup fails (that is in the 1013 * case of not yet adjusted device tree data, where clock related specs 1014 * are missing) 1015 */ 1016 static void mpc5121_clk_provide_backwards_compat(void) 1017 { 1018 enum did_reg_flags { 1019 DID_REG_PSC = BIT(0), 1020 DID_REG_PSCFIFO = BIT(1), 1021 DID_REG_NFC = BIT(2), 1022 DID_REG_CAN = BIT(3), 1023 DID_REG_I2C = BIT(4), 1024 DID_REG_DIU = BIT(5), 1025 DID_REG_VIU = BIT(6), 1026 DID_REG_FEC = BIT(7), 1027 DID_REG_USB = BIT(8), 1028 DID_REG_PATA = BIT(9), 1029 }; 1030 1031 int did_register; 1032 struct device_node *np; 1033 struct resource res; 1034 int idx; 1035 char devname[32]; 1036 1037 did_register = 0; 1038 1039 FOR_NODES(mpc512x_select_psc_compat()) { 1040 NODE_PREP; 1041 idx = (res.start >> 8) & 0xf; 1042 NODE_CHK("ipg", clks[MPC512x_CLK_PSC0 + idx], 0, PSC); 1043 NODE_CHK("mclk", clks[MPC512x_CLK_PSC0_MCLK + idx], 0, PSC); 1044 } 1045 1046 FOR_NODES("fsl,mpc5121-psc-fifo") { 1047 NODE_PREP; 1048 NODE_CHK("ipg", clks[MPC512x_CLK_PSC_FIFO], 1, PSCFIFO); 1049 } 1050 1051 FOR_NODES("fsl,mpc5121-nfc") { 1052 NODE_PREP; 1053 NODE_CHK("ipg", clks[MPC512x_CLK_NFC], 0, NFC); 1054 } 1055 1056 FOR_NODES("fsl,mpc5121-mscan") { 1057 NODE_PREP; 1058 idx = 0; 1059 idx += (res.start & 0x2000) ? 2 : 0; 1060 idx += (res.start & 0x0080) ? 1 : 0; 1061 NODE_CHK("ipg", clks[MPC512x_CLK_BDLC], 0, CAN); 1062 NODE_CHK("mclk", clks[MPC512x_CLK_MSCAN0_MCLK + idx], 0, CAN); 1063 } 1064 1065 /* 1066 * do register the 'ips', 'sys', and 'ref' names globally 1067 * instead of inside each individual CAN node, as there is no 1068 * potential for a name conflict (in contrast to 'ipg' and 'mclk') 1069 */ 1070 if (did_register & DID_REG_CAN) { 1071 clk_register_clkdev(clks[MPC512x_CLK_IPS], "ips", NULL); 1072 clk_register_clkdev(clks[MPC512x_CLK_SYS], "sys", NULL); 1073 clk_register_clkdev(clks[MPC512x_CLK_REF], "ref", NULL); 1074 } 1075 1076 FOR_NODES("fsl,mpc5121-i2c") { 1077 NODE_PREP; 1078 NODE_CHK("ipg", clks[MPC512x_CLK_I2C], 0, I2C); 1079 } 1080 1081 /* 1082 * workaround for the fact that the I2C driver does an "anonymous" 1083 * lookup (NULL name spec, which yields the first clock spec) for 1084 * which we cannot register an alias -- a _global_ 'ipg' alias that 1085 * is not bound to any device name and returns the I2C clock item 1086 * is not a good idea 1087 * 1088 * so we have the lookup in the peripheral driver fail, which is 1089 * silent and non-fatal, and pre-enable the clock item here such 1090 * that register access is possible 1091 * 1092 * see commit b3bfce2b "i2c: mpc: cleanup clock API use" for 1093 * details, adjusting s/NULL/"ipg"/ in i2c-mpc.c would make this 1094 * workaround obsolete 1095 */ 1096 if (did_register & DID_REG_I2C) 1097 clk_prepare_enable(clks[MPC512x_CLK_I2C]); 1098 1099 FOR_NODES("fsl,mpc5121-diu") { 1100 NODE_PREP; 1101 NODE_CHK("ipg", clks[MPC512x_CLK_DIU], 1, DIU); 1102 } 1103 1104 FOR_NODES("fsl,mpc5121-viu") { 1105 NODE_PREP; 1106 NODE_CHK("ipg", clks[MPC512x_CLK_VIU], 0, VIU); 1107 } 1108 1109 /* 1110 * note that 2771399a "fs_enet: cleanup clock API use" did use the 1111 * "per" string for the clock lookup in contrast to the "ipg" name 1112 * which most other nodes are using -- this is not a fatal thing 1113 * but just something to keep in mind when doing compatibility 1114 * registration, it's a non-issue with up-to-date device tree data 1115 */ 1116 FOR_NODES("fsl,mpc5121-fec") { 1117 NODE_PREP; 1118 NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC); 1119 } 1120 FOR_NODES("fsl,mpc5121-fec-mdio") { 1121 NODE_PREP; 1122 NODE_CHK("per", clks[MPC512x_CLK_FEC], 0, FEC); 1123 } 1124 /* 1125 * MPC5125 has two FECs: FEC1 at 0x2800, FEC2 at 0x4800; 1126 * the clock items don't "form an array" since FEC2 was 1127 * added only later and was not allowed to shift all other 1128 * clock item indices, so the numbers aren't adjacent 1129 */ 1130 FOR_NODES("fsl,mpc5125-fec") { 1131 NODE_PREP; 1132 if (res.start & 0x4000) 1133 idx = MPC512x_CLK_FEC2; 1134 else 1135 idx = MPC512x_CLK_FEC; 1136 NODE_CHK("per", clks[idx], 0, FEC); 1137 } 1138 1139 FOR_NODES("fsl,mpc5121-usb2-dr") { 1140 NODE_PREP; 1141 idx = (res.start & 0x4000) ? 1 : 0; 1142 NODE_CHK("ipg", clks[MPC512x_CLK_USB1 + idx], 0, USB); 1143 } 1144 1145 FOR_NODES("fsl,mpc5121-pata") { 1146 NODE_PREP; 1147 NODE_CHK("ipg", clks[MPC512x_CLK_PATA], 0, PATA); 1148 } 1149 1150 /* 1151 * try to collapse diagnostics into a single line of output yet 1152 * provide a full list of what is missing, to avoid noise in the 1153 * absence of up-to-date device tree data -- backwards 1154 * compatibility to old DTBs is a requirement, updates may be 1155 * desirable or preferrable but are not at all mandatory 1156 */ 1157 if (did_register) { 1158 pr_notice("device tree lacks clock specs, adding fallbacks (0x%x,%s%s%s%s%s%s%s%s%s%s)\n", 1159 did_register, 1160 (did_register & DID_REG_PSC) ? " PSC" : "", 1161 (did_register & DID_REG_PSCFIFO) ? " PSCFIFO" : "", 1162 (did_register & DID_REG_NFC) ? " NFC" : "", 1163 (did_register & DID_REG_CAN) ? " CAN" : "", 1164 (did_register & DID_REG_I2C) ? " I2C" : "", 1165 (did_register & DID_REG_DIU) ? " DIU" : "", 1166 (did_register & DID_REG_VIU) ? " VIU" : "", 1167 (did_register & DID_REG_FEC) ? " FEC" : "", 1168 (did_register & DID_REG_USB) ? " USB" : "", 1169 (did_register & DID_REG_PATA) ? " PATA" : ""); 1170 } else { 1171 pr_debug("device tree has clock specs, no fallbacks added\n"); 1172 } 1173 } 1174 1175 /* 1176 * The "fixed-clock" nodes (which includes the oscillator node if the board's 1177 * DT provides one) has already been scanned by the of_clk_init() in 1178 * time_init(). 1179 */ 1180 int __init mpc5121_clk_init(void) 1181 { 1182 struct device_node *clk_np; 1183 int busfreq; 1184 1185 /* map the clock control registers */ 1186 clk_np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-clock"); 1187 if (!clk_np) 1188 return -ENODEV; 1189 clkregs = of_iomap(clk_np, 0); 1190 WARN_ON(!clkregs); 1191 1192 /* determine the SoC variant we run on */ 1193 mpc512x_clk_determine_soc(); 1194 1195 /* invalidate all not yet registered clock slots */ 1196 mpc512x_clk_preset_data(); 1197 1198 /* 1199 * add a dummy clock for those situations where a clock spec is 1200 * required yet no real clock is involved 1201 */ 1202 clks[MPC512x_CLK_DUMMY] = mpc512x_clk_fixed("dummy", 0); 1203 1204 /* 1205 * have all the real nodes in the clock tree populated from REF 1206 * down to all leaves, either starting from the OSC node or from 1207 * a REF root that was created from the IPS bus clock input 1208 */ 1209 busfreq = get_freq_from_dt("bus-frequency"); 1210 mpc512x_clk_setup_clock_tree(clk_np, busfreq); 1211 1212 /* register as an OF clock provider */ 1213 mpc5121_clk_register_of_provider(clk_np); 1214 1215 /* 1216 * unbreak not yet adjusted peripheral drivers during migration 1217 * towards fully operational common clock support, and allow 1218 * operation in the absence of clock related device tree specs 1219 */ 1220 mpc5121_clk_provide_migration_support(); 1221 mpc5121_clk_provide_backwards_compat(); 1222 1223 return 0; 1224 } 1225