1bfa9a2ebSMichael Ellerman /* 2bfa9a2ebSMichael Ellerman * PCI / PCI-X / PCI-Express support for 4xx parts 3bfa9a2ebSMichael Ellerman * 4bfa9a2ebSMichael Ellerman * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp. 5bfa9a2ebSMichael Ellerman * 6bfa9a2ebSMichael Ellerman * Bits and pieces extracted from arch/ppc support by 7bfa9a2ebSMichael Ellerman * 8bfa9a2ebSMichael Ellerman * Matt Porter <mporter@kernel.crashing.org> 9bfa9a2ebSMichael Ellerman * 10bfa9a2ebSMichael Ellerman * Copyright 2002-2005 MontaVista Software Inc. 11bfa9a2ebSMichael Ellerman */ 12bfa9a2ebSMichael Ellerman #ifndef __PPC4XX_PCI_H__ 13bfa9a2ebSMichael Ellerman #define __PPC4XX_PCI_H__ 14bfa9a2ebSMichael Ellerman 15bfa9a2ebSMichael Ellerman /* 16bfa9a2ebSMichael Ellerman * 4xx PCI-X bridge register definitions 17bfa9a2ebSMichael Ellerman */ 18bfa9a2ebSMichael Ellerman #define PCIX0_VENDID 0x000 19bfa9a2ebSMichael Ellerman #define PCIX0_DEVID 0x002 20bfa9a2ebSMichael Ellerman #define PCIX0_COMMAND 0x004 21bfa9a2ebSMichael Ellerman #define PCIX0_STATUS 0x006 22bfa9a2ebSMichael Ellerman #define PCIX0_REVID 0x008 23bfa9a2ebSMichael Ellerman #define PCIX0_CLS 0x009 24bfa9a2ebSMichael Ellerman #define PCIX0_CACHELS 0x00c 25bfa9a2ebSMichael Ellerman #define PCIX0_LATTIM 0x00d 26bfa9a2ebSMichael Ellerman #define PCIX0_HDTYPE 0x00e 27bfa9a2ebSMichael Ellerman #define PCIX0_BIST 0x00f 28bfa9a2ebSMichael Ellerman #define PCIX0_BAR0L 0x010 29bfa9a2ebSMichael Ellerman #define PCIX0_BAR0H 0x014 30bfa9a2ebSMichael Ellerman #define PCIX0_BAR1 0x018 31bfa9a2ebSMichael Ellerman #define PCIX0_BAR2L 0x01c 32bfa9a2ebSMichael Ellerman #define PCIX0_BAR2H 0x020 33bfa9a2ebSMichael Ellerman #define PCIX0_BAR3 0x024 34bfa9a2ebSMichael Ellerman #define PCIX0_CISPTR 0x028 35bfa9a2ebSMichael Ellerman #define PCIX0_SBSYSVID 0x02c 36bfa9a2ebSMichael Ellerman #define PCIX0_SBSYSID 0x02e 37bfa9a2ebSMichael Ellerman #define PCIX0_EROMBA 0x030 38bfa9a2ebSMichael Ellerman #define PCIX0_CAP 0x034 39bfa9a2ebSMichael Ellerman #define PCIX0_RES0 0x035 40bfa9a2ebSMichael Ellerman #define PCIX0_RES1 0x036 41bfa9a2ebSMichael Ellerman #define PCIX0_RES2 0x038 42bfa9a2ebSMichael Ellerman #define PCIX0_INTLN 0x03c 43bfa9a2ebSMichael Ellerman #define PCIX0_INTPN 0x03d 44bfa9a2ebSMichael Ellerman #define PCIX0_MINGNT 0x03e 45bfa9a2ebSMichael Ellerman #define PCIX0_MAXLTNCY 0x03f 46bfa9a2ebSMichael Ellerman #define PCIX0_BRDGOPT1 0x040 47bfa9a2ebSMichael Ellerman #define PCIX0_BRDGOPT2 0x044 48bfa9a2ebSMichael Ellerman #define PCIX0_ERREN 0x050 49bfa9a2ebSMichael Ellerman #define PCIX0_ERRSTS 0x054 50bfa9a2ebSMichael Ellerman #define PCIX0_PLBBESR 0x058 51bfa9a2ebSMichael Ellerman #define PCIX0_PLBBEARL 0x05c 52bfa9a2ebSMichael Ellerman #define PCIX0_PLBBEARH 0x060 53bfa9a2ebSMichael Ellerman #define PCIX0_POM0LAL 0x068 54bfa9a2ebSMichael Ellerman #define PCIX0_POM0LAH 0x06c 55bfa9a2ebSMichael Ellerman #define PCIX0_POM0SA 0x070 56bfa9a2ebSMichael Ellerman #define PCIX0_POM0PCIAL 0x074 57bfa9a2ebSMichael Ellerman #define PCIX0_POM0PCIAH 0x078 58bfa9a2ebSMichael Ellerman #define PCIX0_POM1LAL 0x07c 59bfa9a2ebSMichael Ellerman #define PCIX0_POM1LAH 0x080 60bfa9a2ebSMichael Ellerman #define PCIX0_POM1SA 0x084 61bfa9a2ebSMichael Ellerman #define PCIX0_POM1PCIAL 0x088 62bfa9a2ebSMichael Ellerman #define PCIX0_POM1PCIAH 0x08c 63bfa9a2ebSMichael Ellerman #define PCIX0_POM2SA 0x090 64bfa9a2ebSMichael Ellerman #define PCIX0_PIM0SAL 0x098 65bfa9a2ebSMichael Ellerman #define PCIX0_PIM0SA PCIX0_PIM0SAL 66bfa9a2ebSMichael Ellerman #define PCIX0_PIM0LAL 0x09c 67bfa9a2ebSMichael Ellerman #define PCIX0_PIM0LAH 0x0a0 68bfa9a2ebSMichael Ellerman #define PCIX0_PIM1SA 0x0a4 69bfa9a2ebSMichael Ellerman #define PCIX0_PIM1LAL 0x0a8 70bfa9a2ebSMichael Ellerman #define PCIX0_PIM1LAH 0x0ac 71bfa9a2ebSMichael Ellerman #define PCIX0_PIM2SAL 0x0b0 72bfa9a2ebSMichael Ellerman #define PCIX0_PIM2SA PCIX0_PIM2SAL 73bfa9a2ebSMichael Ellerman #define PCIX0_PIM2LAL 0x0b4 74bfa9a2ebSMichael Ellerman #define PCIX0_PIM2LAH 0x0b8 75bfa9a2ebSMichael Ellerman #define PCIX0_OMCAPID 0x0c0 76bfa9a2ebSMichael Ellerman #define PCIX0_OMNIPTR 0x0c1 77bfa9a2ebSMichael Ellerman #define PCIX0_OMMC 0x0c2 78bfa9a2ebSMichael Ellerman #define PCIX0_OMMA 0x0c4 79bfa9a2ebSMichael Ellerman #define PCIX0_OMMUA 0x0c8 80bfa9a2ebSMichael Ellerman #define PCIX0_OMMDATA 0x0cc 81bfa9a2ebSMichael Ellerman #define PCIX0_OMMEOI 0x0ce 82bfa9a2ebSMichael Ellerman #define PCIX0_PMCAPID 0x0d0 83bfa9a2ebSMichael Ellerman #define PCIX0_PMNIPTR 0x0d1 84bfa9a2ebSMichael Ellerman #define PCIX0_PMC 0x0d2 85bfa9a2ebSMichael Ellerman #define PCIX0_PMCSR 0x0d4 86bfa9a2ebSMichael Ellerman #define PCIX0_PMCSRBSE 0x0d6 87bfa9a2ebSMichael Ellerman #define PCIX0_PMDATA 0x0d7 88bfa9a2ebSMichael Ellerman #define PCIX0_PMSCRR 0x0d8 89bfa9a2ebSMichael Ellerman #define PCIX0_CAPID 0x0dc 90bfa9a2ebSMichael Ellerman #define PCIX0_NIPTR 0x0dd 91bfa9a2ebSMichael Ellerman #define PCIX0_CMD 0x0de 92bfa9a2ebSMichael Ellerman #define PCIX0_STS 0x0e0 93bfa9a2ebSMichael Ellerman #define PCIX0_IDR 0x0e4 94bfa9a2ebSMichael Ellerman #define PCIX0_CID 0x0e8 95bfa9a2ebSMichael Ellerman #define PCIX0_RID 0x0ec 96bfa9a2ebSMichael Ellerman #define PCIX0_PIM0SAH 0x0f8 97bfa9a2ebSMichael Ellerman #define PCIX0_PIM2SAH 0x0fc 98bfa9a2ebSMichael Ellerman #define PCIX0_MSGIL 0x100 99bfa9a2ebSMichael Ellerman #define PCIX0_MSGIH 0x104 100bfa9a2ebSMichael Ellerman #define PCIX0_MSGOL 0x108 101bfa9a2ebSMichael Ellerman #define PCIX0_MSGOH 0x10c 102bfa9a2ebSMichael Ellerman #define PCIX0_IM 0x1f8 103bfa9a2ebSMichael Ellerman 104bfa9a2ebSMichael Ellerman /* 105bfa9a2ebSMichael Ellerman * 4xx PCI bridge register definitions 106bfa9a2ebSMichael Ellerman */ 107bfa9a2ebSMichael Ellerman #define PCIL0_PMM0LA 0x00 108bfa9a2ebSMichael Ellerman #define PCIL0_PMM0MA 0x04 109bfa9a2ebSMichael Ellerman #define PCIL0_PMM0PCILA 0x08 110bfa9a2ebSMichael Ellerman #define PCIL0_PMM0PCIHA 0x0c 111bfa9a2ebSMichael Ellerman #define PCIL0_PMM1LA 0x10 112bfa9a2ebSMichael Ellerman #define PCIL0_PMM1MA 0x14 113bfa9a2ebSMichael Ellerman #define PCIL0_PMM1PCILA 0x18 114bfa9a2ebSMichael Ellerman #define PCIL0_PMM1PCIHA 0x1c 115bfa9a2ebSMichael Ellerman #define PCIL0_PMM2LA 0x20 116bfa9a2ebSMichael Ellerman #define PCIL0_PMM2MA 0x24 117bfa9a2ebSMichael Ellerman #define PCIL0_PMM2PCILA 0x28 118bfa9a2ebSMichael Ellerman #define PCIL0_PMM2PCIHA 0x2c 119bfa9a2ebSMichael Ellerman #define PCIL0_PTM1MS 0x30 120bfa9a2ebSMichael Ellerman #define PCIL0_PTM1LA 0x34 121bfa9a2ebSMichael Ellerman #define PCIL0_PTM2MS 0x38 122bfa9a2ebSMichael Ellerman #define PCIL0_PTM2LA 0x3c 123bfa9a2ebSMichael Ellerman 124bfa9a2ebSMichael Ellerman /* 125bfa9a2ebSMichael Ellerman * 4xx PCIe bridge register definitions 126bfa9a2ebSMichael Ellerman */ 127bfa9a2ebSMichael Ellerman 128bfa9a2ebSMichael Ellerman /* DCR offsets */ 129bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_CFGBAH 0x00 130bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_CFGBAL 0x01 131bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_CFGMSK 0x02 132bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_MSGBAH 0x03 133bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_MSGBAL 0x04 134bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_MSGMSK 0x05 135bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR1BAH 0x06 136bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR1BAL 0x07 137bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR1MSKH 0x08 138bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR1MSKL 0x09 139bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR2BAH 0x0a 140bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR2BAL 0x0b 141bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR2MSKH 0x0c 142bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR2MSKL 0x0d 143bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR3BAH 0x0e 144bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR3BAL 0x0f 145bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR3MSKH 0x10 146bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR3MSKL 0x11 147bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_REGBAH 0x12 148bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_REGBAL 0x13 149bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_REGMSK 0x14 150bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_SPECIAL 0x15 151bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_CFG 0x16 152bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_ESR 0x17 153bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_EARH 0x18 154bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_EARL 0x19 155bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_EATR 0x1a 156bfa9a2ebSMichael Ellerman 157bfa9a2ebSMichael Ellerman /* DMER mask */ 158bfa9a2ebSMichael Ellerman #define GPL_DMER_MASK_DISA 0x02000000 159bfa9a2ebSMichael Ellerman 160bfa9a2ebSMichael Ellerman /* 161bfa9a2ebSMichael Ellerman * System DCRs (SDRs) 162bfa9a2ebSMichael Ellerman */ 163bfa9a2ebSMichael Ellerman #define PESDR0_PLLLCT1 0x03a0 164bfa9a2ebSMichael Ellerman #define PESDR0_PLLLCT2 0x03a1 165bfa9a2ebSMichael Ellerman #define PESDR0_PLLLCT3 0x03a2 166bfa9a2ebSMichael Ellerman 167bfa9a2ebSMichael Ellerman /* 168bfa9a2ebSMichael Ellerman * 440SPe additional DCRs 169bfa9a2ebSMichael Ellerman */ 170bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_UTLSET1 0x0300 171bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_UTLSET2 0x0301 172bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_DLPSET 0x0302 173bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_LOOP 0x0303 174bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_RCSSET 0x0304 175bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_RCSSTS 0x0305 176bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL0SET1 0x0306 177bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL0SET2 0x0307 178bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL0STS 0x0308 179bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL1SET1 0x0309 180bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL1SET2 0x030a 181bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL1STS 0x030b 182bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL2SET1 0x030c 183bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL2SET2 0x030d 184bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL2STS 0x030e 185bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL3SET1 0x030f 186bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL3SET2 0x0310 187bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL3STS 0x0311 188bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL4SET1 0x0312 189bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL4SET2 0x0313 190bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL4STS 0x0314 191bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL5SET1 0x0315 192bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL5SET2 0x0316 193bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL5STS 0x0317 194bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL6SET1 0x0318 195bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL6SET2 0x0319 196bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL6STS 0x031a 197bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL7SET1 0x031b 198bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL7SET2 0x031c 199bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSL7STS 0x031d 200bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_HSSCTLSET 0x031e 201bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_LANE_ABCD 0x031f 202bfa9a2ebSMichael Ellerman #define PESDR0_440SPE_LANE_EFGH 0x0320 203bfa9a2ebSMichael Ellerman 204bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_UTLSET1 0x0340 205bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_UTLSET2 0x0341 206bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_DLPSET 0x0342 207bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_LOOP 0x0343 208bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_RCSSET 0x0344 209bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_RCSSTS 0x0345 210bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL0SET1 0x0346 211bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL0SET2 0x0347 212bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL0STS 0x0348 213bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL1SET1 0x0349 214bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL1SET2 0x034a 215bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL1STS 0x034b 216bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL2SET1 0x034c 217bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL2SET2 0x034d 218bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL2STS 0x034e 219bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL3SET1 0x034f 220bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL3SET2 0x0350 221bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSL3STS 0x0351 222bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_HSSCTLSET 0x0352 223bfa9a2ebSMichael Ellerman #define PESDR1_440SPE_LANE_ABCD 0x0353 224bfa9a2ebSMichael Ellerman 225bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_UTLSET1 0x0370 226bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_UTLSET2 0x0371 227bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_DLPSET 0x0372 228bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_LOOP 0x0373 229bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_RCSSET 0x0374 230bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_RCSSTS 0x0375 231bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL0SET1 0x0376 232bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL0SET2 0x0377 233bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL0STS 0x0378 234bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL1SET1 0x0379 235bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL1SET2 0x037a 236bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL1STS 0x037b 237bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL2SET1 0x037c 238bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL2SET2 0x037d 239bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL2STS 0x037e 240bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL3SET1 0x037f 241bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL3SET2 0x0380 242bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSL3STS 0x0381 243bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_HSSCTLSET 0x0382 244bfa9a2ebSMichael Ellerman #define PESDR2_440SPE_LANE_ABCD 0x0383 245bfa9a2ebSMichael Ellerman 246bfa9a2ebSMichael Ellerman /* 247bfa9a2ebSMichael Ellerman * 405EX additional DCRs 248bfa9a2ebSMichael Ellerman */ 249bfa9a2ebSMichael Ellerman #define PESDR0_405EX_UTLSET1 0x0400 250bfa9a2ebSMichael Ellerman #define PESDR0_405EX_UTLSET2 0x0401 251bfa9a2ebSMichael Ellerman #define PESDR0_405EX_DLPSET 0x0402 252bfa9a2ebSMichael Ellerman #define PESDR0_405EX_LOOP 0x0403 253bfa9a2ebSMichael Ellerman #define PESDR0_405EX_RCSSET 0x0404 254bfa9a2ebSMichael Ellerman #define PESDR0_405EX_RCSSTS 0x0405 255bfa9a2ebSMichael Ellerman #define PESDR0_405EX_PHYSET1 0x0406 256bfa9a2ebSMichael Ellerman #define PESDR0_405EX_PHYSET2 0x0407 257bfa9a2ebSMichael Ellerman #define PESDR0_405EX_BIST 0x0408 258bfa9a2ebSMichael Ellerman #define PESDR0_405EX_LPB 0x040B 259bfa9a2ebSMichael Ellerman #define PESDR0_405EX_PHYSTA 0x040C 260bfa9a2ebSMichael Ellerman 261bfa9a2ebSMichael Ellerman #define PESDR1_405EX_UTLSET1 0x0440 262bfa9a2ebSMichael Ellerman #define PESDR1_405EX_UTLSET2 0x0441 263bfa9a2ebSMichael Ellerman #define PESDR1_405EX_DLPSET 0x0442 264bfa9a2ebSMichael Ellerman #define PESDR1_405EX_LOOP 0x0443 265bfa9a2ebSMichael Ellerman #define PESDR1_405EX_RCSSET 0x0444 266bfa9a2ebSMichael Ellerman #define PESDR1_405EX_RCSSTS 0x0445 267bfa9a2ebSMichael Ellerman #define PESDR1_405EX_PHYSET1 0x0446 268bfa9a2ebSMichael Ellerman #define PESDR1_405EX_PHYSET2 0x0447 269bfa9a2ebSMichael Ellerman #define PESDR1_405EX_BIST 0x0448 270bfa9a2ebSMichael Ellerman #define PESDR1_405EX_LPB 0x044B 271bfa9a2ebSMichael Ellerman #define PESDR1_405EX_PHYSTA 0x044C 272bfa9a2ebSMichael Ellerman 273bfa9a2ebSMichael Ellerman /* 274bfa9a2ebSMichael Ellerman * 460EX additional DCRs 275bfa9a2ebSMichael Ellerman */ 276bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0BIST 0x0308 277bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0BISTSTS 0x0309 278bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0CDRCTL 0x030A 279bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0DRV 0x030B 280bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0REC 0x030C 281bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0LPB 0x030D 282bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0CLK 0x030E 283bfa9a2ebSMichael Ellerman #define PESDR0_460EX_PHY_CTL_RST 0x030F 284bfa9a2ebSMichael Ellerman #define PESDR0_460EX_RSTSTA 0x0310 285bfa9a2ebSMichael Ellerman #define PESDR0_460EX_OBS 0x0311 286bfa9a2ebSMichael Ellerman #define PESDR0_460EX_L0ERRC 0x0320 287bfa9a2ebSMichael Ellerman 288bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0BIST 0x0348 289bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1BIST 0x0349 290bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2BIST 0x034A 291bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3BIST 0x034B 292bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0BISTSTS 0x034C 293bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1BISTSTS 0x034D 294bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2BISTSTS 0x034E 295bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3BISTSTS 0x034F 296bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0CDRCTL 0x0350 297bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1CDRCTL 0x0351 298bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2CDRCTL 0x0352 299bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3CDRCTL 0x0353 300bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0DRV 0x0354 301bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1DRV 0x0355 302bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2DRV 0x0356 303bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3DRV 0x0357 304bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0REC 0x0358 305bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1REC 0x0359 306bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2REC 0x035A 307bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3REC 0x035B 308bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0LPB 0x035C 309bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1LPB 0x035D 310bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2LPB 0x035E 311bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3LPB 0x035F 312bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0CLK 0x0360 313bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1CLK 0x0361 314bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2CLK 0x0362 315bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3CLK 0x0363 316bfa9a2ebSMichael Ellerman #define PESDR1_460EX_PHY_CTL_RST 0x0364 317bfa9a2ebSMichael Ellerman #define PESDR1_460EX_RSTSTA 0x0365 318bfa9a2ebSMichael Ellerman #define PESDR1_460EX_OBS 0x0366 319bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L0ERRC 0x0368 320bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L1ERRC 0x0369 321bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L2ERRC 0x036A 322bfa9a2ebSMichael Ellerman #define PESDR1_460EX_L3ERRC 0x036B 323bfa9a2ebSMichael Ellerman #define PESDR0_460EX_IHS1 0x036C 324bfa9a2ebSMichael Ellerman #define PESDR0_460EX_IHS2 0x036D 325bfa9a2ebSMichael Ellerman 326bfa9a2ebSMichael Ellerman /* 327bfa9a2ebSMichael Ellerman * 460SX additional DCRs 328bfa9a2ebSMichael Ellerman */ 329bfa9a2ebSMichael Ellerman #define PESDRn_460SX_RCEI 0x02 330bfa9a2ebSMichael Ellerman 331bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL0DAMP 0x320 332bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL1DAMP 0x321 333bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL2DAMP 0x322 334bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL3DAMP 0x323 335bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL4DAMP 0x324 336bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL5DAMP 0x325 337bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL6DAMP 0x326 338bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL7DAMP 0x327 339bfa9a2ebSMichael Ellerman 340bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL0DAMP 0x354 341bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL1DAMP 0x355 342bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL2DAMP 0x356 343bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL3DAMP 0x357 344bfa9a2ebSMichael Ellerman 345bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL0DAMP 0x384 346bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL1DAMP 0x385 347bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL2DAMP 0x386 348bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL3DAMP 0x387 349bfa9a2ebSMichael Ellerman 350bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL0COEFA 0x328 351bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL1COEFA 0x329 352bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL2COEFA 0x32A 353bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL3COEFA 0x32B 354bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL4COEFA 0x32C 355bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL5COEFA 0x32D 356bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL6COEFA 0x32E 357bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL7COEFA 0x32F 358bfa9a2ebSMichael Ellerman 359bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL0COEFA 0x358 360bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL1COEFA 0x359 361bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL2COEFA 0x35A 362bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL3COEFA 0x35B 363bfa9a2ebSMichael Ellerman 364bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL0COEFA 0x388 365bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL1COEFA 0x389 366bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL2COEFA 0x38A 367bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL3COEFA 0x38B 368bfa9a2ebSMichael Ellerman 369bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSL1CALDRV 0x339 370bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSL1CALDRV 0x361 371bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSL1CALDRV 0x391 372bfa9a2ebSMichael Ellerman 373bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSSLEW 0x338 374bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSSLEW 0x360 375bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSSLEW 0x390 376bfa9a2ebSMichael Ellerman 377bfa9a2ebSMichael Ellerman #define PESDR0_460SX_HSSCTLSET 0x31E 378bfa9a2ebSMichael Ellerman #define PESDR1_460SX_HSSCTLSET 0x352 379bfa9a2ebSMichael Ellerman #define PESDR2_460SX_HSSCTLSET 0x382 380bfa9a2ebSMichael Ellerman 381bfa9a2ebSMichael Ellerman #define PESDR0_460SX_RCSSET 0x304 382bfa9a2ebSMichael Ellerman #define PESDR1_460SX_RCSSET 0x344 383bfa9a2ebSMichael Ellerman #define PESDR2_460SX_RCSSET 0x374 384bfa9a2ebSMichael Ellerman /* 385bfa9a2ebSMichael Ellerman * Of the above, some are common offsets from the base 386bfa9a2ebSMichael Ellerman */ 387bfa9a2ebSMichael Ellerman #define PESDRn_UTLSET1 0x00 388bfa9a2ebSMichael Ellerman #define PESDRn_UTLSET2 0x01 389bfa9a2ebSMichael Ellerman #define PESDRn_DLPSET 0x02 390bfa9a2ebSMichael Ellerman #define PESDRn_LOOP 0x03 391bfa9a2ebSMichael Ellerman #define PESDRn_RCSSET 0x04 392bfa9a2ebSMichael Ellerman #define PESDRn_RCSSTS 0x05 393bfa9a2ebSMichael Ellerman 394bfa9a2ebSMichael Ellerman /* 440spe only */ 395bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL0SET1 0x06 396bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL0SET2 0x07 397bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL0STS 0x08 398bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL1SET1 0x09 399bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL1SET2 0x0a 400bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL1STS 0x0b 401bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL2SET1 0x0c 402bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL2SET2 0x0d 403bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL2STS 0x0e 404bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL3SET1 0x0f 405bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL3SET2 0x10 406bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL3STS 0x11 407bfa9a2ebSMichael Ellerman 408bfa9a2ebSMichael Ellerman /* 440spe port 0 only */ 409bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL4SET1 0x12 410bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL4SET2 0x13 411bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL4STS 0x14 412bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL5SET1 0x15 413bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL5SET2 0x16 414bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL5STS 0x17 415bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL6SET1 0x18 416bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL6SET2 0x19 417bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL6STS 0x1a 418bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL7SET1 0x1b 419bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL7SET2 0x1c 420bfa9a2ebSMichael Ellerman #define PESDRn_440SPE_HSSL7STS 0x1d 421bfa9a2ebSMichael Ellerman 422bfa9a2ebSMichael Ellerman /* 405ex only */ 423bfa9a2ebSMichael Ellerman #define PESDRn_405EX_PHYSET1 0x06 424bfa9a2ebSMichael Ellerman #define PESDRn_405EX_PHYSET2 0x07 425bfa9a2ebSMichael Ellerman #define PESDRn_405EX_PHYSTA 0x0c 426bfa9a2ebSMichael Ellerman 427bfa9a2ebSMichael Ellerman /* 428bfa9a2ebSMichael Ellerman * UTL register offsets 429bfa9a2ebSMichael Ellerman */ 430bfa9a2ebSMichael Ellerman #define PEUTL_PBCTL 0x00 431bfa9a2ebSMichael Ellerman #define PEUTL_PBBSZ 0x20 432bfa9a2ebSMichael Ellerman #define PEUTL_OPDBSZ 0x68 433bfa9a2ebSMichael Ellerman #define PEUTL_IPHBSZ 0x70 434bfa9a2ebSMichael Ellerman #define PEUTL_IPDBSZ 0x78 435bfa9a2ebSMichael Ellerman #define PEUTL_OUTTR 0x90 436bfa9a2ebSMichael Ellerman #define PEUTL_INTR 0x98 437bfa9a2ebSMichael Ellerman #define PEUTL_PCTL 0xa0 438bfa9a2ebSMichael Ellerman #define PEUTL_RCSTA 0xB0 439bfa9a2ebSMichael Ellerman #define PEUTL_RCIRQEN 0xb8 440bfa9a2ebSMichael Ellerman 441bfa9a2ebSMichael Ellerman /* 442bfa9a2ebSMichael Ellerman * Config space register offsets 443bfa9a2ebSMichael Ellerman */ 444bfa9a2ebSMichael Ellerman #define PECFG_ECRTCTL 0x074 445bfa9a2ebSMichael Ellerman 446bfa9a2ebSMichael Ellerman #define PECFG_BAR0LMPA 0x210 447bfa9a2ebSMichael Ellerman #define PECFG_BAR0HMPA 0x214 448bfa9a2ebSMichael Ellerman #define PECFG_BAR1MPA 0x218 449bfa9a2ebSMichael Ellerman #define PECFG_BAR2LMPA 0x220 450bfa9a2ebSMichael Ellerman #define PECFG_BAR2HMPA 0x224 451bfa9a2ebSMichael Ellerman 452bfa9a2ebSMichael Ellerman #define PECFG_PIMEN 0x33c 453bfa9a2ebSMichael Ellerman #define PECFG_PIM0LAL 0x340 454bfa9a2ebSMichael Ellerman #define PECFG_PIM0LAH 0x344 455bfa9a2ebSMichael Ellerman #define PECFG_PIM1LAL 0x348 456bfa9a2ebSMichael Ellerman #define PECFG_PIM1LAH 0x34c 457bfa9a2ebSMichael Ellerman #define PECFG_PIM01SAL 0x350 458bfa9a2ebSMichael Ellerman #define PECFG_PIM01SAH 0x354 459bfa9a2ebSMichael Ellerman 460bfa9a2ebSMichael Ellerman #define PECFG_POM0LAL 0x380 461bfa9a2ebSMichael Ellerman #define PECFG_POM0LAH 0x384 462bfa9a2ebSMichael Ellerman #define PECFG_POM1LAL 0x388 463bfa9a2ebSMichael Ellerman #define PECFG_POM1LAH 0x38c 464bfa9a2ebSMichael Ellerman #define PECFG_POM2LAL 0x390 465bfa9a2ebSMichael Ellerman #define PECFG_POM2LAH 0x394 466bfa9a2ebSMichael Ellerman 467bfa9a2ebSMichael Ellerman /* 460sx only */ 468bfa9a2ebSMichael Ellerman #define PECFG_460SX_DLLSTA 0x3f8 469bfa9a2ebSMichael Ellerman 470bfa9a2ebSMichael Ellerman /* 460sx Bit Mappings */ 471bfa9a2ebSMichael Ellerman #define PECFG_460SX_DLLSTA_LINKUP 0x00000010 472bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_460SX_OMR1MSKL_UOT 0x00000004 473bfa9a2ebSMichael Ellerman 474bfa9a2ebSMichael Ellerman /* PEGPL Bit Mappings */ 475bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMRxMSKL_VAL 0x00000001 476bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002 477bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_OMR3MSKL_IO 0x00000002 478bfa9a2ebSMichael Ellerman 479bfa9a2ebSMichael Ellerman /* 476FPE */ 480bfa9a2ebSMichael Ellerman #define PCCFG_LCPA 0x270 481bfa9a2ebSMichael Ellerman #define PECFG_TLDLP 0x3F8 482bfa9a2ebSMichael Ellerman #define PECFG_TLDLP_LNKUP 0x00000008 483bfa9a2ebSMichael Ellerman #define PECFG_TLDLP_PRESENT 0x00000010 484bfa9a2ebSMichael Ellerman #define DCRO_PEGPL_476FPE_OMR1MSKL_UOT 0x00000004 485bfa9a2ebSMichael Ellerman 486bfa9a2ebSMichael Ellerman /* SDR Bit Mappings */ 487bfa9a2ebSMichael Ellerman #define PESDRx_RCSSET_HLDPLB 0x10000000 488bfa9a2ebSMichael Ellerman #define PESDRx_RCSSET_RSTGU 0x01000000 489bfa9a2ebSMichael Ellerman #define PESDRx_RCSSET_RDY 0x00100000 490bfa9a2ebSMichael Ellerman #define PESDRx_RCSSET_RSTDL 0x00010000 491bfa9a2ebSMichael Ellerman #define PESDRx_RCSSET_RSTPYN 0x00001000 492bfa9a2ebSMichael Ellerman 493bfa9a2ebSMichael Ellerman enum 494bfa9a2ebSMichael Ellerman { 495bfa9a2ebSMichael Ellerman PTYPE_ENDPOINT = 0x0, 496bfa9a2ebSMichael Ellerman PTYPE_LEGACY_ENDPOINT = 0x1, 497bfa9a2ebSMichael Ellerman PTYPE_ROOT_PORT = 0x4, 498bfa9a2ebSMichael Ellerman 499bfa9a2ebSMichael Ellerman LNKW_X1 = 0x1, 500bfa9a2ebSMichael Ellerman LNKW_X4 = 0x4, 501bfa9a2ebSMichael Ellerman LNKW_X8 = 0x8 502bfa9a2ebSMichael Ellerman }; 503bfa9a2ebSMichael Ellerman 504bfa9a2ebSMichael Ellerman 505bfa9a2ebSMichael Ellerman #endif /* __PPC4XX_PCI_H__ */ 506