1494d82ceSIvan Mikhaylov #ifndef _ASM_POWERPC_FSP_DCR_H_ 2494d82ceSIvan Mikhaylov #define _ASM_POWERPC_FSP_DCR_H_ 3494d82ceSIvan Mikhaylov #ifdef __KERNEL__ 4494d82ceSIvan Mikhaylov #include <asm/dcr.h> 5494d82ceSIvan Mikhaylov 6494d82ceSIvan Mikhaylov #define DCRN_CMU_ADDR 0x00C /* Chip management unic addr */ 7494d82ceSIvan Mikhaylov #define DCRN_CMU_DATA 0x00D /* Chip management unic data */ 8494d82ceSIvan Mikhaylov 9494d82ceSIvan Mikhaylov /* PLB4 Arbiter */ 10494d82ceSIvan Mikhaylov #define DCRN_PLB4_PCBI 0x010 /* PLB Crossbar ID/Rev Register */ 11494d82ceSIvan Mikhaylov #define DCRN_PLB4_P0ACR 0x011 /* PLB0 Arbiter Control Register */ 12494d82ceSIvan Mikhaylov #define DCRN_PLB4_P0ESRL 0x012 /* PLB0 Error Status Register Low */ 13494d82ceSIvan Mikhaylov #define DCRN_PLB4_P0ESRH 0x013 /* PLB0 Error Status Register High */ 14494d82ceSIvan Mikhaylov #define DCRN_PLB4_P0EARL 0x014 /* PLB0 Error Address Register Low */ 15494d82ceSIvan Mikhaylov #define DCRN_PLB4_P0EARH 0x015 /* PLB0 Error Address Register High */ 16494d82ceSIvan Mikhaylov #define DCRN_PLB4_P0ESRLS 0x016 /* PLB0 Error Status Register Low Set*/ 17494d82ceSIvan Mikhaylov #define DCRN_PLB4_P0ESRHS 0x017 /* PLB0 Error Status Register High */ 18494d82ceSIvan Mikhaylov #define DCRN_PLB4_PCBC 0x018 /* PLB Crossbar Control Register */ 19494d82ceSIvan Mikhaylov #define DCRN_PLB4_P1ACR 0x019 /* PLB1 Arbiter Control Register */ 20494d82ceSIvan Mikhaylov #define DCRN_PLB4_P1ESRL 0x01A /* PLB1 Error Status Register Low */ 21494d82ceSIvan Mikhaylov #define DCRN_PLB4_P1ESRH 0x01B /* PLB1 Error Status Register High */ 22494d82ceSIvan Mikhaylov #define DCRN_PLB4_P1EARL 0x01C /* PLB1 Error Address Register Low */ 23494d82ceSIvan Mikhaylov #define DCRN_PLB4_P1EARH 0x01D /* PLB1 Error Address Register High */ 24494d82ceSIvan Mikhaylov #define DCRN_PLB4_P1ESRLS 0x01E /* PLB1 Error Status Register Low Set*/ 25494d82ceSIvan Mikhaylov #define DCRN_PLB4_P1ESRHS 0x01F /*PLB1 Error Status Register High Set*/ 26494d82ceSIvan Mikhaylov 27494d82ceSIvan Mikhaylov /* PLB4/OPB bridge 0, 1, 2, 3 */ 28494d82ceSIvan Mikhaylov #define DCRN_PLB4OPB0_BASE 0x020 29494d82ceSIvan Mikhaylov #define DCRN_PLB4OPB1_BASE 0x030 30494d82ceSIvan Mikhaylov #define DCRN_PLB4OPB2_BASE 0x040 31494d82ceSIvan Mikhaylov #define DCRN_PLB4OPB3_BASE 0x050 32494d82ceSIvan Mikhaylov 33494d82ceSIvan Mikhaylov #define PLB4OPB_GESR0 0x0 /* Error status 0: Master Dev 0-3 */ 34494d82ceSIvan Mikhaylov #define PLB4OPB_GEAR 0x2 /* Error Address Register */ 35494d82ceSIvan Mikhaylov #define PLB4OPB_GEARU 0x3 /* Error Upper Address Register */ 36494d82ceSIvan Mikhaylov #define PLB4OPB_GESR1 0x4 /* Error Status 1: Master Dev 4-7 */ 37494d82ceSIvan Mikhaylov #define PLB4OPB_GESR2 0xC /* Error Status 2: Master Dev 8-11 */ 38494d82ceSIvan Mikhaylov 39494d82ceSIvan Mikhaylov /* PLB4-to-AHB Bridge */ 40494d82ceSIvan Mikhaylov #define DCRN_PLB4AHB_BASE 0x400 41494d82ceSIvan Mikhaylov #define DCRN_PLB4AHB_SEUAR (DCRN_PLB4AHB_BASE + 1) 42494d82ceSIvan Mikhaylov #define DCRN_PLB4AHB_SELAR (DCRN_PLB4AHB_BASE + 2) 43494d82ceSIvan Mikhaylov #define DCRN_PLB4AHB_ESR (DCRN_PLB4AHB_BASE + 3) 44494d82ceSIvan Mikhaylov #define DCRN_AHBPLB4_ESR (DCRN_PLB4AHB_BASE + 8) 45494d82ceSIvan Mikhaylov #define DCRN_AHBPLB4_EAR (DCRN_PLB4AHB_BASE + 9) 46494d82ceSIvan Mikhaylov 47494d82ceSIvan Mikhaylov /* PLB6 Controller */ 48494d82ceSIvan Mikhaylov #define DCRN_PLB6_BASE 0x11111300 49494d82ceSIvan Mikhaylov #define DCRN_PLB6_CR0 (DCRN_PLB6_BASE) 50494d82ceSIvan Mikhaylov #define DCRN_PLB6_ERR (DCRN_PLB6_BASE + 0x0B) 51494d82ceSIvan Mikhaylov #define DCRN_PLB6_HD (DCRN_PLB6_BASE + 0x0E) 52494d82ceSIvan Mikhaylov #define DCRN_PLB6_SHD (DCRN_PLB6_BASE + 0x10) 53494d82ceSIvan Mikhaylov 54494d82ceSIvan Mikhaylov /* PLB4-to-PLB6 Bridge */ 55494d82ceSIvan Mikhaylov #define DCRN_PLB4PLB6_BASE 0x11111320 56494d82ceSIvan Mikhaylov #define DCRN_PLB4PLB6_ESR (DCRN_PLB4PLB6_BASE + 1) 57494d82ceSIvan Mikhaylov #define DCRN_PLB4PLB6_EARH (DCRN_PLB4PLB6_BASE + 3) 58494d82ceSIvan Mikhaylov #define DCRN_PLB4PLB6_EARL (DCRN_PLB4PLB6_BASE + 4) 59494d82ceSIvan Mikhaylov 60494d82ceSIvan Mikhaylov /* PLB6-to-PLB4 Bridge */ 61494d82ceSIvan Mikhaylov #define DCRN_PLB6PLB4_BASE 0x11111350 62494d82ceSIvan Mikhaylov #define DCRN_PLB6PLB4_ESR (DCRN_PLB6PLB4_BASE + 1) 63494d82ceSIvan Mikhaylov #define DCRN_PLB6PLB4_EARH (DCRN_PLB6PLB4_BASE + 3) 64494d82ceSIvan Mikhaylov #define DCRN_PLB6PLB4_EARL (DCRN_PLB6PLB4_BASE + 4) 65494d82ceSIvan Mikhaylov 66494d82ceSIvan Mikhaylov /* PLB6-to-MCIF Bridge */ 67494d82ceSIvan Mikhaylov #define DCRN_PLB6MCIF_BASE 0x11111380 68494d82ceSIvan Mikhaylov #define DCRN_PLB6MCIF_BESR0 (DCRN_PLB6MCIF_BASE + 0) 69494d82ceSIvan Mikhaylov #define DCRN_PLB6MCIF_BESR1 (DCRN_PLB6MCIF_BASE + 1) 70494d82ceSIvan Mikhaylov #define DCRN_PLB6MCIF_BEARL (DCRN_PLB6MCIF_BASE + 2) 71494d82ceSIvan Mikhaylov #define DCRN_PLB6MCIF_BEARH (DCRN_PLB6MCIF_BASE + 3) 72494d82ceSIvan Mikhaylov 73494d82ceSIvan Mikhaylov /* Configuration Logic Registers */ 74494d82ceSIvan Mikhaylov #define DCRN_CONF_BASE 0x11111400 75494d82ceSIvan Mikhaylov #define DCRN_CONF_FIR_RWC (DCRN_CONF_BASE + 0x3A) 76494d82ceSIvan Mikhaylov #define DCRN_CONF_EIR_RS (DCRN_CONF_BASE + 0x3E) 77494d82ceSIvan Mikhaylov #define DCRN_CONF_RPERR0 (DCRN_CONF_BASE + 0x4D) 78494d82ceSIvan Mikhaylov #define DCRN_CONF_RPERR1 (DCRN_CONF_BASE + 0x4E) 79494d82ceSIvan Mikhaylov 80494d82ceSIvan Mikhaylov #define DCRN_L2CDCRAI 0x11111100 81494d82ceSIvan Mikhaylov #define DCRN_L2CDCRDI 0x11111104 82494d82ceSIvan Mikhaylov /* L2 indirect addresses */ 83494d82ceSIvan Mikhaylov #define L2MCK 0x120 84494d82ceSIvan Mikhaylov #define L2MCKEN 0x130 85494d82ceSIvan Mikhaylov #define L2INT 0x150 86494d82ceSIvan Mikhaylov #define L2INTEN 0x160 87494d82ceSIvan Mikhaylov #define L2LOG0 0x180 88494d82ceSIvan Mikhaylov #define L2LOG1 0x184 89494d82ceSIvan Mikhaylov #define L2LOG2 0x188 90494d82ceSIvan Mikhaylov #define L2LOG3 0x18C 91494d82ceSIvan Mikhaylov #define L2LOG4 0x190 92494d82ceSIvan Mikhaylov #define L2LOG5 0x194 93494d82ceSIvan Mikhaylov #define L2PLBSTAT0 0x300 94494d82ceSIvan Mikhaylov #define L2PLBSTAT1 0x304 95494d82ceSIvan Mikhaylov #define L2PLBMCKEN0 0x330 96494d82ceSIvan Mikhaylov #define L2PLBMCKEN1 0x334 97494d82ceSIvan Mikhaylov #define L2PLBINTEN0 0x360 98494d82ceSIvan Mikhaylov #define L2PLBINTEN1 0x364 99494d82ceSIvan Mikhaylov #define L2ARRSTAT0 0x500 100494d82ceSIvan Mikhaylov #define L2ARRSTAT1 0x504 101494d82ceSIvan Mikhaylov #define L2ARRSTAT2 0x508 102494d82ceSIvan Mikhaylov #define L2ARRMCKEN0 0x530 103494d82ceSIvan Mikhaylov #define L2ARRMCKEN1 0x534 104494d82ceSIvan Mikhaylov #define L2ARRMCKEN2 0x538 105494d82ceSIvan Mikhaylov #define L2ARRINTEN0 0x560 106494d82ceSIvan Mikhaylov #define L2ARRINTEN1 0x564 107494d82ceSIvan Mikhaylov #define L2ARRINTEN2 0x568 108494d82ceSIvan Mikhaylov #define L2CPUSTAT 0x700 109494d82ceSIvan Mikhaylov #define L2CPUMCKEN 0x730 110494d82ceSIvan Mikhaylov #define L2CPUINTEN 0x760 111494d82ceSIvan Mikhaylov #define L2RACSTAT0 0x900 112494d82ceSIvan Mikhaylov #define L2RACMCKEN0 0x930 113494d82ceSIvan Mikhaylov #define L2RACINTEN0 0x960 114494d82ceSIvan Mikhaylov #define L2WACSTAT0 0xD00 115494d82ceSIvan Mikhaylov #define L2WACSTAT1 0xD04 116494d82ceSIvan Mikhaylov #define L2WACSTAT2 0xD08 117494d82ceSIvan Mikhaylov #define L2WACMCKEN0 0xD30 118494d82ceSIvan Mikhaylov #define L2WACMCKEN1 0xD34 119494d82ceSIvan Mikhaylov #define L2WACMCKEN2 0xD38 120494d82ceSIvan Mikhaylov #define L2WACINTEN0 0xD60 121494d82ceSIvan Mikhaylov #define L2WACINTEN1 0xD64 122494d82ceSIvan Mikhaylov #define L2WACINTEN2 0xD68 123494d82ceSIvan Mikhaylov #define L2WDFSTAT 0xF00 124494d82ceSIvan Mikhaylov #define L2WDFMCKEN 0xF30 125494d82ceSIvan Mikhaylov #define L2WDFINTEN 0xF60 126494d82ceSIvan Mikhaylov 127494d82ceSIvan Mikhaylov /* DDR3/4 Memory Controller */ 128494d82ceSIvan Mikhaylov #define DCRN_DDR34_BASE 0x11120000 129494d82ceSIvan Mikhaylov #define DCRN_DDR34_MCSTAT 0x10 130494d82ceSIvan Mikhaylov #define DCRN_DDR34_MCOPT1 0x20 131494d82ceSIvan Mikhaylov #define DCRN_DDR34_MCOPT2 0x21 132494d82ceSIvan Mikhaylov #define DCRN_DDR34_PHYSTAT 0x32 133494d82ceSIvan Mikhaylov #define DCRN_DDR34_CFGR0 0x40 134494d82ceSIvan Mikhaylov #define DCRN_DDR34_CFGR1 0x41 135494d82ceSIvan Mikhaylov #define DCRN_DDR34_CFGR2 0x42 136494d82ceSIvan Mikhaylov #define DCRN_DDR34_CFGR3 0x43 137494d82ceSIvan Mikhaylov #define DCRN_DDR34_SCRUB_CNTL 0xAA 138494d82ceSIvan Mikhaylov #define DCRN_DDR34_SCRUB_INT 0xAB 139494d82ceSIvan Mikhaylov #define DCRN_DDR34_SCRUB_START_ADDR 0xB0 140494d82ceSIvan Mikhaylov #define DCRN_DDR34_SCRUB_END_ADDR 0xD0 141494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_ADDR_PORT0 0xE0 142494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_ADDR_PORT1 0xE1 143494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_ADDR_PORT2 0xE2 144494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_ADDR_PORT3 0xE3 145494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_COUNT_PORT0 0xE4 146494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_COUNT_PORT1 0xE5 147494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_COUNT_PORT2 0xE6 148494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_COUNT_PORT3 0xE7 149494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_PORT0 0xF0 150494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_PORT1 0xF2 151494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_PORT2 0xF4 152494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECCERR_PORT3 0xF6 153494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECC_CHECK_PORT0 0xF8 154494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECC_CHECK_PORT1 0xF9 155494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECC_CHECK_PORT2 0xF9 156494d82ceSIvan Mikhaylov #define DCRN_DDR34_ECC_CHECK_PORT3 0xFB 157494d82ceSIvan Mikhaylov 158494d82ceSIvan Mikhaylov #define DDR34_SCRUB_CNTL_STOP 0x00000000 159494d82ceSIvan Mikhaylov #define DDR34_SCRUB_CNTL_SCRUB 0x80000000 160494d82ceSIvan Mikhaylov #define DDR34_SCRUB_CNTL_UE_STOP 0x20000000 161494d82ceSIvan Mikhaylov #define DDR34_SCRUB_CNTL_CE_STOP 0x10000000 162494d82ceSIvan Mikhaylov #define DDR34_SCRUB_CNTL_RANK_EN 0x00008000 163494d82ceSIvan Mikhaylov 164494d82ceSIvan Mikhaylov /* PLB-Attached DDR3/4 Core Wrapper */ 165494d82ceSIvan Mikhaylov #define DCRN_CW_BASE 0x11111800 166494d82ceSIvan Mikhaylov #define DCRN_CW_MCER0 0x00 167494d82ceSIvan Mikhaylov #define DCRN_CW_MCER1 0x01 168494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_AND0 0x02 169494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_AND1 0x03 170494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_OR0 0x04 171494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_OR1 0x05 172494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_MASK0 0x06 173494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_MASK1 0x07 174494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_MASK_AND0 0x08 175494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_MASK_AND1 0x09 176494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_MASK_OR0 0x0A 177494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_MASK_OR1 0x0B 178494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_ACTION0 0x0C 179494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_ACTION1 0x0D 180494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_WOF0 0x0E 181494d82ceSIvan Mikhaylov #define DCRN_CW_MCER_WOF1 0x0F 182494d82ceSIvan Mikhaylov #define DCRN_CW_LFIR 0x10 183494d82ceSIvan Mikhaylov #define DCRN_CW_LFIR_AND 0x11 184494d82ceSIvan Mikhaylov #define DCRN_CW_LFIR_OR 0x12 185494d82ceSIvan Mikhaylov #define DCRN_CW_LFIR_MASK 0x13 186494d82ceSIvan Mikhaylov #define DCRN_CW_LFIR_MASK_AND 0x14 187494d82ceSIvan Mikhaylov #define DCRN_CW_LFIR_MASK_OR 0x15 188494d82ceSIvan Mikhaylov 189494d82ceSIvan Mikhaylov #define CW_MCER0_MEM_CE 0x00020000 190494d82ceSIvan Mikhaylov /* CMU addresses */ 191494d82ceSIvan Mikhaylov #define CMUN_CRCS 0x00 /* Chip Reset Control/Status */ 192494d82ceSIvan Mikhaylov #define CMUN_CONFFIR0 0x20 /* Config Reg Parity FIR 0 */ 193494d82ceSIvan Mikhaylov #define CMUN_CONFFIR1 0x21 /* Config Reg Parity FIR 1 */ 194494d82ceSIvan Mikhaylov #define CMUN_CONFFIR2 0x22 /* Config Reg Parity FIR 2 */ 195494d82ceSIvan Mikhaylov #define CMUN_CONFFIR3 0x23 /* Config Reg Parity FIR 3 */ 196494d82ceSIvan Mikhaylov #define CMUN_URCR3_RS 0x24 /* Unit Reset Control Reg 3 Set */ 197494d82ceSIvan Mikhaylov #define CMUN_URCR3_C 0x25 /* Unit Reset Control Reg 3 Clear */ 198494d82ceSIvan Mikhaylov #define CMUN_URCR3_P 0x26 /* Unit Reset Control Reg 3 Pulse */ 199494d82ceSIvan Mikhaylov #define CMUN_PW0 0x2C /* Pulse Width Register */ 200494d82ceSIvan Mikhaylov #define CMUN_URCR0_P 0x2D /* Unit Reset Control Reg 0 Pulse */ 201494d82ceSIvan Mikhaylov #define CMUN_URCR1_P 0x2E /* Unit Reset Control Reg 1 Pulse */ 202494d82ceSIvan Mikhaylov #define CMUN_URCR2_P 0x2F /* Unit Reset Control Reg 2 Pulse */ 203494d82ceSIvan Mikhaylov #define CMUN_CLS_RW 0x30 /* Code Load Status (Read/Write) */ 204494d82ceSIvan Mikhaylov #define CMUN_CLS_S 0x31 /* Code Load Status (Set) */ 205494d82ceSIvan Mikhaylov #define CMUN_CLS_C 0x32 /* Code Load Status (Clear */ 206494d82ceSIvan Mikhaylov #define CMUN_URCR2_RS 0x33 /* Unit Reset Control Reg 2 Set */ 207494d82ceSIvan Mikhaylov #define CMUN_URCR2_C 0x34 /* Unit Reset Control Reg 2 Clear */ 208494d82ceSIvan Mikhaylov #define CMUN_CLKEN0 0x35 /* Clock Enable 0 */ 209494d82ceSIvan Mikhaylov #define CMUN_CLKEN1 0x36 /* Clock Enable 1 */ 210494d82ceSIvan Mikhaylov #define CMUN_PCD0 0x37 /* PSI clock divider 0 */ 211494d82ceSIvan Mikhaylov #define CMUN_PCD1 0x38 /* PSI clock divider 1 */ 212494d82ceSIvan Mikhaylov #define CMUN_TMR0 0x39 /* Reset Timer */ 213494d82ceSIvan Mikhaylov #define CMUN_TVS0 0x3A /* TV Sense Reg 0 */ 214494d82ceSIvan Mikhaylov #define CMUN_TVS1 0x3B /* TV Sense Reg 1 */ 215494d82ceSIvan Mikhaylov #define CMUN_MCCR 0x3C /* DRAM Configuration Reg */ 216494d82ceSIvan Mikhaylov #define CMUN_FIR0 0x3D /* Fault Isolation Reg 0 */ 217494d82ceSIvan Mikhaylov #define CMUN_FMR0 0x3E /* FIR Mask Reg 0 */ 218494d82ceSIvan Mikhaylov #define CMUN_ETDRB 0x3F /* ETDR Backdoor */ 219494d82ceSIvan Mikhaylov 220494d82ceSIvan Mikhaylov /* CRCS bit fields */ 221494d82ceSIvan Mikhaylov #define CRCS_STAT_MASK 0xF0000000 222494d82ceSIvan Mikhaylov #define CRCS_STAT_POR 0x10000000 223494d82ceSIvan Mikhaylov #define CRCS_STAT_PHR 0x20000000 224494d82ceSIvan Mikhaylov #define CRCS_STAT_PCIE 0x30000000 225494d82ceSIvan Mikhaylov #define CRCS_STAT_CRCS_SYS 0x40000000 226494d82ceSIvan Mikhaylov #define CRCS_STAT_DBCR_SYS 0x50000000 227494d82ceSIvan Mikhaylov #define CRCS_STAT_HOST_SYS 0x60000000 228494d82ceSIvan Mikhaylov #define CRCS_STAT_CHIP_RST_B 0x70000000 229494d82ceSIvan Mikhaylov #define CRCS_STAT_CRCS_CHIP 0x80000000 230494d82ceSIvan Mikhaylov #define CRCS_STAT_DBCR_CHIP 0x90000000 231494d82ceSIvan Mikhaylov #define CRCS_STAT_HOST_CHIP 0xA0000000 232494d82ceSIvan Mikhaylov #define CRCS_STAT_PSI_CHIP 0xB0000000 233494d82ceSIvan Mikhaylov #define CRCS_STAT_CRCS_CORE 0xC0000000 234494d82ceSIvan Mikhaylov #define CRCS_STAT_DBCR_CORE 0xD0000000 235494d82ceSIvan Mikhaylov #define CRCS_STAT_HOST_CORE 0xE0000000 236494d82ceSIvan Mikhaylov #define CRCS_STAT_PCIE_HOT 0xF0000000 237494d82ceSIvan Mikhaylov #define CRCS_STAT_SELF_CORE 0x40000000 238494d82ceSIvan Mikhaylov #define CRCS_STAT_SELF_CHIP 0x50000000 239494d82ceSIvan Mikhaylov #define CRCS_WATCHE 0x08000000 240494d82ceSIvan Mikhaylov #define CRCS_CORE 0x04000000 /* Reset PPC440 core */ 241494d82ceSIvan Mikhaylov #define CRCS_CHIP 0x02000000 /* Chip Reset */ 242494d82ceSIvan Mikhaylov #define CRCS_SYS 0x01000000 /* System Reset */ 243494d82ceSIvan Mikhaylov #define CRCS_WRCR 0x00800000 /* Watchdog reset on core reset */ 244494d82ceSIvan Mikhaylov #define CRCS_EXTCR 0x00080000 /* CHIP_RST_B triggers chip reset */ 245494d82ceSIvan Mikhaylov #define CRCS_PLOCK 0x00000002 /* PLL Locked */ 246494d82ceSIvan Mikhaylov 247494d82ceSIvan Mikhaylov #define mtcmu(reg, data) \ 248494d82ceSIvan Mikhaylov do { \ 249494d82ceSIvan Mikhaylov mtdcr(DCRN_CMU_ADDR, reg); \ 250494d82ceSIvan Mikhaylov mtdcr(DCRN_CMU_DATA, data); \ 251494d82ceSIvan Mikhaylov } while (0) 252494d82ceSIvan Mikhaylov 253494d82ceSIvan Mikhaylov #define mfcmu(reg)\ 254494d82ceSIvan Mikhaylov ({u32 data; \ 255494d82ceSIvan Mikhaylov mtdcr(DCRN_CMU_ADDR, reg); \ 256494d82ceSIvan Mikhaylov data = mfdcr(DCRN_CMU_DATA); \ 257494d82ceSIvan Mikhaylov data; }) 258494d82ceSIvan Mikhaylov 259494d82ceSIvan Mikhaylov #define mtl2(reg, data) \ 260494d82ceSIvan Mikhaylov do { \ 261494d82ceSIvan Mikhaylov mtdcr(DCRN_L2CDCRAI, reg); \ 262494d82ceSIvan Mikhaylov mtdcr(DCRN_L2CDCRDI, data); \ 263494d82ceSIvan Mikhaylov } while (0) 264494d82ceSIvan Mikhaylov 265494d82ceSIvan Mikhaylov #define mfl2(reg) \ 266494d82ceSIvan Mikhaylov ({u32 data; \ 267494d82ceSIvan Mikhaylov mtdcr(DCRN_L2CDCRAI, reg); \ 268494d82ceSIvan Mikhaylov data = mfdcr(DCRN_L2CDCRDI); \ 269494d82ceSIvan Mikhaylov data; }) 270494d82ceSIvan Mikhaylov 271494d82ceSIvan Mikhaylov #endif /* __KERNEL__ */ 272494d82ceSIvan Mikhaylov #endif /* _ASM_POWERPC_FSP2_DCR_H_ */ 273