1 /* 2 * FSP-2 board specific routines 3 * 4 * Based on earlier code: 5 * Matt Porter <mporter@kernel.crashing.org> 6 * Copyright 2002-2005 MontaVista Software Inc. 7 * 8 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> 9 * Copyright (c) 2003-2005 Zultys Technologies 10 * 11 * Rewritten and ported to the merged powerpc tree: 12 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation. 13 * 14 * This program is free software; you can redistribute it and/or modify it 15 * under the terms of the GNU General Public License as published by the 16 * Free Software Foundation; either version 2 of the License, or (at your 17 * option) any later version. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/of_platform.h> 22 #include <linux/rtc.h> 23 24 #include <asm/machdep.h> 25 #include <asm/prom.h> 26 #include <asm/udbg.h> 27 #include <asm/time.h> 28 #include <asm/uic.h> 29 #include <asm/ppc4xx.h> 30 #include <asm/dcr.h> 31 #include <linux/interrupt.h> 32 #include <linux/of_irq.h> 33 #include "fsp2.h" 34 35 #define FSP2_BUS_ERR "ibm,bus-error-irq" 36 #define FSP2_CMU_ERR "ibm,cmu-error-irq" 37 #define FSP2_CONF_ERR "ibm,conf-error-irq" 38 #define FSP2_OPBD_ERR "ibm,opbd-error-irq" 39 #define FSP2_MCUE "ibm,mc-ue-irq" 40 #define FSP2_RST_WRN "ibm,reset-warning-irq" 41 42 static __initdata struct of_device_id fsp2_of_bus[] = { 43 { .compatible = "ibm,plb4", }, 44 { .compatible = "ibm,plb6", }, 45 { .compatible = "ibm,opb", }, 46 {}, 47 }; 48 49 static void l2regs(void) 50 { 51 pr_err("L2 Controller:\n"); 52 pr_err("MCK: 0x%08x\n", mfl2(L2MCK)); 53 pr_err("INT: 0x%08x\n", mfl2(L2INT)); 54 pr_err("PLBSTAT0: 0x%08x\n", mfl2(L2PLBSTAT0)); 55 pr_err("PLBSTAT1: 0x%08x\n", mfl2(L2PLBSTAT1)); 56 pr_err("ARRSTAT0: 0x%08x\n", mfl2(L2ARRSTAT0)); 57 pr_err("ARRSTAT1: 0x%08x\n", mfl2(L2ARRSTAT1)); 58 pr_err("ARRSTAT2: 0x%08x\n", mfl2(L2ARRSTAT2)); 59 pr_err("CPUSTAT: 0x%08x\n", mfl2(L2CPUSTAT)); 60 pr_err("RACSTAT0: 0x%08x\n", mfl2(L2RACSTAT0)); 61 pr_err("WACSTAT0: 0x%08x\n", mfl2(L2WACSTAT0)); 62 pr_err("WACSTAT1: 0x%08x\n", mfl2(L2WACSTAT1)); 63 pr_err("WACSTAT2: 0x%08x\n", mfl2(L2WACSTAT2)); 64 pr_err("WDFSTAT: 0x%08x\n", mfl2(L2WDFSTAT)); 65 pr_err("LOG0: 0x%08x\n", mfl2(L2LOG0)); 66 pr_err("LOG1: 0x%08x\n", mfl2(L2LOG1)); 67 pr_err("LOG2: 0x%08x\n", mfl2(L2LOG2)); 68 pr_err("LOG3: 0x%08x\n", mfl2(L2LOG3)); 69 pr_err("LOG4: 0x%08x\n", mfl2(L2LOG4)); 70 pr_err("LOG5: 0x%08x\n", mfl2(L2LOG5)); 71 } 72 73 static void show_plbopb_regs(u32 base, int num) 74 { 75 pr_err("\nPLBOPB Bridge %d:\n", num); 76 pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0)); 77 pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1)); 78 pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2)); 79 pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU)); 80 pr_err("GEAR: 0x%08x\n", mfdcr(base + PLB4OPB_GEAR)); 81 } 82 83 static irqreturn_t bus_err_handler(int irq, void *data) 84 { 85 pr_err("Bus Error\n"); 86 87 l2regs(); 88 89 pr_err("\nPLB6 Controller:\n"); 90 pr_err("BC_SHD: 0x%08x\n", mfdcr(DCRN_PLB6_SHD)); 91 pr_err("BC_ERR: 0x%08x\n", mfdcr(DCRN_PLB6_ERR)); 92 93 pr_err("\nPLB6-to-PLB4 Bridge:\n"); 94 pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_ESR)); 95 pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARH)); 96 pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARL)); 97 98 pr_err("\nPLB4-to-PLB6 Bridge:\n"); 99 pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_ESR)); 100 pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARH)); 101 pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARL)); 102 103 pr_err("\nPLB6-to-MCIF Bridge:\n"); 104 pr_err("BESR0: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR0)); 105 pr_err("BESR1: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR1)); 106 pr_err("BEARH: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARH)); 107 pr_err("BEARL: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARL)); 108 109 pr_err("\nPLB4 Arbiter:\n"); 110 pr_err("P0ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRH)); 111 pr_err("P0ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRL)); 112 pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH)); 113 pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH)); 114 pr_err("P1ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRH)); 115 pr_err("P1ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRL)); 116 pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH)); 117 pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH)); 118 119 show_plbopb_regs(DCRN_PLB4OPB0_BASE, 0); 120 show_plbopb_regs(DCRN_PLB4OPB1_BASE, 1); 121 show_plbopb_regs(DCRN_PLB4OPB2_BASE, 2); 122 show_plbopb_regs(DCRN_PLB4OPB3_BASE, 3); 123 124 pr_err("\nPLB4-to-AHB Bridge:\n"); 125 pr_err("ESR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_ESR)); 126 pr_err("SEUAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SEUAR)); 127 pr_err("SELAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SELAR)); 128 129 pr_err("\nAHB-to-PLB4 Bridge:\n"); 130 pr_err("\nESR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_ESR)); 131 pr_err("\nEAR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_EAR)); 132 panic("Bus Error\n"); 133 } 134 135 static irqreturn_t cmu_err_handler(int irq, void *data) { 136 pr_err("CMU Error\n"); 137 pr_err("FIR0: 0x%08x\n", mfcmu(CMUN_FIR0)); 138 panic("CMU Error\n"); 139 } 140 141 static irqreturn_t conf_err_handler(int irq, void *data) { 142 pr_err("Configuration Logic Error\n"); 143 pr_err("CONF_FIR: 0x%08x\n", mfdcr(DCRN_CONF_FIR_RWC)); 144 pr_err("RPERR0: 0x%08x\n", mfdcr(DCRN_CONF_RPERR0)); 145 pr_err("RPERR1: 0x%08x\n", mfdcr(DCRN_CONF_RPERR1)); 146 panic("Configuration Logic Error\n"); 147 } 148 149 static irqreturn_t opbd_err_handler(int irq, void *data) { 150 panic("OPBD Error\n"); 151 } 152 153 static irqreturn_t mcue_handler(int irq, void *data) { 154 pr_err("DDR: Uncorrectable Error\n"); 155 pr_err("MCSTAT: 0x%08x\n", 156 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT)); 157 pr_err("MCOPT1: 0x%08x\n", 158 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT1)); 159 pr_err("MCOPT2: 0x%08x\n", 160 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT2)); 161 pr_err("PHYSTAT: 0x%08x\n", 162 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_PHYSTAT)); 163 pr_err("CFGR0: 0x%08x\n", 164 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0)); 165 pr_err("CFGR1: 0x%08x\n", 166 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1)); 167 pr_err("CFGR2: 0x%08x\n", 168 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2)); 169 pr_err("CFGR3: 0x%08x\n", 170 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3)); 171 pr_err("SCRUB_CNTL: 0x%08x\n", 172 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_SCRUB_CNTL)); 173 pr_err("ECCERR_PORT0: 0x%08x\n", 174 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_PORT0)); 175 pr_err("ECCERR_ADDR_PORT0: 0x%08x\n", 176 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_ADDR_PORT0)); 177 pr_err("ECCERR_CNT_PORT0: 0x%08x\n", 178 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_COUNT_PORT0)); 179 pr_err("ECC_CHECK_PORT0: 0x%08x\n", 180 mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECC_CHECK_PORT0)); 181 pr_err("MCER0: 0x%08x\n", 182 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0)); 183 pr_err("MCER1: 0x%08x\n", 184 mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1)); 185 pr_err("BESR: 0x%08x\n", 186 mfdcr(DCRN_PLB6MCIF_BESR0)); 187 pr_err("BEARL: 0x%08x\n", 188 mfdcr(DCRN_PLB6MCIF_BEARL)); 189 pr_err("BEARH: 0x%08x\n", 190 mfdcr(DCRN_PLB6MCIF_BEARH)); 191 panic("DDR: Uncorrectable Error\n"); 192 } 193 194 static irqreturn_t rst_wrn_handler(int irq, void *data) { 195 u32 crcs = mfcmu(CMUN_CRCS); 196 switch (crcs & CRCS_STAT_MASK) { 197 case CRCS_STAT_CHIP_RST_B: 198 panic("Received chassis-initiated reset request"); 199 default: 200 panic("Unknown external reset: CRCS=0x%x", crcs); 201 } 202 } 203 204 static void node_irq_request(const char *compat, irq_handler_t errirq_handler) 205 { 206 struct device_node *np; 207 unsigned int irq; 208 int32_t rc; 209 210 for_each_compatible_node(np, NULL, compat) { 211 irq = irq_of_parse_and_map(np, 0); 212 if (irq == NO_IRQ) { 213 pr_err("device tree node %pOFn is missing a interrupt", 214 np); 215 return; 216 } 217 218 rc = request_irq(irq, errirq_handler, 0, np->name, np); 219 if (rc) { 220 pr_err("fsp_of_probe: request_irq failed: np=%pOF rc=%d", 221 np, rc); 222 return; 223 } 224 } 225 } 226 227 static void critical_irq_setup(void) 228 { 229 node_irq_request(FSP2_CMU_ERR, cmu_err_handler); 230 node_irq_request(FSP2_BUS_ERR, bus_err_handler); 231 node_irq_request(FSP2_CONF_ERR, conf_err_handler); 232 node_irq_request(FSP2_OPBD_ERR, opbd_err_handler); 233 node_irq_request(FSP2_MCUE, mcue_handler); 234 node_irq_request(FSP2_RST_WRN, rst_wrn_handler); 235 } 236 237 static int __init fsp2_device_probe(void) 238 { 239 of_platform_bus_probe(NULL, fsp2_of_bus, NULL); 240 return 0; 241 } 242 machine_device_initcall(fsp2, fsp2_device_probe); 243 244 static int __init fsp2_probe(void) 245 { 246 u32 val; 247 unsigned long root = of_get_flat_dt_root(); 248 249 if (!of_flat_dt_is_compatible(root, "ibm,fsp2")) 250 return 0; 251 252 /* Clear BC_ERR and mask snoopable request plb errors. */ 253 val = mfdcr(DCRN_PLB6_CR0); 254 val |= 0x20000000; 255 mtdcr(DCRN_PLB6_BASE, val); 256 mtdcr(DCRN_PLB6_HD, 0xffff0000); 257 mtdcr(DCRN_PLB6_SHD, 0xffff0000); 258 259 /* TVSENSE reset is blocked (clock gated) by the POR default of the TVS 260 * sleep config bit. As a consequence, TVSENSE will provide erratic 261 * sensor values, which may result in spurious (parity) errors 262 * recorded in the CMU FIR and leading to erroneous interrupt requests 263 * once the CMU interrupt is unmasked. 264 */ 265 266 /* 1. set TVS1[UNDOZE] */ 267 val = mfcmu(CMUN_TVS1); 268 val |= 0x4; 269 mtcmu(CMUN_TVS1, val); 270 271 /* 2. clear FIR[TVS] and FIR[TVSPAR] */ 272 val = mfcmu(CMUN_FIR0); 273 val |= 0x30000000; 274 mtcmu(CMUN_FIR0, val); 275 276 /* L2 machine checks */ 277 mtl2(L2PLBMCKEN0, 0xffffffff); 278 mtl2(L2PLBMCKEN1, 0x0000ffff); 279 mtl2(L2ARRMCKEN0, 0xffffffff); 280 mtl2(L2ARRMCKEN1, 0xffffffff); 281 mtl2(L2ARRMCKEN2, 0xfffff000); 282 mtl2(L2CPUMCKEN, 0xffffffff); 283 mtl2(L2RACMCKEN0, 0xffffffff); 284 mtl2(L2WACMCKEN0, 0xffffffff); 285 mtl2(L2WACMCKEN1, 0xffffffff); 286 mtl2(L2WACMCKEN2, 0xffffffff); 287 mtl2(L2WDFMCKEN, 0xffffffff); 288 289 /* L2 interrupts */ 290 mtl2(L2PLBINTEN1, 0xffff0000); 291 292 /* 293 * At a global level, enable all L2 machine checks and interrupts 294 * reported by the L2 subsystems, except for the external machine check 295 * input (UIC0.1). 296 */ 297 mtl2(L2MCKEN, 0x000007ff); 298 mtl2(L2INTEN, 0x000004ff); 299 300 /* Enable FSP-2 configuration logic parity errors */ 301 mtdcr(DCRN_CONF_EIR_RS, 0x80000000); 302 return 1; 303 } 304 305 static void __init fsp2_irq_init(void) 306 { 307 uic_init_tree(); 308 critical_irq_setup(); 309 } 310 311 define_machine(fsp2) { 312 .name = "FSP-2", 313 .probe = fsp2_probe, 314 .progress = udbg_progress, 315 .init_IRQ = fsp2_irq_init, 316 .get_irq = uic_get_irq, 317 .restart = ppc4xx_reset_system, 318 .calibrate_decr = generic_calibrate_decr, 319 }; 320