1 /* 2 * Performance counter support for POWER9 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * Copyright 2013 Michael Ellerman, IBM Corporation. 6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or later version. 12 */ 13 14 #define pr_fmt(fmt) "power9-pmu: " fmt 15 16 #include "isa207-common.h" 17 18 /* 19 * Raw event encoding for Power9: 20 * 21 * 60 56 52 48 44 40 36 32 22 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 23 * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ] 24 * | | | | | 25 * | | *- IFM (Linux) | thresh start/stop -* 26 * | *- BHRB (Linux) *sm 27 * *- EBB (Linux) 28 * 29 * 28 24 20 16 12 8 4 0 30 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 31 * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ] 32 * | | | | | 33 * | | | | *- mark 34 * | | *- L1/L2/L3 cache_sel | 35 * | | | 36 * | *- sampling mode for marked events *- combine 37 * | 38 * *- thresh_sel 39 * 40 * Below uses IBM bit numbering. 41 * 42 * MMCR1[x:y] = unit (PMCxUNIT) 43 * MMCR1[24] = pmc1combine[0] 44 * MMCR1[25] = pmc1combine[1] 45 * MMCR1[26] = pmc2combine[0] 46 * MMCR1[27] = pmc2combine[1] 47 * MMCR1[28] = pmc3combine[0] 48 * MMCR1[29] = pmc3combine[1] 49 * MMCR1[30] = pmc4combine[0] 50 * MMCR1[31] = pmc4combine[1] 51 * 52 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 53 * MMCR1[20:27] = thresh_ctl 54 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 55 * MMCR1[20:27] = thresh_ctl 56 * else 57 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 58 * 59 * if thresh_sel: 60 * MMCRA[45:47] = thresh_sel 61 * 62 * if thresh_cmp: 63 * MMCRA[9:11] = thresh_cmp[0:2] 64 * MMCRA[12:18] = thresh_cmp[3:9] 65 * 66 * if unit == 6 or unit == 7 67 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) 68 * else if unit == 8 or unit == 9: 69 * if cache_sel[0] == 0: # L3 bank 70 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) 71 * else if cache_sel[0] == 1: 72 * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) 73 * else if cache_sel[1]: # L1 event 74 * MMCR1[16] = cache_sel[2] 75 * MMCR1[17] = cache_sel[3] 76 * 77 * if mark: 78 * MMCRA[63] = 1 (SAMPLE_ENABLE) 79 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 80 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 81 * 82 * if EBB and BHRB: 83 * MMCRA[32:33] = IFM 84 * 85 * MMCRA[SDAR_MODE] = sm 86 */ 87 88 /* 89 * Some power9 event codes. 90 */ 91 #define EVENT(_name, _code) _name = _code, 92 93 enum { 94 #include "power9-events-list.h" 95 }; 96 97 #undef EVENT 98 99 /* MMCRA IFM bits - POWER9 */ 100 #define POWER9_MMCRA_IFM1 0x0000000040000000UL 101 #define POWER9_MMCRA_IFM2 0x0000000080000000UL 102 #define POWER9_MMCRA_IFM3 0x00000000C0000000UL 103 104 /* PowerISA v2.07 format attribute structure*/ 105 extern struct attribute_group isa207_pmu_format_group; 106 107 /* Table of alternatives, sorted by column 0 */ 108 static const unsigned int power9_event_alternatives[][MAX_ALT] = { 109 { PM_INST_DISP, PM_INST_DISP_ALT }, 110 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 111 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 112 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT }, 113 { PM_BR_2PATH, PM_BR_2PATH_ALT }, 114 }; 115 116 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 117 { 118 int num_alt = 0; 119 120 num_alt = isa207_get_alternatives(event, alt, 121 ARRAY_SIZE(power9_event_alternatives), flags, 122 power9_event_alternatives); 123 124 return num_alt; 125 } 126 127 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 128 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC); 129 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 130 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 131 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 132 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 133 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 134 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN); 135 136 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN); 137 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 138 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 139 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 140 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 141 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 142 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 143 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 144 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 145 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 146 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 147 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 148 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 149 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 150 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 151 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 152 153 static struct attribute *power9_events_attr[] = { 154 GENERIC_EVENT_PTR(PM_CYC), 155 GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC), 156 GENERIC_EVENT_PTR(PM_CMPLU_STALL), 157 GENERIC_EVENT_PTR(PM_INST_CMPL), 158 GENERIC_EVENT_PTR(PM_BR_CMPL), 159 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 160 GENERIC_EVENT_PTR(PM_LD_REF_L1), 161 GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN), 162 CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN), 163 CACHE_EVENT_PTR(PM_LD_REF_L1), 164 CACHE_EVENT_PTR(PM_L1_PREF), 165 CACHE_EVENT_PTR(PM_ST_MISS_L1), 166 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 167 CACHE_EVENT_PTR(PM_INST_FROM_L1), 168 CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 169 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 170 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 171 CACHE_EVENT_PTR(PM_L3_PREF_ALL), 172 CACHE_EVENT_PTR(PM_L2_ST_MISS), 173 CACHE_EVENT_PTR(PM_L2_ST), 174 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 175 CACHE_EVENT_PTR(PM_BR_CMPL), 176 CACHE_EVENT_PTR(PM_DTLB_MISS), 177 CACHE_EVENT_PTR(PM_ITLB_MISS), 178 NULL 179 }; 180 181 static struct attribute_group power9_pmu_events_group = { 182 .name = "events", 183 .attrs = power9_events_attr, 184 }; 185 186 static const struct attribute_group *power9_isa207_pmu_attr_groups[] = { 187 &isa207_pmu_format_group, 188 &power9_pmu_events_group, 189 NULL, 190 }; 191 192 PMU_FORMAT_ATTR(event, "config:0-51"); 193 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 194 PMU_FORMAT_ATTR(mark, "config:8"); 195 PMU_FORMAT_ATTR(combine, "config:10-11"); 196 PMU_FORMAT_ATTR(unit, "config:12-15"); 197 PMU_FORMAT_ATTR(pmc, "config:16-19"); 198 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 199 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 200 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 201 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 202 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 203 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 204 PMU_FORMAT_ATTR(sdar_mode, "config:50-51"); 205 206 static struct attribute *power9_pmu_format_attr[] = { 207 &format_attr_event.attr, 208 &format_attr_pmcxsel.attr, 209 &format_attr_mark.attr, 210 &format_attr_combine.attr, 211 &format_attr_unit.attr, 212 &format_attr_pmc.attr, 213 &format_attr_cache_sel.attr, 214 &format_attr_sample_mode.attr, 215 &format_attr_thresh_sel.attr, 216 &format_attr_thresh_stop.attr, 217 &format_attr_thresh_start.attr, 218 &format_attr_thresh_cmp.attr, 219 &format_attr_sdar_mode.attr, 220 NULL, 221 }; 222 223 static struct attribute_group power9_pmu_format_group = { 224 .name = "format", 225 .attrs = power9_pmu_format_attr, 226 }; 227 228 static const struct attribute_group *power9_pmu_attr_groups[] = { 229 &power9_pmu_format_group, 230 &power9_pmu_events_group, 231 NULL, 232 }; 233 234 static int power9_generic_events_dd1[] = { 235 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 236 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 237 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 238 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_DISP, 239 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL_ALT, 240 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 241 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 242 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN, 243 }; 244 245 static int power9_generic_events[] = { 246 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 247 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 248 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 249 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 250 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 251 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 252 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 253 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN, 254 }; 255 256 static u64 power9_bhrb_filter_map(u64 branch_sample_type) 257 { 258 u64 pmu_bhrb_filter = 0; 259 260 /* BHRB and regular PMU events share the same privilege state 261 * filter configuration. BHRB is always recorded along with a 262 * regular PMU event. As the privilege state filter is handled 263 * in the basic PMC configuration of the accompanying regular 264 * PMU event, we ignore any separate BHRB specific request. 265 */ 266 267 /* No branch filter requested */ 268 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 269 return pmu_bhrb_filter; 270 271 /* Invalid branch filter options - HW does not support */ 272 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 273 return -1; 274 275 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 276 return -1; 277 278 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 279 return -1; 280 281 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 282 pmu_bhrb_filter |= POWER9_MMCRA_IFM1; 283 return pmu_bhrb_filter; 284 } 285 286 /* Every thing else is unsupported */ 287 return -1; 288 } 289 290 static void power9_config_bhrb(u64 pmu_bhrb_filter) 291 { 292 /* Enable BHRB filter in PMU */ 293 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 294 } 295 296 #define C(x) PERF_COUNT_HW_CACHE_##x 297 298 /* 299 * Table of generalized cache-related events. 300 * 0 means not supported, -1 means nonsensical, other values 301 * are event codes. 302 */ 303 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 304 [ C(L1D) ] = { 305 [ C(OP_READ) ] = { 306 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 307 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN, 308 }, 309 [ C(OP_WRITE) ] = { 310 [ C(RESULT_ACCESS) ] = 0, 311 [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 312 }, 313 [ C(OP_PREFETCH) ] = { 314 [ C(RESULT_ACCESS) ] = PM_L1_PREF, 315 [ C(RESULT_MISS) ] = 0, 316 }, 317 }, 318 [ C(L1I) ] = { 319 [ C(OP_READ) ] = { 320 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 321 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 322 }, 323 [ C(OP_WRITE) ] = { 324 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 325 [ C(RESULT_MISS) ] = -1, 326 }, 327 [ C(OP_PREFETCH) ] = { 328 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 329 [ C(RESULT_MISS) ] = 0, 330 }, 331 }, 332 [ C(LL) ] = { 333 [ C(OP_READ) ] = { 334 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 335 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 336 }, 337 [ C(OP_WRITE) ] = { 338 [ C(RESULT_ACCESS) ] = PM_L2_ST, 339 [ C(RESULT_MISS) ] = PM_L2_ST_MISS, 340 }, 341 [ C(OP_PREFETCH) ] = { 342 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 343 [ C(RESULT_MISS) ] = 0, 344 }, 345 }, 346 [ C(DTLB) ] = { 347 [ C(OP_READ) ] = { 348 [ C(RESULT_ACCESS) ] = 0, 349 [ C(RESULT_MISS) ] = PM_DTLB_MISS, 350 }, 351 [ C(OP_WRITE) ] = { 352 [ C(RESULT_ACCESS) ] = -1, 353 [ C(RESULT_MISS) ] = -1, 354 }, 355 [ C(OP_PREFETCH) ] = { 356 [ C(RESULT_ACCESS) ] = -1, 357 [ C(RESULT_MISS) ] = -1, 358 }, 359 }, 360 [ C(ITLB) ] = { 361 [ C(OP_READ) ] = { 362 [ C(RESULT_ACCESS) ] = 0, 363 [ C(RESULT_MISS) ] = PM_ITLB_MISS, 364 }, 365 [ C(OP_WRITE) ] = { 366 [ C(RESULT_ACCESS) ] = -1, 367 [ C(RESULT_MISS) ] = -1, 368 }, 369 [ C(OP_PREFETCH) ] = { 370 [ C(RESULT_ACCESS) ] = -1, 371 [ C(RESULT_MISS) ] = -1, 372 }, 373 }, 374 [ C(BPU) ] = { 375 [ C(OP_READ) ] = { 376 [ C(RESULT_ACCESS) ] = PM_BR_CMPL, 377 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 378 }, 379 [ C(OP_WRITE) ] = { 380 [ C(RESULT_ACCESS) ] = -1, 381 [ C(RESULT_MISS) ] = -1, 382 }, 383 [ C(OP_PREFETCH) ] = { 384 [ C(RESULT_ACCESS) ] = -1, 385 [ C(RESULT_MISS) ] = -1, 386 }, 387 }, 388 [ C(NODE) ] = { 389 [ C(OP_READ) ] = { 390 [ C(RESULT_ACCESS) ] = -1, 391 [ C(RESULT_MISS) ] = -1, 392 }, 393 [ C(OP_WRITE) ] = { 394 [ C(RESULT_ACCESS) ] = -1, 395 [ C(RESULT_MISS) ] = -1, 396 }, 397 [ C(OP_PREFETCH) ] = { 398 [ C(RESULT_ACCESS) ] = -1, 399 [ C(RESULT_MISS) ] = -1, 400 }, 401 }, 402 }; 403 404 #undef C 405 406 static struct power_pmu power9_isa207_pmu = { 407 .name = "POWER9", 408 .n_counter = MAX_PMU_COUNTERS, 409 .add_fields = ISA207_ADD_FIELDS, 410 .test_adder = P9_DD1_TEST_ADDER, 411 .compute_mmcr = isa207_compute_mmcr, 412 .config_bhrb = power9_config_bhrb, 413 .bhrb_filter_map = power9_bhrb_filter_map, 414 .get_constraint = isa207_get_constraint, 415 .get_alternatives = power9_get_alternatives, 416 .disable_pmc = isa207_disable_pmc, 417 .flags = PPMU_NO_SIAR | PPMU_ARCH_207S, 418 .n_generic = ARRAY_SIZE(power9_generic_events_dd1), 419 .generic_events = power9_generic_events_dd1, 420 .cache_events = &power9_cache_events, 421 .attr_groups = power9_isa207_pmu_attr_groups, 422 .bhrb_nr = 32, 423 }; 424 425 static struct power_pmu power9_pmu = { 426 .name = "POWER9", 427 .n_counter = MAX_PMU_COUNTERS, 428 .add_fields = ISA207_ADD_FIELDS, 429 .test_adder = ISA207_TEST_ADDER, 430 .compute_mmcr = isa207_compute_mmcr, 431 .config_bhrb = power9_config_bhrb, 432 .bhrb_filter_map = power9_bhrb_filter_map, 433 .get_constraint = isa207_get_constraint, 434 .get_alternatives = power9_get_alternatives, 435 .get_mem_data_src = isa207_get_mem_data_src, 436 .get_mem_weight = isa207_get_mem_weight, 437 .disable_pmc = isa207_disable_pmc, 438 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 439 .n_generic = ARRAY_SIZE(power9_generic_events), 440 .generic_events = power9_generic_events, 441 .cache_events = &power9_cache_events, 442 .attr_groups = power9_pmu_attr_groups, 443 .bhrb_nr = 32, 444 }; 445 446 static int __init init_power9_pmu(void) 447 { 448 int rc = 0; 449 450 /* Comes from cpu_specs[] */ 451 if (!cur_cpu_spec->oprofile_cpu_type || 452 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9")) 453 return -ENODEV; 454 455 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 456 /* 457 * Since PM_INST_CMPL may not provide right counts in all 458 * sampling scenarios in power9 DD1, instead use PM_INST_DISP. 459 */ 460 EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP; 461 /* 462 * Power9 DD1 should use PM_BR_CMPL_ALT event code for 463 * "branches" to provide correct counter value. 464 */ 465 EVENT_VAR(PM_BR_CMPL, _g).id = PM_BR_CMPL_ALT; 466 EVENT_VAR(PM_BR_CMPL, _c).id = PM_BR_CMPL_ALT; 467 rc = register_power_pmu(&power9_isa207_pmu); 468 } else { 469 rc = register_power_pmu(&power9_pmu); 470 } 471 472 if (rc) 473 return rc; 474 475 /* Tell userspace that EBB is supported */ 476 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 477 478 return 0; 479 } 480 early_initcall(init_power9_pmu); 481