1 /* 2 * Performance counter support for POWER9 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * Copyright 2013 Michael Ellerman, IBM Corporation. 6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or later version. 12 */ 13 14 #define pr_fmt(fmt) "power9-pmu: " fmt 15 16 #include "isa207-common.h" 17 18 /* 19 * Raw event encoding for Power9: 20 * 21 * 60 56 52 48 44 40 36 32 22 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 23 * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ] 24 * | | | | | 25 * | | *- IFM (Linux) | thresh start/stop -* 26 * | *- BHRB (Linux) *sm 27 * *- EBB (Linux) 28 * 29 * 28 24 20 16 12 8 4 0 30 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 31 * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ] 32 * | | | | | 33 * | | | | *- mark 34 * | | *- L1/L2/L3 cache_sel | 35 * | | | 36 * | *- sampling mode for marked events *- combine 37 * | 38 * *- thresh_sel 39 * 40 * Below uses IBM bit numbering. 41 * 42 * MMCR1[x:y] = unit (PMCxUNIT) 43 * MMCR1[24] = pmc1combine[0] 44 * MMCR1[25] = pmc1combine[1] 45 * MMCR1[26] = pmc2combine[0] 46 * MMCR1[27] = pmc2combine[1] 47 * MMCR1[28] = pmc3combine[0] 48 * MMCR1[29] = pmc3combine[1] 49 * MMCR1[30] = pmc4combine[0] 50 * MMCR1[31] = pmc4combine[1] 51 * 52 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 53 * MMCR1[20:27] = thresh_ctl 54 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 55 * MMCR1[20:27] = thresh_ctl 56 * else 57 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 58 * 59 * if thresh_sel: 60 * MMCRA[45:47] = thresh_sel 61 * 62 * if thresh_cmp: 63 * MMCRA[9:11] = thresh_cmp[0:2] 64 * MMCRA[12:18] = thresh_cmp[3:9] 65 * 66 * if unit == 6 or unit == 7 67 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) 68 * else if unit == 8 or unit == 9: 69 * if cache_sel[0] == 0: # L3 bank 70 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) 71 * else if cache_sel[0] == 1: 72 * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) 73 * else if cache_sel[1]: # L1 event 74 * MMCR1[16] = cache_sel[2] 75 * MMCR1[17] = cache_sel[3] 76 * 77 * if mark: 78 * MMCRA[63] = 1 (SAMPLE_ENABLE) 79 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 80 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 81 * 82 * if EBB and BHRB: 83 * MMCRA[32:33] = IFM 84 * 85 * MMCRA[SDAR_MODE] = sm 86 */ 87 88 /* 89 * Some power9 event codes. 90 */ 91 #define EVENT(_name, _code) _name = _code, 92 93 enum { 94 #include "power9-events-list.h" 95 }; 96 97 #undef EVENT 98 99 /* MMCRA IFM bits - POWER9 */ 100 #define POWER9_MMCRA_IFM1 0x0000000040000000UL 101 #define POWER9_MMCRA_IFM2 0x0000000080000000UL 102 #define POWER9_MMCRA_IFM3 0x00000000C0000000UL 103 104 /* PowerISA v2.07 format attribute structure*/ 105 extern struct attribute_group isa207_pmu_format_group; 106 107 /* Table of alternatives, sorted by column 0 */ 108 static const unsigned int power9_event_alternatives[][MAX_ALT] = { 109 { PM_INST_DISP, PM_INST_DISP_ALT }, 110 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 111 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 112 }; 113 114 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 115 { 116 int num_alt = 0; 117 118 num_alt = isa207_get_alternatives(event, alt, power9_event_alternatives, 119 (int)ARRAY_SIZE(power9_event_alternatives)); 120 121 return num_alt; 122 } 123 124 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 125 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC); 126 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 127 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 128 GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_CMPL); 129 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 130 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 131 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN); 132 133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN); 134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 135 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 136 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 137 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 138 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 139 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 140 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 141 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 142 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 143 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 144 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 145 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 146 CACHE_EVENT_ATTR(branch-loads, PM_BRU_CMPL); 147 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 148 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 149 150 static struct attribute *power9_events_attr[] = { 151 GENERIC_EVENT_PTR(PM_CYC), 152 GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC), 153 GENERIC_EVENT_PTR(PM_CMPLU_STALL), 154 GENERIC_EVENT_PTR(PM_INST_CMPL), 155 GENERIC_EVENT_PTR(PM_BRU_CMPL), 156 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 157 GENERIC_EVENT_PTR(PM_LD_REF_L1), 158 GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN), 159 CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN), 160 CACHE_EVENT_PTR(PM_LD_REF_L1), 161 CACHE_EVENT_PTR(PM_L1_PREF), 162 CACHE_EVENT_PTR(PM_ST_MISS_L1), 163 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 164 CACHE_EVENT_PTR(PM_INST_FROM_L1), 165 CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 166 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 167 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 168 CACHE_EVENT_PTR(PM_L3_PREF_ALL), 169 CACHE_EVENT_PTR(PM_L2_ST_MISS), 170 CACHE_EVENT_PTR(PM_L2_ST), 171 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 172 CACHE_EVENT_PTR(PM_BRU_CMPL), 173 CACHE_EVENT_PTR(PM_DTLB_MISS), 174 CACHE_EVENT_PTR(PM_ITLB_MISS), 175 NULL 176 }; 177 178 static struct attribute_group power9_pmu_events_group = { 179 .name = "events", 180 .attrs = power9_events_attr, 181 }; 182 183 static const struct attribute_group *power9_isa207_pmu_attr_groups[] = { 184 &isa207_pmu_format_group, 185 &power9_pmu_events_group, 186 NULL, 187 }; 188 189 PMU_FORMAT_ATTR(event, "config:0-51"); 190 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 191 PMU_FORMAT_ATTR(mark, "config:8"); 192 PMU_FORMAT_ATTR(combine, "config:10-11"); 193 PMU_FORMAT_ATTR(unit, "config:12-15"); 194 PMU_FORMAT_ATTR(pmc, "config:16-19"); 195 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 196 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 197 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 198 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 199 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 200 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 201 PMU_FORMAT_ATTR(sdar_mode, "config:50-51"); 202 203 static struct attribute *power9_pmu_format_attr[] = { 204 &format_attr_event.attr, 205 &format_attr_pmcxsel.attr, 206 &format_attr_mark.attr, 207 &format_attr_combine.attr, 208 &format_attr_unit.attr, 209 &format_attr_pmc.attr, 210 &format_attr_cache_sel.attr, 211 &format_attr_sample_mode.attr, 212 &format_attr_thresh_sel.attr, 213 &format_attr_thresh_stop.attr, 214 &format_attr_thresh_start.attr, 215 &format_attr_thresh_cmp.attr, 216 &format_attr_sdar_mode.attr, 217 NULL, 218 }; 219 220 static struct attribute_group power9_pmu_format_group = { 221 .name = "format", 222 .attrs = power9_pmu_format_attr, 223 }; 224 225 static const struct attribute_group *power9_pmu_attr_groups[] = { 226 &power9_pmu_format_group, 227 &power9_pmu_events_group, 228 NULL, 229 }; 230 231 static int power9_generic_events_dd1[] = { 232 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 233 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 234 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 235 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_DISP, 236 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL_ALT, 237 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 238 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 239 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN, 240 }; 241 242 static int power9_generic_events[] = { 243 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 244 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 245 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 246 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 247 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_CMPL, 248 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 249 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 250 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN, 251 }; 252 253 static u64 power9_bhrb_filter_map(u64 branch_sample_type) 254 { 255 u64 pmu_bhrb_filter = 0; 256 257 /* BHRB and regular PMU events share the same privilege state 258 * filter configuration. BHRB is always recorded along with a 259 * regular PMU event. As the privilege state filter is handled 260 * in the basic PMC configuration of the accompanying regular 261 * PMU event, we ignore any separate BHRB specific request. 262 */ 263 264 /* No branch filter requested */ 265 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 266 return pmu_bhrb_filter; 267 268 /* Invalid branch filter options - HW does not support */ 269 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 270 return -1; 271 272 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 273 return -1; 274 275 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 276 return -1; 277 278 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 279 pmu_bhrb_filter |= POWER9_MMCRA_IFM1; 280 return pmu_bhrb_filter; 281 } 282 283 /* Every thing else is unsupported */ 284 return -1; 285 } 286 287 static void power9_config_bhrb(u64 pmu_bhrb_filter) 288 { 289 /* Enable BHRB filter in PMU */ 290 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 291 } 292 293 #define C(x) PERF_COUNT_HW_CACHE_##x 294 295 /* 296 * Table of generalized cache-related events. 297 * 0 means not supported, -1 means nonsensical, other values 298 * are event codes. 299 */ 300 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 301 [ C(L1D) ] = { 302 [ C(OP_READ) ] = { 303 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 304 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN, 305 }, 306 [ C(OP_WRITE) ] = { 307 [ C(RESULT_ACCESS) ] = 0, 308 [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 309 }, 310 [ C(OP_PREFETCH) ] = { 311 [ C(RESULT_ACCESS) ] = PM_L1_PREF, 312 [ C(RESULT_MISS) ] = 0, 313 }, 314 }, 315 [ C(L1I) ] = { 316 [ C(OP_READ) ] = { 317 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 318 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 319 }, 320 [ C(OP_WRITE) ] = { 321 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 322 [ C(RESULT_MISS) ] = -1, 323 }, 324 [ C(OP_PREFETCH) ] = { 325 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 326 [ C(RESULT_MISS) ] = 0, 327 }, 328 }, 329 [ C(LL) ] = { 330 [ C(OP_READ) ] = { 331 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 332 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 333 }, 334 [ C(OP_WRITE) ] = { 335 [ C(RESULT_ACCESS) ] = PM_L2_ST, 336 [ C(RESULT_MISS) ] = PM_L2_ST_MISS, 337 }, 338 [ C(OP_PREFETCH) ] = { 339 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 340 [ C(RESULT_MISS) ] = 0, 341 }, 342 }, 343 [ C(DTLB) ] = { 344 [ C(OP_READ) ] = { 345 [ C(RESULT_ACCESS) ] = 0, 346 [ C(RESULT_MISS) ] = PM_DTLB_MISS, 347 }, 348 [ C(OP_WRITE) ] = { 349 [ C(RESULT_ACCESS) ] = -1, 350 [ C(RESULT_MISS) ] = -1, 351 }, 352 [ C(OP_PREFETCH) ] = { 353 [ C(RESULT_ACCESS) ] = -1, 354 [ C(RESULT_MISS) ] = -1, 355 }, 356 }, 357 [ C(ITLB) ] = { 358 [ C(OP_READ) ] = { 359 [ C(RESULT_ACCESS) ] = 0, 360 [ C(RESULT_MISS) ] = PM_ITLB_MISS, 361 }, 362 [ C(OP_WRITE) ] = { 363 [ C(RESULT_ACCESS) ] = -1, 364 [ C(RESULT_MISS) ] = -1, 365 }, 366 [ C(OP_PREFETCH) ] = { 367 [ C(RESULT_ACCESS) ] = -1, 368 [ C(RESULT_MISS) ] = -1, 369 }, 370 }, 371 [ C(BPU) ] = { 372 [ C(OP_READ) ] = { 373 [ C(RESULT_ACCESS) ] = PM_BRU_CMPL, 374 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 375 }, 376 [ C(OP_WRITE) ] = { 377 [ C(RESULT_ACCESS) ] = -1, 378 [ C(RESULT_MISS) ] = -1, 379 }, 380 [ C(OP_PREFETCH) ] = { 381 [ C(RESULT_ACCESS) ] = -1, 382 [ C(RESULT_MISS) ] = -1, 383 }, 384 }, 385 [ C(NODE) ] = { 386 [ C(OP_READ) ] = { 387 [ C(RESULT_ACCESS) ] = -1, 388 [ C(RESULT_MISS) ] = -1, 389 }, 390 [ C(OP_WRITE) ] = { 391 [ C(RESULT_ACCESS) ] = -1, 392 [ C(RESULT_MISS) ] = -1, 393 }, 394 [ C(OP_PREFETCH) ] = { 395 [ C(RESULT_ACCESS) ] = -1, 396 [ C(RESULT_MISS) ] = -1, 397 }, 398 }, 399 }; 400 401 #undef C 402 403 static struct power_pmu power9_isa207_pmu = { 404 .name = "POWER9", 405 .n_counter = MAX_PMU_COUNTERS, 406 .add_fields = ISA207_ADD_FIELDS, 407 .test_adder = P9_DD1_TEST_ADDER, 408 .compute_mmcr = isa207_compute_mmcr, 409 .config_bhrb = power9_config_bhrb, 410 .bhrb_filter_map = power9_bhrb_filter_map, 411 .get_constraint = isa207_get_constraint, 412 .get_alternatives = power9_get_alternatives, 413 .disable_pmc = isa207_disable_pmc, 414 .flags = PPMU_NO_SIAR | PPMU_ARCH_207S, 415 .n_generic = ARRAY_SIZE(power9_generic_events_dd1), 416 .generic_events = power9_generic_events_dd1, 417 .cache_events = &power9_cache_events, 418 .attr_groups = power9_isa207_pmu_attr_groups, 419 .bhrb_nr = 32, 420 }; 421 422 static struct power_pmu power9_pmu = { 423 .name = "POWER9", 424 .n_counter = MAX_PMU_COUNTERS, 425 .add_fields = ISA207_ADD_FIELDS, 426 .test_adder = ISA207_TEST_ADDER, 427 .compute_mmcr = isa207_compute_mmcr, 428 .config_bhrb = power9_config_bhrb, 429 .bhrb_filter_map = power9_bhrb_filter_map, 430 .get_constraint = isa207_get_constraint, 431 .get_alternatives = power9_get_alternatives, 432 .get_mem_data_src = isa207_get_mem_data_src, 433 .get_mem_weight = isa207_get_mem_weight, 434 .disable_pmc = isa207_disable_pmc, 435 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 436 .n_generic = ARRAY_SIZE(power9_generic_events), 437 .generic_events = power9_generic_events, 438 .cache_events = &power9_cache_events, 439 .attr_groups = power9_pmu_attr_groups, 440 .bhrb_nr = 32, 441 }; 442 443 static int __init init_power9_pmu(void) 444 { 445 int rc = 0; 446 447 /* Comes from cpu_specs[] */ 448 if (!cur_cpu_spec->oprofile_cpu_type || 449 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9")) 450 return -ENODEV; 451 452 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 453 /* 454 * Since PM_INST_CMPL may not provide right counts in all 455 * sampling scenarios in power9 DD1, instead use PM_INST_DISP. 456 */ 457 EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP; 458 /* 459 * Power9 DD1 should use PM_BR_CMPL_ALT event code for 460 * "branches" to provide correct counter value. 461 */ 462 EVENT_VAR(PM_BRU_CMPL, _g).id = PM_BR_CMPL_ALT; 463 EVENT_VAR(PM_BRU_CMPL, _c).id = PM_BR_CMPL_ALT; 464 rc = register_power_pmu(&power9_isa207_pmu); 465 } else { 466 rc = register_power_pmu(&power9_pmu); 467 } 468 469 if (rc) 470 return rc; 471 472 /* Tell userspace that EBB is supported */ 473 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 474 475 return 0; 476 } 477 early_initcall(init_power9_pmu); 478