1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance counter support for POWER9 processors. 4 * 5 * Copyright 2009 Paul Mackerras, IBM Corporation. 6 * Copyright 2013 Michael Ellerman, IBM Corporation. 7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 8 */ 9 10 #define pr_fmt(fmt) "power9-pmu: " fmt 11 12 #include "isa207-common.h" 13 14 /* 15 * Raw event encoding for Power9: 16 * 17 * 60 56 52 48 44 40 36 32 18 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 19 * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ] 20 * | | | | | 21 * | | *- IFM (Linux) | thresh start/stop -* 22 * | *- BHRB (Linux) *sm 23 * *- EBB (Linux) 24 * 25 * 28 24 20 16 12 8 4 0 26 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 27 * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ] 28 * | | | | | 29 * | | | | *- mark 30 * | | *- L1/L2/L3 cache_sel | 31 * | | | 32 * | *- sampling mode for marked events *- combine 33 * | 34 * *- thresh_sel 35 * 36 * Below uses IBM bit numbering. 37 * 38 * MMCR1[x:y] = unit (PMCxUNIT) 39 * MMCR1[24] = pmc1combine[0] 40 * MMCR1[25] = pmc1combine[1] 41 * MMCR1[26] = pmc2combine[0] 42 * MMCR1[27] = pmc2combine[1] 43 * MMCR1[28] = pmc3combine[0] 44 * MMCR1[29] = pmc3combine[1] 45 * MMCR1[30] = pmc4combine[0] 46 * MMCR1[31] = pmc4combine[1] 47 * 48 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 49 * MMCR1[20:27] = thresh_ctl 50 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 51 * MMCR1[20:27] = thresh_ctl 52 * else 53 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 54 * 55 * if thresh_sel: 56 * MMCRA[45:47] = thresh_sel 57 * 58 * if thresh_cmp: 59 * MMCRA[9:11] = thresh_cmp[0:2] 60 * MMCRA[12:18] = thresh_cmp[3:9] 61 * 62 * MMCR1[16] = cache_sel[2] 63 * MMCR1[17] = cache_sel[3] 64 * 65 * if mark: 66 * MMCRA[63] = 1 (SAMPLE_ENABLE) 67 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 68 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 69 * 70 * if EBB and BHRB: 71 * MMCRA[32:33] = IFM 72 * 73 * MMCRA[SDAR_MODE] = sm 74 */ 75 76 /* 77 * Some power9 event codes. 78 */ 79 #define EVENT(_name, _code) _name = _code, 80 81 enum { 82 #include "power9-events-list.h" 83 }; 84 85 #undef EVENT 86 87 /* MMCRA IFM bits - POWER9 */ 88 #define POWER9_MMCRA_IFM1 0x0000000040000000UL 89 #define POWER9_MMCRA_IFM2 0x0000000080000000UL 90 #define POWER9_MMCRA_IFM3 0x00000000C0000000UL 91 #define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL 92 93 /* Nasty Power9 specific hack */ 94 #define PVR_POWER9_CUMULUS 0x00002000 95 96 /* PowerISA v2.07 format attribute structure*/ 97 extern struct attribute_group isa207_pmu_format_group; 98 99 int p9_dd21_bl_ev[] = { 100 PM_MRK_ST_DONE_L2, 101 PM_RADIX_PWC_L1_HIT, 102 PM_FLOP_CMPL, 103 PM_MRK_NTF_FIN, 104 PM_RADIX_PWC_L2_HIT, 105 PM_IFETCH_THROTTLE, 106 PM_MRK_L2_TM_ST_ABORT_SISTER, 107 PM_RADIX_PWC_L3_HIT, 108 PM_RUN_CYC_SMT2_MODE, 109 PM_TM_TX_PASS_RUN_INST, 110 PM_DISP_HELD_SYNC_HOLD, 111 }; 112 113 int p9_dd22_bl_ev[] = { 114 PM_DTLB_MISS_16G, 115 PM_DERAT_MISS_2M, 116 PM_DTLB_MISS_2M, 117 PM_MRK_DTLB_MISS_1G, 118 PM_DTLB_MISS_4K, 119 PM_DERAT_MISS_1G, 120 PM_MRK_DERAT_MISS_2M, 121 PM_MRK_DTLB_MISS_4K, 122 PM_MRK_DTLB_MISS_16G, 123 PM_DTLB_MISS_64K, 124 PM_MRK_DERAT_MISS_1G, 125 PM_MRK_DTLB_MISS_64K, 126 PM_DISP_HELD_SYNC_HOLD, 127 PM_DTLB_MISS_16M, 128 PM_DTLB_MISS_1G, 129 PM_MRK_DTLB_MISS_16M, 130 }; 131 132 /* Table of alternatives, sorted by column 0 */ 133 static const unsigned int power9_event_alternatives[][MAX_ALT] = { 134 { PM_INST_DISP, PM_INST_DISP_ALT }, 135 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 136 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 137 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT }, 138 { PM_BR_2PATH, PM_BR_2PATH_ALT }, 139 }; 140 141 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 142 { 143 int num_alt = 0; 144 145 num_alt = isa207_get_alternatives(event, alt, 146 ARRAY_SIZE(power9_event_alternatives), flags, 147 power9_event_alternatives); 148 149 return num_alt; 150 } 151 152 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 153 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC); 154 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 155 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 156 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 157 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 158 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 159 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN); 160 GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS); 161 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES); 162 163 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN); 164 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 165 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 166 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 167 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 168 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 169 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 170 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 171 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 172 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 173 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 174 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 175 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 176 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 177 178 static struct attribute *power9_events_attr[] = { 179 GENERIC_EVENT_PTR(PM_CYC), 180 GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC), 181 GENERIC_EVENT_PTR(PM_CMPLU_STALL), 182 GENERIC_EVENT_PTR(PM_INST_CMPL), 183 GENERIC_EVENT_PTR(PM_BR_CMPL), 184 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 185 GENERIC_EVENT_PTR(PM_LD_REF_L1), 186 GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN), 187 GENERIC_EVENT_PTR(MEM_LOADS), 188 GENERIC_EVENT_PTR(MEM_STORES), 189 CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN), 190 CACHE_EVENT_PTR(PM_LD_REF_L1), 191 CACHE_EVENT_PTR(PM_L1_PREF), 192 CACHE_EVENT_PTR(PM_ST_MISS_L1), 193 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 194 CACHE_EVENT_PTR(PM_INST_FROM_L1), 195 CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 196 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 197 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 198 CACHE_EVENT_PTR(PM_L3_PREF_ALL), 199 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 200 CACHE_EVENT_PTR(PM_BR_CMPL), 201 CACHE_EVENT_PTR(PM_DTLB_MISS), 202 CACHE_EVENT_PTR(PM_ITLB_MISS), 203 NULL 204 }; 205 206 static struct attribute_group power9_pmu_events_group = { 207 .name = "events", 208 .attrs = power9_events_attr, 209 }; 210 211 PMU_FORMAT_ATTR(event, "config:0-51"); 212 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 213 PMU_FORMAT_ATTR(mark, "config:8"); 214 PMU_FORMAT_ATTR(combine, "config:10-11"); 215 PMU_FORMAT_ATTR(unit, "config:12-15"); 216 PMU_FORMAT_ATTR(pmc, "config:16-19"); 217 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 218 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 219 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 220 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 221 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 222 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 223 PMU_FORMAT_ATTR(sdar_mode, "config:50-51"); 224 225 static struct attribute *power9_pmu_format_attr[] = { 226 &format_attr_event.attr, 227 &format_attr_pmcxsel.attr, 228 &format_attr_mark.attr, 229 &format_attr_combine.attr, 230 &format_attr_unit.attr, 231 &format_attr_pmc.attr, 232 &format_attr_cache_sel.attr, 233 &format_attr_sample_mode.attr, 234 &format_attr_thresh_sel.attr, 235 &format_attr_thresh_stop.attr, 236 &format_attr_thresh_start.attr, 237 &format_attr_thresh_cmp.attr, 238 &format_attr_sdar_mode.attr, 239 NULL, 240 }; 241 242 static struct attribute_group power9_pmu_format_group = { 243 .name = "format", 244 .attrs = power9_pmu_format_attr, 245 }; 246 247 static const struct attribute_group *power9_pmu_attr_groups[] = { 248 &power9_pmu_format_group, 249 &power9_pmu_events_group, 250 NULL, 251 }; 252 253 static int power9_generic_events[] = { 254 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 255 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 256 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 257 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 258 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 259 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 260 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 261 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN, 262 }; 263 264 static u64 power9_bhrb_filter_map(u64 branch_sample_type) 265 { 266 u64 pmu_bhrb_filter = 0; 267 268 /* BHRB and regular PMU events share the same privilege state 269 * filter configuration. BHRB is always recorded along with a 270 * regular PMU event. As the privilege state filter is handled 271 * in the basic PMC configuration of the accompanying regular 272 * PMU event, we ignore any separate BHRB specific request. 273 */ 274 275 /* No branch filter requested */ 276 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 277 return pmu_bhrb_filter; 278 279 /* Invalid branch filter options - HW does not support */ 280 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 281 return -1; 282 283 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 284 return -1; 285 286 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 287 return -1; 288 289 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 290 pmu_bhrb_filter |= POWER9_MMCRA_IFM1; 291 return pmu_bhrb_filter; 292 } 293 294 /* Every thing else is unsupported */ 295 return -1; 296 } 297 298 static void power9_config_bhrb(u64 pmu_bhrb_filter) 299 { 300 pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK; 301 302 /* Enable BHRB filter in PMU */ 303 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 304 } 305 306 #define C(x) PERF_COUNT_HW_CACHE_##x 307 308 /* 309 * Table of generalized cache-related events. 310 * 0 means not supported, -1 means nonsensical, other values 311 * are event codes. 312 */ 313 static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 314 [ C(L1D) ] = { 315 [ C(OP_READ) ] = { 316 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 317 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN, 318 }, 319 [ C(OP_WRITE) ] = { 320 [ C(RESULT_ACCESS) ] = 0, 321 [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 322 }, 323 [ C(OP_PREFETCH) ] = { 324 [ C(RESULT_ACCESS) ] = PM_L1_PREF, 325 [ C(RESULT_MISS) ] = 0, 326 }, 327 }, 328 [ C(L1I) ] = { 329 [ C(OP_READ) ] = { 330 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 331 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 332 }, 333 [ C(OP_WRITE) ] = { 334 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 335 [ C(RESULT_MISS) ] = -1, 336 }, 337 [ C(OP_PREFETCH) ] = { 338 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 339 [ C(RESULT_MISS) ] = 0, 340 }, 341 }, 342 [ C(LL) ] = { 343 [ C(OP_READ) ] = { 344 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 345 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 346 }, 347 [ C(OP_WRITE) ] = { 348 [ C(RESULT_ACCESS) ] = 0, 349 [ C(RESULT_MISS) ] = 0, 350 }, 351 [ C(OP_PREFETCH) ] = { 352 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 353 [ C(RESULT_MISS) ] = 0, 354 }, 355 }, 356 [ C(DTLB) ] = { 357 [ C(OP_READ) ] = { 358 [ C(RESULT_ACCESS) ] = 0, 359 [ C(RESULT_MISS) ] = PM_DTLB_MISS, 360 }, 361 [ C(OP_WRITE) ] = { 362 [ C(RESULT_ACCESS) ] = -1, 363 [ C(RESULT_MISS) ] = -1, 364 }, 365 [ C(OP_PREFETCH) ] = { 366 [ C(RESULT_ACCESS) ] = -1, 367 [ C(RESULT_MISS) ] = -1, 368 }, 369 }, 370 [ C(ITLB) ] = { 371 [ C(OP_READ) ] = { 372 [ C(RESULT_ACCESS) ] = 0, 373 [ C(RESULT_MISS) ] = PM_ITLB_MISS, 374 }, 375 [ C(OP_WRITE) ] = { 376 [ C(RESULT_ACCESS) ] = -1, 377 [ C(RESULT_MISS) ] = -1, 378 }, 379 [ C(OP_PREFETCH) ] = { 380 [ C(RESULT_ACCESS) ] = -1, 381 [ C(RESULT_MISS) ] = -1, 382 }, 383 }, 384 [ C(BPU) ] = { 385 [ C(OP_READ) ] = { 386 [ C(RESULT_ACCESS) ] = PM_BR_CMPL, 387 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 388 }, 389 [ C(OP_WRITE) ] = { 390 [ C(RESULT_ACCESS) ] = -1, 391 [ C(RESULT_MISS) ] = -1, 392 }, 393 [ C(OP_PREFETCH) ] = { 394 [ C(RESULT_ACCESS) ] = -1, 395 [ C(RESULT_MISS) ] = -1, 396 }, 397 }, 398 [ C(NODE) ] = { 399 [ C(OP_READ) ] = { 400 [ C(RESULT_ACCESS) ] = -1, 401 [ C(RESULT_MISS) ] = -1, 402 }, 403 [ C(OP_WRITE) ] = { 404 [ C(RESULT_ACCESS) ] = -1, 405 [ C(RESULT_MISS) ] = -1, 406 }, 407 [ C(OP_PREFETCH) ] = { 408 [ C(RESULT_ACCESS) ] = -1, 409 [ C(RESULT_MISS) ] = -1, 410 }, 411 }, 412 }; 413 414 #undef C 415 416 static struct power_pmu power9_pmu = { 417 .name = "POWER9", 418 .n_counter = MAX_PMU_COUNTERS, 419 .add_fields = ISA207_ADD_FIELDS, 420 .test_adder = ISA207_TEST_ADDER, 421 .group_constraint_mask = CNST_CACHE_PMC4_MASK, 422 .group_constraint_val = CNST_CACHE_PMC4_VAL, 423 .compute_mmcr = isa207_compute_mmcr, 424 .config_bhrb = power9_config_bhrb, 425 .bhrb_filter_map = power9_bhrb_filter_map, 426 .get_constraint = isa207_get_constraint, 427 .get_alternatives = power9_get_alternatives, 428 .get_mem_data_src = isa207_get_mem_data_src, 429 .get_mem_weight = isa207_get_mem_weight, 430 .disable_pmc = isa207_disable_pmc, 431 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 432 .n_generic = ARRAY_SIZE(power9_generic_events), 433 .generic_events = power9_generic_events, 434 .cache_events = &power9_cache_events, 435 .attr_groups = power9_pmu_attr_groups, 436 .bhrb_nr = 32, 437 }; 438 439 int init_power9_pmu(void) 440 { 441 int rc = 0; 442 unsigned int pvr = mfspr(SPRN_PVR); 443 444 /* Comes from cpu_specs[] */ 445 if (!cur_cpu_spec->oprofile_cpu_type || 446 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9")) 447 return -ENODEV; 448 449 /* Blacklist events */ 450 if (!(pvr & PVR_POWER9_CUMULUS)) { 451 if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) { 452 power9_pmu.blacklist_ev = p9_dd21_bl_ev; 453 power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev); 454 } else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) { 455 power9_pmu.blacklist_ev = p9_dd22_bl_ev; 456 power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev); 457 } 458 } 459 460 rc = register_power_pmu(&power9_pmu); 461 if (rc) 462 return rc; 463 464 /* Tell userspace that EBB is supported */ 465 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 466 467 return 0; 468 } 469