1 /* 2 * Performance counter support for POWER9 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * Copyright 2013 Michael Ellerman, IBM Corporation. 6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or later version. 12 */ 13 14 #define pr_fmt(fmt) "power9-pmu: " fmt 15 16 #include "isa207-common.h" 17 18 /* 19 * Raw event encoding for Power9: 20 * 21 * 60 56 52 48 44 40 36 32 22 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 23 * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ] 24 * | | | | | 25 * | | *- IFM (Linux) | thresh start/stop -* 26 * | *- BHRB (Linux) *sm 27 * *- EBB (Linux) 28 * 29 * 28 24 20 16 12 8 4 0 30 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 31 * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ] 32 * | | | | | 33 * | | | | *- mark 34 * | | *- L1/L2/L3 cache_sel | 35 * | | | 36 * | *- sampling mode for marked events *- combine 37 * | 38 * *- thresh_sel 39 * 40 * Below uses IBM bit numbering. 41 * 42 * MMCR1[x:y] = unit (PMCxUNIT) 43 * MMCR1[24] = pmc1combine[0] 44 * MMCR1[25] = pmc1combine[1] 45 * MMCR1[26] = pmc2combine[0] 46 * MMCR1[27] = pmc2combine[1] 47 * MMCR1[28] = pmc3combine[0] 48 * MMCR1[29] = pmc3combine[1] 49 * MMCR1[30] = pmc4combine[0] 50 * MMCR1[31] = pmc4combine[1] 51 * 52 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 53 * MMCR1[20:27] = thresh_ctl 54 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 55 * MMCR1[20:27] = thresh_ctl 56 * else 57 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 58 * 59 * if thresh_sel: 60 * MMCRA[45:47] = thresh_sel 61 * 62 * if thresh_cmp: 63 * MMCRA[9:11] = thresh_cmp[0:2] 64 * MMCRA[12:18] = thresh_cmp[3:9] 65 * 66 * if unit == 6 or unit == 7 67 * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) 68 * else if unit == 8 or unit == 9: 69 * if cache_sel[0] == 0: # L3 bank 70 * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) 71 * else if cache_sel[0] == 1: 72 * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) 73 * else if cache_sel[1]: # L1 event 74 * MMCR1[16] = cache_sel[2] 75 * MMCR1[17] = cache_sel[3] 76 * 77 * if mark: 78 * MMCRA[63] = 1 (SAMPLE_ENABLE) 79 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 80 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 81 * 82 * if EBB and BHRB: 83 * MMCRA[32:33] = IFM 84 * 85 * MMCRA[SDAR_MODE] = sm 86 */ 87 88 /* 89 * Some power9 event codes. 90 */ 91 #define EVENT(_name, _code) _name = _code, 92 93 enum { 94 #include "power9-events-list.h" 95 }; 96 97 #undef EVENT 98 99 /* MMCRA IFM bits - POWER9 */ 100 #define POWER9_MMCRA_IFM1 0x0000000040000000UL 101 #define POWER9_MMCRA_IFM2 0x0000000080000000UL 102 #define POWER9_MMCRA_IFM3 0x00000000C0000000UL 103 104 /* Nasty Power9 specific hack */ 105 #define PVR_POWER9_CUMULUS 0x00002000 106 107 /* PowerISA v2.07 format attribute structure*/ 108 extern struct attribute_group isa207_pmu_format_group; 109 110 int p9_dd21_bl_ev[] = { 111 PM_MRK_ST_DONE_L2, 112 PM_RADIX_PWC_L1_HIT, 113 PM_FLOP_CMPL, 114 PM_MRK_NTF_FIN, 115 PM_RADIX_PWC_L2_HIT, 116 PM_IFETCH_THROTTLE, 117 PM_MRK_L2_TM_ST_ABORT_SISTER, 118 PM_RADIX_PWC_L3_HIT, 119 PM_RUN_CYC_SMT2_MODE, 120 PM_TM_TX_PASS_RUN_INST, 121 PM_DISP_HELD_SYNC_HOLD, 122 }; 123 124 int p9_dd22_bl_ev[] = { 125 PM_DTLB_MISS_16G, 126 PM_DERAT_MISS_2M, 127 PM_DTLB_MISS_2M, 128 PM_MRK_DTLB_MISS_1G, 129 PM_DTLB_MISS_4K, 130 PM_DERAT_MISS_1G, 131 PM_MRK_DERAT_MISS_2M, 132 PM_MRK_DTLB_MISS_4K, 133 PM_MRK_DTLB_MISS_16G, 134 PM_DTLB_MISS_64K, 135 PM_MRK_DERAT_MISS_1G, 136 PM_MRK_DTLB_MISS_64K, 137 PM_DISP_HELD_SYNC_HOLD, 138 PM_DTLB_MISS_16M, 139 PM_DTLB_MISS_1G, 140 PM_MRK_DTLB_MISS_16M, 141 }; 142 143 /* Table of alternatives, sorted by column 0 */ 144 static const unsigned int power9_event_alternatives[][MAX_ALT] = { 145 { PM_INST_DISP, PM_INST_DISP_ALT }, 146 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 147 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 148 { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT }, 149 { PM_BR_2PATH, PM_BR_2PATH_ALT }, 150 }; 151 152 static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 153 { 154 int num_alt = 0; 155 156 num_alt = isa207_get_alternatives(event, alt, 157 ARRAY_SIZE(power9_event_alternatives), flags, 158 power9_event_alternatives); 159 160 return num_alt; 161 } 162 163 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 164 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC); 165 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 166 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 167 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 168 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 169 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 170 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN); 171 172 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN); 173 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 174 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 175 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 176 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 177 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 178 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 179 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 180 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 181 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 182 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 183 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 184 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 185 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 186 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 187 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 188 189 static struct attribute *power9_events_attr[] = { 190 GENERIC_EVENT_PTR(PM_CYC), 191 GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC), 192 GENERIC_EVENT_PTR(PM_CMPLU_STALL), 193 GENERIC_EVENT_PTR(PM_INST_CMPL), 194 GENERIC_EVENT_PTR(PM_BR_CMPL), 195 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 196 GENERIC_EVENT_PTR(PM_LD_REF_L1), 197 GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN), 198 CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN), 199 CACHE_EVENT_PTR(PM_LD_REF_L1), 200 CACHE_EVENT_PTR(PM_L1_PREF), 201 CACHE_EVENT_PTR(PM_ST_MISS_L1), 202 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 203 CACHE_EVENT_PTR(PM_INST_FROM_L1), 204 CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 205 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 206 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 207 CACHE_EVENT_PTR(PM_L3_PREF_ALL), 208 CACHE_EVENT_PTR(PM_L2_ST_MISS), 209 CACHE_EVENT_PTR(PM_L2_ST), 210 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 211 CACHE_EVENT_PTR(PM_BR_CMPL), 212 CACHE_EVENT_PTR(PM_DTLB_MISS), 213 CACHE_EVENT_PTR(PM_ITLB_MISS), 214 NULL 215 }; 216 217 static struct attribute_group power9_pmu_events_group = { 218 .name = "events", 219 .attrs = power9_events_attr, 220 }; 221 222 PMU_FORMAT_ATTR(event, "config:0-51"); 223 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 224 PMU_FORMAT_ATTR(mark, "config:8"); 225 PMU_FORMAT_ATTR(combine, "config:10-11"); 226 PMU_FORMAT_ATTR(unit, "config:12-15"); 227 PMU_FORMAT_ATTR(pmc, "config:16-19"); 228 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 229 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 230 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 231 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 232 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 233 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 234 PMU_FORMAT_ATTR(sdar_mode, "config:50-51"); 235 236 static struct attribute *power9_pmu_format_attr[] = { 237 &format_attr_event.attr, 238 &format_attr_pmcxsel.attr, 239 &format_attr_mark.attr, 240 &format_attr_combine.attr, 241 &format_attr_unit.attr, 242 &format_attr_pmc.attr, 243 &format_attr_cache_sel.attr, 244 &format_attr_sample_mode.attr, 245 &format_attr_thresh_sel.attr, 246 &format_attr_thresh_stop.attr, 247 &format_attr_thresh_start.attr, 248 &format_attr_thresh_cmp.attr, 249 &format_attr_sdar_mode.attr, 250 NULL, 251 }; 252 253 static struct attribute_group power9_pmu_format_group = { 254 .name = "format", 255 .attrs = power9_pmu_format_attr, 256 }; 257 258 static const struct attribute_group *power9_pmu_attr_groups[] = { 259 &power9_pmu_format_group, 260 &power9_pmu_events_group, 261 NULL, 262 }; 263 264 static int power9_generic_events[] = { 265 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 266 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 267 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 268 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 269 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 270 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 271 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 272 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN, 273 }; 274 275 static u64 power9_bhrb_filter_map(u64 branch_sample_type) 276 { 277 u64 pmu_bhrb_filter = 0; 278 279 /* BHRB and regular PMU events share the same privilege state 280 * filter configuration. BHRB is always recorded along with a 281 * regular PMU event. As the privilege state filter is handled 282 * in the basic PMC configuration of the accompanying regular 283 * PMU event, we ignore any separate BHRB specific request. 284 */ 285 286 /* No branch filter requested */ 287 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 288 return pmu_bhrb_filter; 289 290 /* Invalid branch filter options - HW does not support */ 291 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 292 return -1; 293 294 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 295 return -1; 296 297 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 298 return -1; 299 300 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 301 pmu_bhrb_filter |= POWER9_MMCRA_IFM1; 302 return pmu_bhrb_filter; 303 } 304 305 /* Every thing else is unsupported */ 306 return -1; 307 } 308 309 static void power9_config_bhrb(u64 pmu_bhrb_filter) 310 { 311 /* Enable BHRB filter in PMU */ 312 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 313 } 314 315 #define C(x) PERF_COUNT_HW_CACHE_##x 316 317 /* 318 * Table of generalized cache-related events. 319 * 0 means not supported, -1 means nonsensical, other values 320 * are event codes. 321 */ 322 static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 323 [ C(L1D) ] = { 324 [ C(OP_READ) ] = { 325 [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 326 [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN, 327 }, 328 [ C(OP_WRITE) ] = { 329 [ C(RESULT_ACCESS) ] = 0, 330 [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 331 }, 332 [ C(OP_PREFETCH) ] = { 333 [ C(RESULT_ACCESS) ] = PM_L1_PREF, 334 [ C(RESULT_MISS) ] = 0, 335 }, 336 }, 337 [ C(L1I) ] = { 338 [ C(OP_READ) ] = { 339 [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 340 [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 341 }, 342 [ C(OP_WRITE) ] = { 343 [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 344 [ C(RESULT_MISS) ] = -1, 345 }, 346 [ C(OP_PREFETCH) ] = { 347 [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 348 [ C(RESULT_MISS) ] = 0, 349 }, 350 }, 351 [ C(LL) ] = { 352 [ C(OP_READ) ] = { 353 [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 354 [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 355 }, 356 [ C(OP_WRITE) ] = { 357 [ C(RESULT_ACCESS) ] = PM_L2_ST, 358 [ C(RESULT_MISS) ] = PM_L2_ST_MISS, 359 }, 360 [ C(OP_PREFETCH) ] = { 361 [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 362 [ C(RESULT_MISS) ] = 0, 363 }, 364 }, 365 [ C(DTLB) ] = { 366 [ C(OP_READ) ] = { 367 [ C(RESULT_ACCESS) ] = 0, 368 [ C(RESULT_MISS) ] = PM_DTLB_MISS, 369 }, 370 [ C(OP_WRITE) ] = { 371 [ C(RESULT_ACCESS) ] = -1, 372 [ C(RESULT_MISS) ] = -1, 373 }, 374 [ C(OP_PREFETCH) ] = { 375 [ C(RESULT_ACCESS) ] = -1, 376 [ C(RESULT_MISS) ] = -1, 377 }, 378 }, 379 [ C(ITLB) ] = { 380 [ C(OP_READ) ] = { 381 [ C(RESULT_ACCESS) ] = 0, 382 [ C(RESULT_MISS) ] = PM_ITLB_MISS, 383 }, 384 [ C(OP_WRITE) ] = { 385 [ C(RESULT_ACCESS) ] = -1, 386 [ C(RESULT_MISS) ] = -1, 387 }, 388 [ C(OP_PREFETCH) ] = { 389 [ C(RESULT_ACCESS) ] = -1, 390 [ C(RESULT_MISS) ] = -1, 391 }, 392 }, 393 [ C(BPU) ] = { 394 [ C(OP_READ) ] = { 395 [ C(RESULT_ACCESS) ] = PM_BR_CMPL, 396 [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 397 }, 398 [ C(OP_WRITE) ] = { 399 [ C(RESULT_ACCESS) ] = -1, 400 [ C(RESULT_MISS) ] = -1, 401 }, 402 [ C(OP_PREFETCH) ] = { 403 [ C(RESULT_ACCESS) ] = -1, 404 [ C(RESULT_MISS) ] = -1, 405 }, 406 }, 407 [ C(NODE) ] = { 408 [ C(OP_READ) ] = { 409 [ C(RESULT_ACCESS) ] = -1, 410 [ C(RESULT_MISS) ] = -1, 411 }, 412 [ C(OP_WRITE) ] = { 413 [ C(RESULT_ACCESS) ] = -1, 414 [ C(RESULT_MISS) ] = -1, 415 }, 416 [ C(OP_PREFETCH) ] = { 417 [ C(RESULT_ACCESS) ] = -1, 418 [ C(RESULT_MISS) ] = -1, 419 }, 420 }, 421 }; 422 423 #undef C 424 425 static struct power_pmu power9_pmu = { 426 .name = "POWER9", 427 .n_counter = MAX_PMU_COUNTERS, 428 .add_fields = ISA207_ADD_FIELDS, 429 .test_adder = ISA207_TEST_ADDER, 430 .compute_mmcr = isa207_compute_mmcr, 431 .config_bhrb = power9_config_bhrb, 432 .bhrb_filter_map = power9_bhrb_filter_map, 433 .get_constraint = isa207_get_constraint, 434 .get_alternatives = power9_get_alternatives, 435 .get_mem_data_src = isa207_get_mem_data_src, 436 .get_mem_weight = isa207_get_mem_weight, 437 .disable_pmc = isa207_disable_pmc, 438 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 439 .n_generic = ARRAY_SIZE(power9_generic_events), 440 .generic_events = power9_generic_events, 441 .cache_events = &power9_cache_events, 442 .attr_groups = power9_pmu_attr_groups, 443 .bhrb_nr = 32, 444 }; 445 446 static int __init init_power9_pmu(void) 447 { 448 int rc = 0; 449 unsigned int pvr = mfspr(SPRN_PVR); 450 451 /* Comes from cpu_specs[] */ 452 if (!cur_cpu_spec->oprofile_cpu_type || 453 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9")) 454 return -ENODEV; 455 456 /* Blacklist events */ 457 if (!(pvr & PVR_POWER9_CUMULUS)) { 458 if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) { 459 power9_pmu.blacklist_ev = p9_dd21_bl_ev; 460 power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev); 461 } else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) { 462 power9_pmu.blacklist_ev = p9_dd22_bl_ev; 463 power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev); 464 } 465 } 466 467 rc = register_power_pmu(&power9_pmu); 468 if (rc) 469 return rc; 470 471 /* Tell userspace that EBB is supported */ 472 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 473 474 return 0; 475 } 476 early_initcall(init_power9_pmu); 477