1 /* 2 * Performance counter support for POWER9 processors. 3 * 4 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 /* 13 * Power9 event codes. 14 */ 15 EVENT(PM_CYC, 0x0001e) 16 EVENT(PM_ICT_NOSLOT_CYC, 0x100f8) 17 EVENT(PM_CMPLU_STALL, 0x1e054) 18 EVENT(PM_INST_CMPL, 0x00002) 19 EVENT(PM_BR_CMPL, 0x4d05e) 20 EVENT(PM_BR_MPRED_CMPL, 0x400f6) 21 22 /* All L1 D cache load references counted at finish, gated by reject */ 23 EVENT(PM_LD_REF_L1, 0x100fc) 24 /* Load Missed L1 */ 25 EVENT(PM_LD_MISS_L1_FIN, 0x2c04e) 26 EVENT(PM_LD_MISS_L1, 0x3e054) 27 /* Alternate event code for PM_LD_MISS_L1 */ 28 EVENT(PM_LD_MISS_L1_ALT, 0x400f0) 29 /* Store Missed L1 */ 30 EVENT(PM_ST_MISS_L1, 0x300f0) 31 /* L1 cache data prefetches */ 32 EVENT(PM_L1_PREF, 0x20054) 33 /* Instruction fetches from L1 */ 34 EVENT(PM_INST_FROM_L1, 0x04080) 35 /* Demand iCache Miss */ 36 EVENT(PM_L1_ICACHE_MISS, 0x200fd) 37 /* Instruction Demand sectors wriittent into IL1 */ 38 EVENT(PM_L1_DEMAND_WRITE, 0x0408c) 39 /* Instruction prefetch written into IL1 */ 40 EVENT(PM_IC_PREF_WRITE, 0x0488c) 41 /* The data cache was reloaded from local core's L3 due to a demand load */ 42 EVENT(PM_DATA_FROM_L3, 0x4c042) 43 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */ 44 EVENT(PM_DATA_FROM_L3MISS, 0x300fe) 45 /* All successful D-side store dispatches for this thread */ 46 EVENT(PM_L2_ST, 0x16880) 47 /* All successful D-side store dispatches for this thread that were L2 Miss */ 48 EVENT(PM_L2_ST_MISS, 0x26880) 49 /* Total HW L3 prefetches(Load+store) */ 50 EVENT(PM_L3_PREF_ALL, 0x4e052) 51 /* Data PTEG reload */ 52 EVENT(PM_DTLB_MISS, 0x300fc) 53 /* ITLB Reloaded */ 54 EVENT(PM_ITLB_MISS, 0x400fc) 55 /* Run_Instructions */ 56 EVENT(PM_RUN_INST_CMPL, 0x500fa) 57 /* Alternate event code for PM_RUN_INST_CMPL */ 58 EVENT(PM_RUN_INST_CMPL_ALT, 0x400fa) 59 /* Run_cycles */ 60 EVENT(PM_RUN_CYC, 0x600f4) 61 /* Alternate event code for Run_cycles */ 62 EVENT(PM_RUN_CYC_ALT, 0x200f4) 63 /* Instruction Dispatched */ 64 EVENT(PM_INST_DISP, 0x200f2) 65 EVENT(PM_INST_DISP_ALT, 0x300f2) 66 /* Alternate Branch event code */ 67 EVENT(PM_BR_CMPL_ALT, 0x10012) 68 /* Branch event that are not strongly biased */ 69 EVENT(PM_BR_2PATH, 0x20036) 70 /* ALternate branch event that are not strongly biased */ 71 EVENT(PM_BR_2PATH_ALT, 0x40036) 72 73 /* Blacklisted events */ 74 EVENT(PM_MRK_ST_DONE_L2, 0x10134) 75 EVENT(PM_RADIX_PWC_L1_HIT, 0x1f056) 76 EVENT(PM_FLOP_CMPL, 0x100f4) 77 EVENT(PM_MRK_NTF_FIN, 0x20112) 78 EVENT(PM_RADIX_PWC_L2_HIT, 0x2d024) 79 EVENT(PM_IFETCH_THROTTLE, 0x3405e) 80 EVENT(PM_MRK_L2_TM_ST_ABORT_SISTER, 0x3e15c) 81 EVENT(PM_RADIX_PWC_L3_HIT, 0x3f056) 82 EVENT(PM_RUN_CYC_SMT2_MODE, 0x3006c) 83 EVENT(PM_TM_TX_PASS_RUN_INST, 0x4e014) 84 EVENT(PM_DISP_HELD_SYNC_HOLD, 0x4003c) 85 EVENT(PM_DTLB_MISS_16G, 0x1c058) 86 EVENT(PM_DERAT_MISS_2M, 0x1c05a) 87 EVENT(PM_DTLB_MISS_2M, 0x1c05c) 88 EVENT(PM_MRK_DTLB_MISS_1G, 0x1d15c) 89 EVENT(PM_DTLB_MISS_4K, 0x2c056) 90 EVENT(PM_DERAT_MISS_1G, 0x2c05a) 91 EVENT(PM_MRK_DERAT_MISS_2M, 0x2d152) 92 EVENT(PM_MRK_DTLB_MISS_4K, 0x2d156) 93 EVENT(PM_MRK_DTLB_MISS_16G, 0x2d15e) 94 EVENT(PM_DTLB_MISS_64K, 0x3c056) 95 EVENT(PM_MRK_DERAT_MISS_1G, 0x3d152) 96 EVENT(PM_MRK_DTLB_MISS_64K, 0x3d156) 97 EVENT(PM_DTLB_MISS_16M, 0x4c056) 98 EVENT(PM_DTLB_MISS_1G, 0x4c05a) 99 EVENT(PM_MRK_DTLB_MISS_16M, 0x4c15e) 100 101 /* 102 * Memory Access Events 103 * 104 * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0) 105 * To enable capturing of memory profiling, these MMCRA bits 106 * needs to be programmed and corresponding raw event format 107 * encoding. 108 * 109 * MMCRA bits encoding needed are 110 * SM (Sampling Mode) 111 * EM (Eligibility for Random Sampling) 112 * TECE (Threshold Event Counter Event) 113 * TS (Threshold Start Event) 114 * TE (Threshold End Event) 115 * 116 * Corresponding Raw Encoding bits: 117 * sample [EM,SM] 118 * thresh_sel (TECE) 119 * thresh start (TS) 120 * thresh end (TE) 121 */ 122 EVENT(MEM_LOADS, 0x34340401e0) 123 EVENT(MEM_STORES, 0x343c0401e0) 124