1e05b9b9eSMichael Ellerman /* 2e05b9b9eSMichael Ellerman * Performance counter support for POWER8 processors. 3e05b9b9eSMichael Ellerman * 4e05b9b9eSMichael Ellerman * Copyright 2009 Paul Mackerras, IBM Corporation. 5e05b9b9eSMichael Ellerman * Copyright 2013 Michael Ellerman, IBM Corporation. 6e05b9b9eSMichael Ellerman * 7e05b9b9eSMichael Ellerman * This program is free software; you can redistribute it and/or 8e05b9b9eSMichael Ellerman * modify it under the terms of the GNU General Public License 9e05b9b9eSMichael Ellerman * as published by the Free Software Foundation; either version 10e05b9b9eSMichael Ellerman * 2 of the License, or (at your option) any later version. 11e05b9b9eSMichael Ellerman */ 12e05b9b9eSMichael Ellerman 13c2e37a26SMichael Ellerman #define pr_fmt(fmt) "power8-pmu: " fmt 14c2e37a26SMichael Ellerman 154d3576b2SMadhavan Srinivasan #include "isa207-common.h" 16e05b9b9eSMichael Ellerman 17e05b9b9eSMichael Ellerman /* 18e05b9b9eSMichael Ellerman * Some power8 event codes. 19e05b9b9eSMichael Ellerman */ 20e0728b50SSukadev Bhattiprolu #define EVENT(_name, _code) _name = _code, 21e05b9b9eSMichael Ellerman 22e0728b50SSukadev Bhattiprolu enum { 23e0728b50SSukadev Bhattiprolu #include "power8-events-list.h" 24e0728b50SSukadev Bhattiprolu }; 252fdd313fSMichael Ellerman 26e0728b50SSukadev Bhattiprolu #undef EVENT 27e05b9b9eSMichael Ellerman 28b1113557SAnshuman Khandual /* MMCRA IFM bits - POWER8 */ 29b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM1 0x0000000040000000UL 30b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM2 0x0000000080000000UL 31b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM3 0x00000000C0000000UL 32b1113557SAnshuman Khandual 33e05b9b9eSMichael Ellerman /* Table of alternatives, sorted by column 0 */ 34e05b9b9eSMichael Ellerman static const unsigned int event_alternatives[][MAX_ALT] = { 355bcca743SMadhavan Srinivasan { PM_MRK_ST_CMPL, PM_MRK_ST_CMPL_ALT }, 365bcca743SMadhavan Srinivasan { PM_BR_MRK_2PATH, PM_BR_MRK_2PATH_ALT }, 375bcca743SMadhavan Srinivasan { PM_L3_CO_MEPF, PM_L3_CO_MEPF_ALT }, 385bcca743SMadhavan Srinivasan { PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L2MISS_ALT }, 395bcca743SMadhavan Srinivasan { PM_CMPLU_STALL_ALT, PM_CMPLU_STALL }, 405bcca743SMadhavan Srinivasan { PM_BR_2PATH, PM_BR_2PATH_ALT }, 415bcca743SMadhavan Srinivasan { PM_INST_DISP, PM_INST_DISP_ALT }, 425bcca743SMadhavan Srinivasan { PM_RUN_CYC_ALT, PM_RUN_CYC }, 435bcca743SMadhavan Srinivasan { PM_MRK_FILT_MATCH, PM_MRK_FILT_MATCH_ALT }, 445bcca743SMadhavan Srinivasan { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT }, 455bcca743SMadhavan Srinivasan { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 46e05b9b9eSMichael Ellerman }; 47e05b9b9eSMichael Ellerman 48e05b9b9eSMichael Ellerman /* 49e05b9b9eSMichael Ellerman * Scan the alternatives table for a match and return the 50e05b9b9eSMichael Ellerman * index into the alternatives table if found, else -1. 51e05b9b9eSMichael Ellerman */ 52e05b9b9eSMichael Ellerman static int find_alternative(u64 event) 53e05b9b9eSMichael Ellerman { 54e05b9b9eSMichael Ellerman int i, j; 55e05b9b9eSMichael Ellerman 56e05b9b9eSMichael Ellerman for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { 57e05b9b9eSMichael Ellerman if (event < event_alternatives[i][0]) 58e05b9b9eSMichael Ellerman break; 59e05b9b9eSMichael Ellerman 60e05b9b9eSMichael Ellerman for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) 61e05b9b9eSMichael Ellerman if (event == event_alternatives[i][j]) 62e05b9b9eSMichael Ellerman return i; 63e05b9b9eSMichael Ellerman } 64e05b9b9eSMichael Ellerman 65e05b9b9eSMichael Ellerman return -1; 66e05b9b9eSMichael Ellerman } 67e05b9b9eSMichael Ellerman 68e05b9b9eSMichael Ellerman static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 69e05b9b9eSMichael Ellerman { 70e05b9b9eSMichael Ellerman int i, j, num_alt = 0; 71e05b9b9eSMichael Ellerman u64 alt_event; 72e05b9b9eSMichael Ellerman 73e05b9b9eSMichael Ellerman alt[num_alt++] = event; 74e05b9b9eSMichael Ellerman 75e05b9b9eSMichael Ellerman i = find_alternative(event); 76e05b9b9eSMichael Ellerman if (i >= 0) { 77e05b9b9eSMichael Ellerman /* Filter out the original event, it's already in alt[0] */ 78e05b9b9eSMichael Ellerman for (j = 0; j < MAX_ALT; ++j) { 79e05b9b9eSMichael Ellerman alt_event = event_alternatives[i][j]; 80e05b9b9eSMichael Ellerman if (alt_event && alt_event != event) 81e05b9b9eSMichael Ellerman alt[num_alt++] = alt_event; 82e05b9b9eSMichael Ellerman } 83e05b9b9eSMichael Ellerman } 84e05b9b9eSMichael Ellerman 85e05b9b9eSMichael Ellerman if (flags & PPMU_ONLY_COUNT_RUN) { 86e05b9b9eSMichael Ellerman /* 87e05b9b9eSMichael Ellerman * We're only counting in RUN state, so PM_CYC is equivalent to 88e05b9b9eSMichael Ellerman * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. 89e05b9b9eSMichael Ellerman */ 90e05b9b9eSMichael Ellerman j = num_alt; 91e05b9b9eSMichael Ellerman for (i = 0; i < num_alt; ++i) { 92e05b9b9eSMichael Ellerman switch (alt[i]) { 935bcca743SMadhavan Srinivasan case PM_CYC: 945bcca743SMadhavan Srinivasan alt[j++] = PM_RUN_CYC; 95e05b9b9eSMichael Ellerman break; 965bcca743SMadhavan Srinivasan case PM_RUN_CYC: 975bcca743SMadhavan Srinivasan alt[j++] = PM_CYC; 98e05b9b9eSMichael Ellerman break; 995bcca743SMadhavan Srinivasan case PM_INST_CMPL: 1005bcca743SMadhavan Srinivasan alt[j++] = PM_RUN_INST_CMPL; 101e05b9b9eSMichael Ellerman break; 1025bcca743SMadhavan Srinivasan case PM_RUN_INST_CMPL: 1035bcca743SMadhavan Srinivasan alt[j++] = PM_INST_CMPL; 104e05b9b9eSMichael Ellerman break; 105e05b9b9eSMichael Ellerman } 106e05b9b9eSMichael Ellerman } 107e05b9b9eSMichael Ellerman num_alt = j; 108e05b9b9eSMichael Ellerman } 109e05b9b9eSMichael Ellerman 110e05b9b9eSMichael Ellerman return num_alt; 111e05b9b9eSMichael Ellerman } 112e05b9b9eSMichael Ellerman 113e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 114e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC); 115e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 116e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 117e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN); 118e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 119e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 120e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); 121e0728b50SSukadev Bhattiprolu 122e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 123e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 124e0728b50SSukadev Bhattiprolu 125e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 126e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 127e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 128e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 129e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 130e0728b50SSukadev Bhattiprolu 131e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 132e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 133e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 134e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 135e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 136e0728b50SSukadev Bhattiprolu 137e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 138e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN); 139e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 140e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 141e0728b50SSukadev Bhattiprolu 142e0728b50SSukadev Bhattiprolu static struct attribute *power8_events_attr[] = { 143e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_CYC), 144e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC), 145e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_CMPLU_STALL), 146e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_INST_CMPL), 147e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_BRU_FIN), 148e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 149e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_LD_REF_L1), 150e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_LD_MISS_L1), 151e0728b50SSukadev Bhattiprolu 152e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_LD_MISS_L1), 153e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_LD_REF_L1), 154e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L1_PREF), 155e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_ST_MISS_L1), 156e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 157e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_INST_FROM_L1), 158e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 159e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 160e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DATA_FROM_L3), 161e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L3_PREF_ALL), 162e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L2_ST_MISS), 163e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L2_ST), 164e0728b50SSukadev Bhattiprolu 165e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 166e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_BRU_FIN), 167e0728b50SSukadev Bhattiprolu 168e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DTLB_MISS), 169e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_ITLB_MISS), 170e0728b50SSukadev Bhattiprolu NULL 171e0728b50SSukadev Bhattiprolu }; 172e0728b50SSukadev Bhattiprolu 173e0728b50SSukadev Bhattiprolu static struct attribute_group power8_pmu_events_group = { 174e0728b50SSukadev Bhattiprolu .name = "events", 175e0728b50SSukadev Bhattiprolu .attrs = power8_events_attr, 176e0728b50SSukadev Bhattiprolu }; 177e0728b50SSukadev Bhattiprolu 178e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(event, "config:0-49"); 179e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 180e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(mark, "config:8"); 181e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(combine, "config:11"); 182e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(unit, "config:12-15"); 183e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(pmc, "config:16-19"); 184e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 185e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 186e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 187e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 188e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 189e05b9b9eSMichael Ellerman PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 190e05b9b9eSMichael Ellerman 191e05b9b9eSMichael Ellerman static struct attribute *power8_pmu_format_attr[] = { 192e05b9b9eSMichael Ellerman &format_attr_event.attr, 193e05b9b9eSMichael Ellerman &format_attr_pmcxsel.attr, 194e05b9b9eSMichael Ellerman &format_attr_mark.attr, 195e05b9b9eSMichael Ellerman &format_attr_combine.attr, 196e05b9b9eSMichael Ellerman &format_attr_unit.attr, 197e05b9b9eSMichael Ellerman &format_attr_pmc.attr, 198e05b9b9eSMichael Ellerman &format_attr_cache_sel.attr, 199e05b9b9eSMichael Ellerman &format_attr_sample_mode.attr, 200e05b9b9eSMichael Ellerman &format_attr_thresh_sel.attr, 201e05b9b9eSMichael Ellerman &format_attr_thresh_stop.attr, 202e05b9b9eSMichael Ellerman &format_attr_thresh_start.attr, 203e05b9b9eSMichael Ellerman &format_attr_thresh_cmp.attr, 204e05b9b9eSMichael Ellerman NULL, 205e05b9b9eSMichael Ellerman }; 206e05b9b9eSMichael Ellerman 207e05b9b9eSMichael Ellerman struct attribute_group power8_pmu_format_group = { 208e05b9b9eSMichael Ellerman .name = "format", 209e05b9b9eSMichael Ellerman .attrs = power8_pmu_format_attr, 210e05b9b9eSMichael Ellerman }; 211e05b9b9eSMichael Ellerman 212e05b9b9eSMichael Ellerman static const struct attribute_group *power8_pmu_attr_groups[] = { 213e05b9b9eSMichael Ellerman &power8_pmu_format_group, 214e0728b50SSukadev Bhattiprolu &power8_pmu_events_group, 215e05b9b9eSMichael Ellerman NULL, 216e05b9b9eSMichael Ellerman }; 217e05b9b9eSMichael Ellerman 218e05b9b9eSMichael Ellerman static int power8_generic_events[] = { 219e05b9b9eSMichael Ellerman [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 220e05b9b9eSMichael Ellerman [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC, 221e05b9b9eSMichael Ellerman [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 222e05b9b9eSMichael Ellerman [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 223e05b9b9eSMichael Ellerman [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN, 224e05b9b9eSMichael Ellerman [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 2252fdd313fSMichael Ellerman [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 2262fdd313fSMichael Ellerman [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 227e05b9b9eSMichael Ellerman }; 228e05b9b9eSMichael Ellerman 229b1113557SAnshuman Khandual static u64 power8_bhrb_filter_map(u64 branch_sample_type) 230b1113557SAnshuman Khandual { 231b1113557SAnshuman Khandual u64 pmu_bhrb_filter = 0; 232b1113557SAnshuman Khandual 2337689bdcaSAnshuman Khandual /* BHRB and regular PMU events share the same privilege state 234b1113557SAnshuman Khandual * filter configuration. BHRB is always recorded along with a 2357689bdcaSAnshuman Khandual * regular PMU event. As the privilege state filter is handled 2367689bdcaSAnshuman Khandual * in the basic PMC configuration of the accompanying regular 2377689bdcaSAnshuman Khandual * PMU event, we ignore any separate BHRB specific request. 238b1113557SAnshuman Khandual */ 239b1113557SAnshuman Khandual 240b1113557SAnshuman Khandual /* No branch filter requested */ 241b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 242b1113557SAnshuman Khandual return pmu_bhrb_filter; 243b1113557SAnshuman Khandual 244b1113557SAnshuman Khandual /* Invalid branch filter options - HW does not support */ 245b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 246b1113557SAnshuman Khandual return -1; 247b1113557SAnshuman Khandual 248b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 249b1113557SAnshuman Khandual return -1; 250b1113557SAnshuman Khandual 25124f1a79aSStephane Eranian if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 25224f1a79aSStephane Eranian return -1; 25324f1a79aSStephane Eranian 254b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 255b1113557SAnshuman Khandual pmu_bhrb_filter |= POWER8_MMCRA_IFM1; 256b1113557SAnshuman Khandual return pmu_bhrb_filter; 257b1113557SAnshuman Khandual } 258b1113557SAnshuman Khandual 259b1113557SAnshuman Khandual /* Every thing else is unsupported */ 260b1113557SAnshuman Khandual return -1; 261b1113557SAnshuman Khandual } 262b1113557SAnshuman Khandual 263b1113557SAnshuman Khandual static void power8_config_bhrb(u64 pmu_bhrb_filter) 264b1113557SAnshuman Khandual { 265b1113557SAnshuman Khandual /* Enable BHRB filter in PMU */ 266b1113557SAnshuman Khandual mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 267b1113557SAnshuman Khandual } 268b1113557SAnshuman Khandual 2692fdd313fSMichael Ellerman #define C(x) PERF_COUNT_HW_CACHE_##x 2702fdd313fSMichael Ellerman 2712fdd313fSMichael Ellerman /* 2722fdd313fSMichael Ellerman * Table of generalized cache-related events. 2732fdd313fSMichael Ellerman * 0 means not supported, -1 means nonsensical, other values 2742fdd313fSMichael Ellerman * are event codes. 2752fdd313fSMichael Ellerman */ 2762fdd313fSMichael Ellerman static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 2772fdd313fSMichael Ellerman [ C(L1D) ] = { 2782fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2792fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 2802fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_LD_MISS_L1, 2812fdd313fSMichael Ellerman }, 2822fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2832fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 2842fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 2852fdd313fSMichael Ellerman }, 2862fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2872fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L1_PREF, 2882fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 2892fdd313fSMichael Ellerman }, 2902fdd313fSMichael Ellerman }, 2912fdd313fSMichael Ellerman [ C(L1I) ] = { 2922fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2932fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 2942fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 2952fdd313fSMichael Ellerman }, 2962fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2972fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 2982fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2992fdd313fSMichael Ellerman }, 3002fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3012fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 3022fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 3032fdd313fSMichael Ellerman }, 3042fdd313fSMichael Ellerman }, 3052fdd313fSMichael Ellerman [ C(LL) ] = { 3062fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3072fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 3082fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 3092fdd313fSMichael Ellerman }, 3102fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3112fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L2_ST, 3122fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_L2_ST_MISS, 3132fdd313fSMichael Ellerman }, 3142fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3152fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 3162fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 3172fdd313fSMichael Ellerman }, 3182fdd313fSMichael Ellerman }, 3192fdd313fSMichael Ellerman [ C(DTLB) ] = { 3202fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3212fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 3222fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_DTLB_MISS, 3232fdd313fSMichael Ellerman }, 3242fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3252fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3262fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3272fdd313fSMichael Ellerman }, 3282fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3292fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3302fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3312fdd313fSMichael Ellerman }, 3322fdd313fSMichael Ellerman }, 3332fdd313fSMichael Ellerman [ C(ITLB) ] = { 3342fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3352fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 3362fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_ITLB_MISS, 3372fdd313fSMichael Ellerman }, 3382fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3392fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3402fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3412fdd313fSMichael Ellerman }, 3422fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3432fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3442fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3452fdd313fSMichael Ellerman }, 3462fdd313fSMichael Ellerman }, 3472fdd313fSMichael Ellerman [ C(BPU) ] = { 3482fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3492fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_BRU_FIN, 3502fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 3512fdd313fSMichael Ellerman }, 3522fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3532fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3542fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3552fdd313fSMichael Ellerman }, 3562fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3572fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3582fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3592fdd313fSMichael Ellerman }, 3602fdd313fSMichael Ellerman }, 3612fdd313fSMichael Ellerman [ C(NODE) ] = { 3622fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3632fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3642fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3652fdd313fSMichael Ellerman }, 3662fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3672fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3682fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3692fdd313fSMichael Ellerman }, 3702fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3712fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3722fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3732fdd313fSMichael Ellerman }, 3742fdd313fSMichael Ellerman }, 3752fdd313fSMichael Ellerman }; 3762fdd313fSMichael Ellerman 3772fdd313fSMichael Ellerman #undef C 3782fdd313fSMichael Ellerman 379e05b9b9eSMichael Ellerman static struct power_pmu power8_pmu = { 380e05b9b9eSMichael Ellerman .name = "POWER8", 3814d3576b2SMadhavan Srinivasan .n_counter = MAX_PMU_COUNTERS, 382e05b9b9eSMichael Ellerman .max_alternatives = MAX_ALT + 1, 3834d3576b2SMadhavan Srinivasan .add_fields = ISA207_ADD_FIELDS, 3844d3576b2SMadhavan Srinivasan .test_adder = ISA207_TEST_ADDER, 3857ffd948fSMadhavan Srinivasan .compute_mmcr = isa207_compute_mmcr, 386b1113557SAnshuman Khandual .config_bhrb = power8_config_bhrb, 387b1113557SAnshuman Khandual .bhrb_filter_map = power8_bhrb_filter_map, 3887ffd948fSMadhavan Srinivasan .get_constraint = isa207_get_constraint, 389e05b9b9eSMichael Ellerman .get_alternatives = power8_get_alternatives, 3907ffd948fSMadhavan Srinivasan .disable_pmc = isa207_disable_pmc, 391370f06c8SMadhavan Srinivasan .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 392e05b9b9eSMichael Ellerman .n_generic = ARRAY_SIZE(power8_generic_events), 393e05b9b9eSMichael Ellerman .generic_events = power8_generic_events, 3942fdd313fSMichael Ellerman .cache_events = &power8_cache_events, 395e05b9b9eSMichael Ellerman .attr_groups = power8_pmu_attr_groups, 396b1113557SAnshuman Khandual .bhrb_nr = 32, 397e05b9b9eSMichael Ellerman }; 398e05b9b9eSMichael Ellerman 399e05b9b9eSMichael Ellerman static int __init init_power8_pmu(void) 400e05b9b9eSMichael Ellerman { 4015d7ead00SMichael Ellerman int rc; 4025d7ead00SMichael Ellerman 403e05b9b9eSMichael Ellerman if (!cur_cpu_spec->oprofile_cpu_type || 404e05b9b9eSMichael Ellerman strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8")) 405e05b9b9eSMichael Ellerman return -ENODEV; 406e05b9b9eSMichael Ellerman 4075d7ead00SMichael Ellerman rc = register_power_pmu(&power8_pmu); 4085d7ead00SMichael Ellerman if (rc) 4095d7ead00SMichael Ellerman return rc; 4105d7ead00SMichael Ellerman 4115d7ead00SMichael Ellerman /* Tell userspace that EBB is supported */ 4125d7ead00SMichael Ellerman cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 4135d7ead00SMichael Ellerman 414c2e37a26SMichael Ellerman if (cpu_has_feature(CPU_FTR_PMAO_BUG)) 415c2e37a26SMichael Ellerman pr_info("PMAO restore workaround active.\n"); 416c2e37a26SMichael Ellerman 4175d7ead00SMichael Ellerman return 0; 418e05b9b9eSMichael Ellerman } 419e05b9b9eSMichael Ellerman early_initcall(init_power8_pmu); 420