1e05b9b9eSMichael Ellerman /* 2e05b9b9eSMichael Ellerman * Performance counter support for POWER8 processors. 3e05b9b9eSMichael Ellerman * 4e05b9b9eSMichael Ellerman * Copyright 2009 Paul Mackerras, IBM Corporation. 5e05b9b9eSMichael Ellerman * Copyright 2013 Michael Ellerman, IBM Corporation. 6e05b9b9eSMichael Ellerman * 7e05b9b9eSMichael Ellerman * This program is free software; you can redistribute it and/or 8e05b9b9eSMichael Ellerman * modify it under the terms of the GNU General Public License 9e05b9b9eSMichael Ellerman * as published by the Free Software Foundation; either version 10e05b9b9eSMichael Ellerman * 2 of the License, or (at your option) any later version. 11e05b9b9eSMichael Ellerman */ 12e05b9b9eSMichael Ellerman 13c2e37a26SMichael Ellerman #define pr_fmt(fmt) "power8-pmu: " fmt 14c2e37a26SMichael Ellerman 154d3576b2SMadhavan Srinivasan #include "isa207-common.h" 16e05b9b9eSMichael Ellerman 17e05b9b9eSMichael Ellerman /* 18e05b9b9eSMichael Ellerman * Some power8 event codes. 19e05b9b9eSMichael Ellerman */ 20e0728b50SSukadev Bhattiprolu #define EVENT(_name, _code) _name = _code, 21e05b9b9eSMichael Ellerman 22e0728b50SSukadev Bhattiprolu enum { 23e0728b50SSukadev Bhattiprolu #include "power8-events-list.h" 24e0728b50SSukadev Bhattiprolu }; 252fdd313fSMichael Ellerman 26e0728b50SSukadev Bhattiprolu #undef EVENT 27e05b9b9eSMichael Ellerman 28b1113557SAnshuman Khandual /* MMCRA IFM bits - POWER8 */ 29b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM1 0x0000000040000000UL 30b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM2 0x0000000080000000UL 31b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM3 0x00000000C0000000UL 32b1113557SAnshuman Khandual 3360b00025SMadhavan Srinivasan /* PowerISA v2.07 format attribute structure*/ 3460b00025SMadhavan Srinivasan extern struct attribute_group isa207_pmu_format_group; 3560b00025SMadhavan Srinivasan 36e05b9b9eSMichael Ellerman /* Table of alternatives, sorted by column 0 */ 37e05b9b9eSMichael Ellerman static const unsigned int event_alternatives[][MAX_ALT] = { 385bcca743SMadhavan Srinivasan { PM_MRK_ST_CMPL, PM_MRK_ST_CMPL_ALT }, 395bcca743SMadhavan Srinivasan { PM_BR_MRK_2PATH, PM_BR_MRK_2PATH_ALT }, 405bcca743SMadhavan Srinivasan { PM_L3_CO_MEPF, PM_L3_CO_MEPF_ALT }, 415bcca743SMadhavan Srinivasan { PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L2MISS_ALT }, 425bcca743SMadhavan Srinivasan { PM_CMPLU_STALL_ALT, PM_CMPLU_STALL }, 435bcca743SMadhavan Srinivasan { PM_BR_2PATH, PM_BR_2PATH_ALT }, 445bcca743SMadhavan Srinivasan { PM_INST_DISP, PM_INST_DISP_ALT }, 455bcca743SMadhavan Srinivasan { PM_RUN_CYC_ALT, PM_RUN_CYC }, 465bcca743SMadhavan Srinivasan { PM_MRK_FILT_MATCH, PM_MRK_FILT_MATCH_ALT }, 475bcca743SMadhavan Srinivasan { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT }, 485bcca743SMadhavan Srinivasan { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 49e05b9b9eSMichael Ellerman }; 50e05b9b9eSMichael Ellerman 51e05b9b9eSMichael Ellerman static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 52e05b9b9eSMichael Ellerman { 5370a7e720SMadhavan Srinivasan int num_alt = 0; 54e05b9b9eSMichael Ellerman 5570a7e720SMadhavan Srinivasan num_alt = isa207_get_alternatives(event, alt, 5670a7e720SMadhavan Srinivasan ARRAY_SIZE(event_alternatives), flags, 5770a7e720SMadhavan Srinivasan event_alternatives); 58e05b9b9eSMichael Ellerman 59e05b9b9eSMichael Ellerman return num_alt; 60e05b9b9eSMichael Ellerman } 61e05b9b9eSMichael Ellerman 62e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 63e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC); 64e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 65e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 66e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN); 67e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 68e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 69e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); 70f2080b9aSMadhavan Srinivasan GENERIC_EVENT_ATTR(mem_access, MEM_ACCESS); 71e0728b50SSukadev Bhattiprolu 72e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 73e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 74e0728b50SSukadev Bhattiprolu 75e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 76e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 77e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 78e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 79e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 80e0728b50SSukadev Bhattiprolu 81e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 82e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 83e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 84e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 85e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 86e0728b50SSukadev Bhattiprolu 87e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 88e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN); 89e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 90e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 91e0728b50SSukadev Bhattiprolu 92e0728b50SSukadev Bhattiprolu static struct attribute *power8_events_attr[] = { 93e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_CYC), 94e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC), 95e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_CMPLU_STALL), 96e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_INST_CMPL), 97e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_BRU_FIN), 98e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 99e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_LD_REF_L1), 100e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_LD_MISS_L1), 101f2080b9aSMadhavan Srinivasan GENERIC_EVENT_PTR(MEM_ACCESS), 102e0728b50SSukadev Bhattiprolu 103e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_LD_MISS_L1), 104e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_LD_REF_L1), 105e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L1_PREF), 106e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_ST_MISS_L1), 107e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 108e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_INST_FROM_L1), 109e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 110e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 111e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DATA_FROM_L3), 112e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L3_PREF_ALL), 113e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L2_ST_MISS), 114e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L2_ST), 115e0728b50SSukadev Bhattiprolu 116e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 117e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_BRU_FIN), 118e0728b50SSukadev Bhattiprolu 119e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DTLB_MISS), 120e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_ITLB_MISS), 121e0728b50SSukadev Bhattiprolu NULL 122e0728b50SSukadev Bhattiprolu }; 123e0728b50SSukadev Bhattiprolu 124e0728b50SSukadev Bhattiprolu static struct attribute_group power8_pmu_events_group = { 125e0728b50SSukadev Bhattiprolu .name = "events", 126e0728b50SSukadev Bhattiprolu .attrs = power8_events_attr, 127e0728b50SSukadev Bhattiprolu }; 128e0728b50SSukadev Bhattiprolu 129e05b9b9eSMichael Ellerman static const struct attribute_group *power8_pmu_attr_groups[] = { 13060b00025SMadhavan Srinivasan &isa207_pmu_format_group, 131e0728b50SSukadev Bhattiprolu &power8_pmu_events_group, 132e05b9b9eSMichael Ellerman NULL, 133e05b9b9eSMichael Ellerman }; 134e05b9b9eSMichael Ellerman 135e05b9b9eSMichael Ellerman static int power8_generic_events[] = { 136e05b9b9eSMichael Ellerman [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 137e05b9b9eSMichael Ellerman [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC, 138e05b9b9eSMichael Ellerman [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 139e05b9b9eSMichael Ellerman [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 140e05b9b9eSMichael Ellerman [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN, 141e05b9b9eSMichael Ellerman [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 1422fdd313fSMichael Ellerman [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 1432fdd313fSMichael Ellerman [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 144e05b9b9eSMichael Ellerman }; 145e05b9b9eSMichael Ellerman 146b1113557SAnshuman Khandual static u64 power8_bhrb_filter_map(u64 branch_sample_type) 147b1113557SAnshuman Khandual { 148b1113557SAnshuman Khandual u64 pmu_bhrb_filter = 0; 149b1113557SAnshuman Khandual 1507689bdcaSAnshuman Khandual /* BHRB and regular PMU events share the same privilege state 151b1113557SAnshuman Khandual * filter configuration. BHRB is always recorded along with a 1527689bdcaSAnshuman Khandual * regular PMU event. As the privilege state filter is handled 1537689bdcaSAnshuman Khandual * in the basic PMC configuration of the accompanying regular 1547689bdcaSAnshuman Khandual * PMU event, we ignore any separate BHRB specific request. 155b1113557SAnshuman Khandual */ 156b1113557SAnshuman Khandual 157b1113557SAnshuman Khandual /* No branch filter requested */ 158b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 159b1113557SAnshuman Khandual return pmu_bhrb_filter; 160b1113557SAnshuman Khandual 161b1113557SAnshuman Khandual /* Invalid branch filter options - HW does not support */ 162b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 163b1113557SAnshuman Khandual return -1; 164b1113557SAnshuman Khandual 165b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 166b1113557SAnshuman Khandual return -1; 167b1113557SAnshuman Khandual 16824f1a79aSStephane Eranian if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 16924f1a79aSStephane Eranian return -1; 17024f1a79aSStephane Eranian 171b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 172b1113557SAnshuman Khandual pmu_bhrb_filter |= POWER8_MMCRA_IFM1; 173b1113557SAnshuman Khandual return pmu_bhrb_filter; 174b1113557SAnshuman Khandual } 175b1113557SAnshuman Khandual 176b1113557SAnshuman Khandual /* Every thing else is unsupported */ 177b1113557SAnshuman Khandual return -1; 178b1113557SAnshuman Khandual } 179b1113557SAnshuman Khandual 180b1113557SAnshuman Khandual static void power8_config_bhrb(u64 pmu_bhrb_filter) 181b1113557SAnshuman Khandual { 182b1113557SAnshuman Khandual /* Enable BHRB filter in PMU */ 183b1113557SAnshuman Khandual mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 184b1113557SAnshuman Khandual } 185b1113557SAnshuman Khandual 1862fdd313fSMichael Ellerman #define C(x) PERF_COUNT_HW_CACHE_##x 1872fdd313fSMichael Ellerman 1882fdd313fSMichael Ellerman /* 1892fdd313fSMichael Ellerman * Table of generalized cache-related events. 1902fdd313fSMichael Ellerman * 0 means not supported, -1 means nonsensical, other values 1912fdd313fSMichael Ellerman * are event codes. 1922fdd313fSMichael Ellerman */ 1932fdd313fSMichael Ellerman static int power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 1942fdd313fSMichael Ellerman [ C(L1D) ] = { 1952fdd313fSMichael Ellerman [ C(OP_READ) ] = { 1962fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 1972fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_LD_MISS_L1, 1982fdd313fSMichael Ellerman }, 1992fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2002fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 2012fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 2022fdd313fSMichael Ellerman }, 2032fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2042fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L1_PREF, 2052fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 2062fdd313fSMichael Ellerman }, 2072fdd313fSMichael Ellerman }, 2082fdd313fSMichael Ellerman [ C(L1I) ] = { 2092fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2102fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 2112fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 2122fdd313fSMichael Ellerman }, 2132fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2142fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 2152fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2162fdd313fSMichael Ellerman }, 2172fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2182fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 2192fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 2202fdd313fSMichael Ellerman }, 2212fdd313fSMichael Ellerman }, 2222fdd313fSMichael Ellerman [ C(LL) ] = { 2232fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2242fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 2252fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 2262fdd313fSMichael Ellerman }, 2272fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2282fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L2_ST, 2292fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_L2_ST_MISS, 2302fdd313fSMichael Ellerman }, 2312fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2322fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 2332fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 2342fdd313fSMichael Ellerman }, 2352fdd313fSMichael Ellerman }, 2362fdd313fSMichael Ellerman [ C(DTLB) ] = { 2372fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2382fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 2392fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_DTLB_MISS, 2402fdd313fSMichael Ellerman }, 2412fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2422fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2432fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2442fdd313fSMichael Ellerman }, 2452fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2462fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2472fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2482fdd313fSMichael Ellerman }, 2492fdd313fSMichael Ellerman }, 2502fdd313fSMichael Ellerman [ C(ITLB) ] = { 2512fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2522fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 2532fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_ITLB_MISS, 2542fdd313fSMichael Ellerman }, 2552fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2562fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2572fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2582fdd313fSMichael Ellerman }, 2592fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2602fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2612fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2622fdd313fSMichael Ellerman }, 2632fdd313fSMichael Ellerman }, 2642fdd313fSMichael Ellerman [ C(BPU) ] = { 2652fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2662fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_BRU_FIN, 2672fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 2682fdd313fSMichael Ellerman }, 2692fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2702fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2712fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2722fdd313fSMichael Ellerman }, 2732fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2742fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2752fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2762fdd313fSMichael Ellerman }, 2772fdd313fSMichael Ellerman }, 2782fdd313fSMichael Ellerman [ C(NODE) ] = { 2792fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2802fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2812fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2822fdd313fSMichael Ellerman }, 2832fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2842fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2852fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2862fdd313fSMichael Ellerman }, 2872fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2882fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 2892fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2902fdd313fSMichael Ellerman }, 2912fdd313fSMichael Ellerman }, 2922fdd313fSMichael Ellerman }; 2932fdd313fSMichael Ellerman 2942fdd313fSMichael Ellerman #undef C 2952fdd313fSMichael Ellerman 296e05b9b9eSMichael Ellerman static struct power_pmu power8_pmu = { 297e05b9b9eSMichael Ellerman .name = "POWER8", 2984d3576b2SMadhavan Srinivasan .n_counter = MAX_PMU_COUNTERS, 299e05b9b9eSMichael Ellerman .max_alternatives = MAX_ALT + 1, 3004d3576b2SMadhavan Srinivasan .add_fields = ISA207_ADD_FIELDS, 3014d3576b2SMadhavan Srinivasan .test_adder = ISA207_TEST_ADDER, 3027ffd948fSMadhavan Srinivasan .compute_mmcr = isa207_compute_mmcr, 303b1113557SAnshuman Khandual .config_bhrb = power8_config_bhrb, 304b1113557SAnshuman Khandual .bhrb_filter_map = power8_bhrb_filter_map, 3057ffd948fSMadhavan Srinivasan .get_constraint = isa207_get_constraint, 306e05b9b9eSMichael Ellerman .get_alternatives = power8_get_alternatives, 307453ce7a9SMadhavan Srinivasan .get_mem_data_src = isa207_get_mem_data_src, 308453ce7a9SMadhavan Srinivasan .get_mem_weight = isa207_get_mem_weight, 3097ffd948fSMadhavan Srinivasan .disable_pmc = isa207_disable_pmc, 310370f06c8SMadhavan Srinivasan .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 311e05b9b9eSMichael Ellerman .n_generic = ARRAY_SIZE(power8_generic_events), 312e05b9b9eSMichael Ellerman .generic_events = power8_generic_events, 3132fdd313fSMichael Ellerman .cache_events = &power8_cache_events, 314e05b9b9eSMichael Ellerman .attr_groups = power8_pmu_attr_groups, 315b1113557SAnshuman Khandual .bhrb_nr = 32, 316e05b9b9eSMichael Ellerman }; 317e05b9b9eSMichael Ellerman 318e05b9b9eSMichael Ellerman static int __init init_power8_pmu(void) 319e05b9b9eSMichael Ellerman { 3205d7ead00SMichael Ellerman int rc; 3215d7ead00SMichael Ellerman 322e05b9b9eSMichael Ellerman if (!cur_cpu_spec->oprofile_cpu_type || 323e05b9b9eSMichael Ellerman strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8")) 324e05b9b9eSMichael Ellerman return -ENODEV; 325e05b9b9eSMichael Ellerman 3265d7ead00SMichael Ellerman rc = register_power_pmu(&power8_pmu); 3275d7ead00SMichael Ellerman if (rc) 3285d7ead00SMichael Ellerman return rc; 3295d7ead00SMichael Ellerman 3305d7ead00SMichael Ellerman /* Tell userspace that EBB is supported */ 3315d7ead00SMichael Ellerman cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 3325d7ead00SMichael Ellerman 333c2e37a26SMichael Ellerman if (cpu_has_feature(CPU_FTR_PMAO_BUG)) 334c2e37a26SMichael Ellerman pr_info("PMAO restore workaround active.\n"); 335c2e37a26SMichael Ellerman 3365d7ead00SMichael Ellerman return 0; 337e05b9b9eSMichael Ellerman } 338e05b9b9eSMichael Ellerman early_initcall(init_power8_pmu); 339