12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2e05b9b9eSMichael Ellerman /* 3e05b9b9eSMichael Ellerman * Performance counter support for POWER8 processors. 4e05b9b9eSMichael Ellerman * 5e05b9b9eSMichael Ellerman * Copyright 2009 Paul Mackerras, IBM Corporation. 6e05b9b9eSMichael Ellerman * Copyright 2013 Michael Ellerman, IBM Corporation. 7e05b9b9eSMichael Ellerman */ 8e05b9b9eSMichael Ellerman 9c2e37a26SMichael Ellerman #define pr_fmt(fmt) "power8-pmu: " fmt 10c2e37a26SMichael Ellerman 114d3576b2SMadhavan Srinivasan #include "isa207-common.h" 12e05b9b9eSMichael Ellerman 13e05b9b9eSMichael Ellerman /* 14e05b9b9eSMichael Ellerman * Some power8 event codes. 15e05b9b9eSMichael Ellerman */ 16e0728b50SSukadev Bhattiprolu #define EVENT(_name, _code) _name = _code, 17e05b9b9eSMichael Ellerman 18e0728b50SSukadev Bhattiprolu enum { 19e0728b50SSukadev Bhattiprolu #include "power8-events-list.h" 20e0728b50SSukadev Bhattiprolu }; 212fdd313fSMichael Ellerman 22e0728b50SSukadev Bhattiprolu #undef EVENT 23e05b9b9eSMichael Ellerman 24b1113557SAnshuman Khandual /* MMCRA IFM bits - POWER8 */ 25b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM1 0x0000000040000000UL 26b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM2 0x0000000080000000UL 27b1113557SAnshuman Khandual #define POWER8_MMCRA_IFM3 0x00000000C0000000UL 283202e35eSRavi Bangoria #define POWER8_MMCRA_BHRB_MASK 0x00000000C0000000UL 29b1113557SAnshuman Khandual 30458c7017SMadhavan Srinivasan /* 31458c7017SMadhavan Srinivasan * Raw event encoding for PowerISA v2.07 (Power8): 32458c7017SMadhavan Srinivasan * 33458c7017SMadhavan Srinivasan * 60 56 52 48 44 40 36 32 34458c7017SMadhavan Srinivasan * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 35458c7017SMadhavan Srinivasan * | | [ ] [ thresh_cmp ] [ thresh_ctl ] 36458c7017SMadhavan Srinivasan * | | | | 37458c7017SMadhavan Srinivasan * | | *- IFM (Linux) thresh start/stop OR FAB match -* 38458c7017SMadhavan Srinivasan * | *- BHRB (Linux) 39458c7017SMadhavan Srinivasan * *- EBB (Linux) 40458c7017SMadhavan Srinivasan * 41458c7017SMadhavan Srinivasan * 28 24 20 16 12 8 4 0 42458c7017SMadhavan Srinivasan * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 43458c7017SMadhavan Srinivasan * [ ] [ sample ] [cache] [ pmc ] [unit ] c m [ pmcxsel ] 44458c7017SMadhavan Srinivasan * | | | | | 45458c7017SMadhavan Srinivasan * | | | | *- mark 46458c7017SMadhavan Srinivasan * | | *- L1/L2/L3 cache_sel | 47458c7017SMadhavan Srinivasan * | | | 48458c7017SMadhavan Srinivasan * | *- sampling mode for marked events *- combine 49458c7017SMadhavan Srinivasan * | 50458c7017SMadhavan Srinivasan * *- thresh_sel 51458c7017SMadhavan Srinivasan * 52458c7017SMadhavan Srinivasan * Below uses IBM bit numbering. 53458c7017SMadhavan Srinivasan * 54458c7017SMadhavan Srinivasan * MMCR1[x:y] = unit (PMCxUNIT) 55458c7017SMadhavan Srinivasan * MMCR1[x] = combine (PMCxCOMB) 56458c7017SMadhavan Srinivasan * 57458c7017SMadhavan Srinivasan * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 58458c7017SMadhavan Srinivasan * # PM_MRK_FAB_RSP_MATCH 59458c7017SMadhavan Srinivasan * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) 60458c7017SMadhavan Srinivasan * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 61458c7017SMadhavan Srinivasan * # PM_MRK_FAB_RSP_MATCH_CYC 62458c7017SMadhavan Srinivasan * MMCR1[20:27] = thresh_ctl (FAB_CRESP_MATCH / FAB_TYPE_MATCH) 63458c7017SMadhavan Srinivasan * else 64458c7017SMadhavan Srinivasan * MMCRA[48:55] = thresh_ctl (THRESH START/END) 65458c7017SMadhavan Srinivasan * 66458c7017SMadhavan Srinivasan * if thresh_sel: 67458c7017SMadhavan Srinivasan * MMCRA[45:47] = thresh_sel 68458c7017SMadhavan Srinivasan * 69458c7017SMadhavan Srinivasan * if thresh_cmp: 70458c7017SMadhavan Srinivasan * MMCRA[22:24] = thresh_cmp[0:2] 71458c7017SMadhavan Srinivasan * MMCRA[25:31] = thresh_cmp[3:9] 72458c7017SMadhavan Srinivasan * 73458c7017SMadhavan Srinivasan * if unit == 6 or unit == 7 74458c7017SMadhavan Srinivasan * MMCRC[53:55] = cache_sel[1:3] (L2EVENT_SEL) 75458c7017SMadhavan Srinivasan * else if unit == 8 or unit == 9: 76458c7017SMadhavan Srinivasan * if cache_sel[0] == 0: # L3 bank 77458c7017SMadhavan Srinivasan * MMCRC[47:49] = cache_sel[1:3] (L3EVENT_SEL0) 78458c7017SMadhavan Srinivasan * else if cache_sel[0] == 1: 79458c7017SMadhavan Srinivasan * MMCRC[50:51] = cache_sel[2:3] (L3EVENT_SEL1) 80458c7017SMadhavan Srinivasan * else if cache_sel[1]: # L1 event 81458c7017SMadhavan Srinivasan * MMCR1[16] = cache_sel[2] 82458c7017SMadhavan Srinivasan * MMCR1[17] = cache_sel[3] 83458c7017SMadhavan Srinivasan * 84458c7017SMadhavan Srinivasan * if mark: 85458c7017SMadhavan Srinivasan * MMCRA[63] = 1 (SAMPLE_ENABLE) 86458c7017SMadhavan Srinivasan * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 87458c7017SMadhavan Srinivasan * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 88458c7017SMadhavan Srinivasan * 89458c7017SMadhavan Srinivasan * if EBB and BHRB: 90458c7017SMadhavan Srinivasan * MMCRA[32:33] = IFM 91458c7017SMadhavan Srinivasan * 92458c7017SMadhavan Srinivasan */ 93458c7017SMadhavan Srinivasan 9460b00025SMadhavan Srinivasan /* PowerISA v2.07 format attribute structure*/ 956b3a3e12SRohan McLure extern const struct attribute_group isa207_pmu_format_group; 9660b00025SMadhavan Srinivasan 97e05b9b9eSMichael Ellerman /* Table of alternatives, sorted by column 0 */ 98e05b9b9eSMichael Ellerman static const unsigned int event_alternatives[][MAX_ALT] = { 995bcca743SMadhavan Srinivasan { PM_MRK_ST_CMPL, PM_MRK_ST_CMPL_ALT }, 1005bcca743SMadhavan Srinivasan { PM_BR_MRK_2PATH, PM_BR_MRK_2PATH_ALT }, 1015bcca743SMadhavan Srinivasan { PM_L3_CO_MEPF, PM_L3_CO_MEPF_ALT }, 1025bcca743SMadhavan Srinivasan { PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L2MISS_ALT }, 1035bcca743SMadhavan Srinivasan { PM_CMPLU_STALL_ALT, PM_CMPLU_STALL }, 1045bcca743SMadhavan Srinivasan { PM_BR_2PATH, PM_BR_2PATH_ALT }, 1055bcca743SMadhavan Srinivasan { PM_INST_DISP, PM_INST_DISP_ALT }, 1065bcca743SMadhavan Srinivasan { PM_RUN_CYC_ALT, PM_RUN_CYC }, 1075bcca743SMadhavan Srinivasan { PM_MRK_FILT_MATCH, PM_MRK_FILT_MATCH_ALT }, 1085bcca743SMadhavan Srinivasan { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT }, 1095bcca743SMadhavan Srinivasan { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 110e05b9b9eSMichael Ellerman }; 111e05b9b9eSMichael Ellerman 112e05b9b9eSMichael Ellerman static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 113e05b9b9eSMichael Ellerman { 11470a7e720SMadhavan Srinivasan int num_alt = 0; 115e05b9b9eSMichael Ellerman 11670a7e720SMadhavan Srinivasan num_alt = isa207_get_alternatives(event, alt, 11770a7e720SMadhavan Srinivasan ARRAY_SIZE(event_alternatives), flags, 11870a7e720SMadhavan Srinivasan event_alternatives); 119e05b9b9eSMichael Ellerman 120e05b9b9eSMichael Ellerman return num_alt; 121e05b9b9eSMichael Ellerman } 122e05b9b9eSMichael Ellerman 123e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 124e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC); 125e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 126e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 127e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN); 128e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 129e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 130e0728b50SSukadev Bhattiprolu GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); 131f2080b9aSMadhavan Srinivasan GENERIC_EVENT_ATTR(mem_access, MEM_ACCESS); 132e0728b50SSukadev Bhattiprolu 133e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 134e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 135e0728b50SSukadev Bhattiprolu 136e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF); 137e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 138e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 139e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 140e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE); 141e0728b50SSukadev Bhattiprolu 142e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 143e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 144e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL); 145e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 146e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 147e0728b50SSukadev Bhattiprolu 148e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 149e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(branch-loads, PM_BRU_FIN); 150e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 151e0728b50SSukadev Bhattiprolu CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 152e0728b50SSukadev Bhattiprolu 153e0728b50SSukadev Bhattiprolu static struct attribute *power8_events_attr[] = { 154e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_CYC), 155e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC), 156e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_CMPLU_STALL), 157e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_INST_CMPL), 158e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_BRU_FIN), 159e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 160e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_LD_REF_L1), 161e0728b50SSukadev Bhattiprolu GENERIC_EVENT_PTR(PM_LD_MISS_L1), 162f2080b9aSMadhavan Srinivasan GENERIC_EVENT_PTR(MEM_ACCESS), 163e0728b50SSukadev Bhattiprolu 164e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_LD_MISS_L1), 165e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_LD_REF_L1), 166e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L1_PREF), 167e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_ST_MISS_L1), 168e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 169e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_INST_FROM_L1), 170e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_IC_PREF_WRITE), 171e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 172e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DATA_FROM_L3), 173e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L3_PREF_ALL), 174e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L2_ST_MISS), 175e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_L2_ST), 176e0728b50SSukadev Bhattiprolu 177e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 178e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_BRU_FIN), 179e0728b50SSukadev Bhattiprolu 180e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_DTLB_MISS), 181e0728b50SSukadev Bhattiprolu CACHE_EVENT_PTR(PM_ITLB_MISS), 182e0728b50SSukadev Bhattiprolu NULL 183e0728b50SSukadev Bhattiprolu }; 184e0728b50SSukadev Bhattiprolu 1856b3a3e12SRohan McLure static const struct attribute_group power8_pmu_events_group = { 186e0728b50SSukadev Bhattiprolu .name = "events", 187e0728b50SSukadev Bhattiprolu .attrs = power8_events_attr, 188e0728b50SSukadev Bhattiprolu }; 189e0728b50SSukadev Bhattiprolu 190*6320e693SAthira Rajeev static struct attribute *power8_pmu_caps_attrs[] = { 191*6320e693SAthira Rajeev NULL 192*6320e693SAthira Rajeev }; 193*6320e693SAthira Rajeev 194*6320e693SAthira Rajeev static struct attribute_group power8_pmu_caps_group = { 195*6320e693SAthira Rajeev .name = "caps", 196*6320e693SAthira Rajeev .attrs = power8_pmu_caps_attrs, 197*6320e693SAthira Rajeev }; 198*6320e693SAthira Rajeev 199e05b9b9eSMichael Ellerman static const struct attribute_group *power8_pmu_attr_groups[] = { 20060b00025SMadhavan Srinivasan &isa207_pmu_format_group, 201e0728b50SSukadev Bhattiprolu &power8_pmu_events_group, 202*6320e693SAthira Rajeev &power8_pmu_caps_group, 203e05b9b9eSMichael Ellerman NULL, 204e05b9b9eSMichael Ellerman }; 205e05b9b9eSMichael Ellerman 206e05b9b9eSMichael Ellerman static int power8_generic_events[] = { 207e05b9b9eSMichael Ellerman [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 208e05b9b9eSMichael Ellerman [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC, 209e05b9b9eSMichael Ellerman [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 210e05b9b9eSMichael Ellerman [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 211e05b9b9eSMichael Ellerman [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN, 212e05b9b9eSMichael Ellerman [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 2132fdd313fSMichael Ellerman [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 2142fdd313fSMichael Ellerman [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 215e05b9b9eSMichael Ellerman }; 216e05b9b9eSMichael Ellerman 217b1113557SAnshuman Khandual static u64 power8_bhrb_filter_map(u64 branch_sample_type) 218b1113557SAnshuman Khandual { 219b1113557SAnshuman Khandual u64 pmu_bhrb_filter = 0; 220b1113557SAnshuman Khandual 2217689bdcaSAnshuman Khandual /* BHRB and regular PMU events share the same privilege state 222b1113557SAnshuman Khandual * filter configuration. BHRB is always recorded along with a 2237689bdcaSAnshuman Khandual * regular PMU event. As the privilege state filter is handled 2247689bdcaSAnshuman Khandual * in the basic PMC configuration of the accompanying regular 2257689bdcaSAnshuman Khandual * PMU event, we ignore any separate BHRB specific request. 226b1113557SAnshuman Khandual */ 227b1113557SAnshuman Khandual 228b1113557SAnshuman Khandual /* No branch filter requested */ 229b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 230b1113557SAnshuman Khandual return pmu_bhrb_filter; 231b1113557SAnshuman Khandual 232b1113557SAnshuman Khandual /* Invalid branch filter options - HW does not support */ 233b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 234b1113557SAnshuman Khandual return -1; 235b1113557SAnshuman Khandual 236b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) 237b1113557SAnshuman Khandual return -1; 238b1113557SAnshuman Khandual 23924f1a79aSStephane Eranian if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 24024f1a79aSStephane Eranian return -1; 24124f1a79aSStephane Eranian 242b1113557SAnshuman Khandual if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 243b1113557SAnshuman Khandual pmu_bhrb_filter |= POWER8_MMCRA_IFM1; 244b1113557SAnshuman Khandual return pmu_bhrb_filter; 245b1113557SAnshuman Khandual } 246b1113557SAnshuman Khandual 247b1113557SAnshuman Khandual /* Every thing else is unsupported */ 248b1113557SAnshuman Khandual return -1; 249b1113557SAnshuman Khandual } 250b1113557SAnshuman Khandual 251b1113557SAnshuman Khandual static void power8_config_bhrb(u64 pmu_bhrb_filter) 252b1113557SAnshuman Khandual { 2533202e35eSRavi Bangoria pmu_bhrb_filter &= POWER8_MMCRA_BHRB_MASK; 2543202e35eSRavi Bangoria 255b1113557SAnshuman Khandual /* Enable BHRB filter in PMU */ 256b1113557SAnshuman Khandual mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 257b1113557SAnshuman Khandual } 258b1113557SAnshuman Khandual 2592fdd313fSMichael Ellerman #define C(x) PERF_COUNT_HW_CACHE_##x 2602fdd313fSMichael Ellerman 2612fdd313fSMichael Ellerman /* 2622fdd313fSMichael Ellerman * Table of generalized cache-related events. 2632fdd313fSMichael Ellerman * 0 means not supported, -1 means nonsensical, other values 2642fdd313fSMichael Ellerman * are event codes. 2652fdd313fSMichael Ellerman */ 2669d4fc86dSAthira Rajeev static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 2672fdd313fSMichael Ellerman [ C(L1D) ] = { 2682fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2692fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_LD_REF_L1, 2702fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_LD_MISS_L1, 2712fdd313fSMichael Ellerman }, 2722fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2732fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 2742fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_ST_MISS_L1, 2752fdd313fSMichael Ellerman }, 2762fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2772fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L1_PREF, 2782fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 2792fdd313fSMichael Ellerman }, 2802fdd313fSMichael Ellerman }, 2812fdd313fSMichael Ellerman [ C(L1I) ] = { 2822fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2832fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1, 2842fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS, 2852fdd313fSMichael Ellerman }, 2862fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 2872fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE, 2882fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 2892fdd313fSMichael Ellerman }, 2902fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 2912fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE, 2922fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 2932fdd313fSMichael Ellerman }, 2942fdd313fSMichael Ellerman }, 2952fdd313fSMichael Ellerman [ C(LL) ] = { 2962fdd313fSMichael Ellerman [ C(OP_READ) ] = { 2972fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3, 2982fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS, 2992fdd313fSMichael Ellerman }, 3002fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3012fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L2_ST, 3022fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_L2_ST_MISS, 3032fdd313fSMichael Ellerman }, 3042fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3052fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL, 3062fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = 0, 3072fdd313fSMichael Ellerman }, 3082fdd313fSMichael Ellerman }, 3092fdd313fSMichael Ellerman [ C(DTLB) ] = { 3102fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3112fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 3122fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_DTLB_MISS, 3132fdd313fSMichael Ellerman }, 3142fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3152fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3162fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3172fdd313fSMichael Ellerman }, 3182fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3192fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3202fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3212fdd313fSMichael Ellerman }, 3222fdd313fSMichael Ellerman }, 3232fdd313fSMichael Ellerman [ C(ITLB) ] = { 3242fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3252fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = 0, 3262fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_ITLB_MISS, 3272fdd313fSMichael Ellerman }, 3282fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3292fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3302fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3312fdd313fSMichael Ellerman }, 3322fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3332fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3342fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3352fdd313fSMichael Ellerman }, 3362fdd313fSMichael Ellerman }, 3372fdd313fSMichael Ellerman [ C(BPU) ] = { 3382fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3392fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = PM_BRU_FIN, 3402fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL, 3412fdd313fSMichael Ellerman }, 3422fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3432fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3442fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3452fdd313fSMichael Ellerman }, 3462fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3472fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3482fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3492fdd313fSMichael Ellerman }, 3502fdd313fSMichael Ellerman }, 3512fdd313fSMichael Ellerman [ C(NODE) ] = { 3522fdd313fSMichael Ellerman [ C(OP_READ) ] = { 3532fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3542fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3552fdd313fSMichael Ellerman }, 3562fdd313fSMichael Ellerman [ C(OP_WRITE) ] = { 3572fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3582fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3592fdd313fSMichael Ellerman }, 3602fdd313fSMichael Ellerman [ C(OP_PREFETCH) ] = { 3612fdd313fSMichael Ellerman [ C(RESULT_ACCESS) ] = -1, 3622fdd313fSMichael Ellerman [ C(RESULT_MISS) ] = -1, 3632fdd313fSMichael Ellerman }, 3642fdd313fSMichael Ellerman }, 3652fdd313fSMichael Ellerman }; 3662fdd313fSMichael Ellerman 3672fdd313fSMichael Ellerman #undef C 3682fdd313fSMichael Ellerman 369e05b9b9eSMichael Ellerman static struct power_pmu power8_pmu = { 370e05b9b9eSMichael Ellerman .name = "POWER8", 3714d3576b2SMadhavan Srinivasan .n_counter = MAX_PMU_COUNTERS, 372e05b9b9eSMichael Ellerman .max_alternatives = MAX_ALT + 1, 3734d3576b2SMadhavan Srinivasan .add_fields = ISA207_ADD_FIELDS, 3744d3576b2SMadhavan Srinivasan .test_adder = ISA207_TEST_ADDER, 3757ffd948fSMadhavan Srinivasan .compute_mmcr = isa207_compute_mmcr, 376b1113557SAnshuman Khandual .config_bhrb = power8_config_bhrb, 377b1113557SAnshuman Khandual .bhrb_filter_map = power8_bhrb_filter_map, 3787ffd948fSMadhavan Srinivasan .get_constraint = isa207_get_constraint, 379e05b9b9eSMichael Ellerman .get_alternatives = power8_get_alternatives, 380453ce7a9SMadhavan Srinivasan .get_mem_data_src = isa207_get_mem_data_src, 381453ce7a9SMadhavan Srinivasan .get_mem_weight = isa207_get_mem_weight, 3827ffd948fSMadhavan Srinivasan .disable_pmc = isa207_disable_pmc, 383370f06c8SMadhavan Srinivasan .flags = PPMU_HAS_SIER | PPMU_ARCH_207S, 384e05b9b9eSMichael Ellerman .n_generic = ARRAY_SIZE(power8_generic_events), 385e05b9b9eSMichael Ellerman .generic_events = power8_generic_events, 3862fdd313fSMichael Ellerman .cache_events = &power8_cache_events, 387e05b9b9eSMichael Ellerman .attr_groups = power8_pmu_attr_groups, 388b1113557SAnshuman Khandual .bhrb_nr = 32, 389e05b9b9eSMichael Ellerman }; 390e05b9b9eSMichael Ellerman 391c49f5d88SNick Child int __init init_power8_pmu(void) 392e05b9b9eSMichael Ellerman { 3935d7ead00SMichael Ellerman int rc; 3945d7ead00SMichael Ellerman 395e05b9b9eSMichael Ellerman if (!cur_cpu_spec->oprofile_cpu_type || 396e05b9b9eSMichael Ellerman strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8")) 397e05b9b9eSMichael Ellerman return -ENODEV; 398e05b9b9eSMichael Ellerman 3995d7ead00SMichael Ellerman rc = register_power_pmu(&power8_pmu); 4005d7ead00SMichael Ellerman if (rc) 4015d7ead00SMichael Ellerman return rc; 4025d7ead00SMichael Ellerman 4035d7ead00SMichael Ellerman /* Tell userspace that EBB is supported */ 4045d7ead00SMichael Ellerman cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 4055d7ead00SMichael Ellerman 406c2e37a26SMichael Ellerman if (cpu_has_feature(CPU_FTR_PMAO_BUG)) 407c2e37a26SMichael Ellerman pr_info("PMAO restore workaround active.\n"); 408c2e37a26SMichael Ellerman 4095d7ead00SMichael Ellerman return 0; 410e05b9b9eSMichael Ellerman } 411