1 /*
2  * Performance counter support for POWER8 processors.
3  *
4  * Copyright 2014 Sukadev Bhattiprolu, IBM Corporation.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11 
12 /*
13  * Power8 event codes.
14  */
15 EVENT(PM_CYC,					0x0001e)
16 EVENT(PM_GCT_NOSLOT_CYC,			0x100f8)
17 EVENT(PM_CMPLU_STALL,				0x4000a)
18 EVENT(PM_INST_CMPL,				0x00002)
19 EVENT(PM_BRU_FIN,				0x10068)
20 EVENT(PM_BR_MPRED_CMPL,				0x400f6)
21 
22 /* All L1 D cache load references counted at finish, gated by reject */
23 EVENT(PM_LD_REF_L1,				0x100ee)
24 /* Load Missed L1 */
25 EVENT(PM_LD_MISS_L1,				0x3e054)
26 /* Store Missed L1 */
27 EVENT(PM_ST_MISS_L1,				0x300f0)
28 /* L1 cache data prefetches */
29 EVENT(PM_L1_PREF,				0x0d8b8)
30 /* Instruction fetches from L1 */
31 EVENT(PM_INST_FROM_L1,				0x04080)
32 /* Demand iCache Miss */
33 EVENT(PM_L1_ICACHE_MISS,			0x200fd)
34 /* Instruction Demand sectors wriittent into IL1 */
35 EVENT(PM_L1_DEMAND_WRITE,			0x0408c)
36 /* Instruction prefetch written into IL1 */
37 EVENT(PM_IC_PREF_WRITE,				0x0408e)
38 /* The data cache was reloaded from local core's L3 due to a demand load */
39 EVENT(PM_DATA_FROM_L3,				0x4c042)
40 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
41 EVENT(PM_DATA_FROM_L3MISS,			0x300fe)
42 /* All successful D-side store dispatches for this thread */
43 EVENT(PM_L2_ST,					0x17080)
44 /* All successful D-side store dispatches for this thread that were L2 Miss */
45 EVENT(PM_L2_ST_MISS,				0x17082)
46 /* Total HW L3 prefetches(Load+store) */
47 EVENT(PM_L3_PREF_ALL,				0x4e052)
48 /* Data PTEG reload */
49 EVENT(PM_DTLB_MISS,				0x300fc)
50 /* ITLB Reloaded */
51 EVENT(PM_ITLB_MISS,				0x400fc)
52 /* Run_Instructions */
53 EVENT(PM_RUN_INST_CMPL,				0x500fa)
54 /* Alternate event code for PM_RUN_INST_CMPL */
55 EVENT(PM_RUN_INST_CMPL_ALT,			0x400fa)
56 /* Run_cycles */
57 EVENT(PM_RUN_CYC,				0x600f4)
58 /* Alternate event code for Run_cycles */
59 EVENT(PM_RUN_CYC_ALT,				0x200f4)
60 /* Marked store completed */
61 EVENT(PM_MRK_ST_CMPL,				0x10134)
62 /* Alternate event code for Marked store completed */
63 EVENT(PM_MRK_ST_CMPL_ALT,			0x301e2)
64 /* Marked two path branch */
65 EVENT(PM_BR_MRK_2PATH,				0x10138)
66 /* Alternate event code for PM_BR_MRK_2PATH */
67 EVENT(PM_BR_MRK_2PATH_ALT,			0x40138)
68 /* L3 castouts in Mepf state */
69 EVENT(PM_L3_CO_MEPF,				0x18082)
70 /* Alternate event code for PM_L3_CO_MEPF */
71 EVENT(PM_L3_CO_MEPF_ALT,			0x3e05e)
72 /* Data cache was reloaded from a location other than L2 due to a marked load */
73 EVENT(PM_MRK_DATA_FROM_L2MISS,			0x1d14e)
74 /* Alternate event code for PM_MRK_DATA_FROM_L2MISS */
75 EVENT(PM_MRK_DATA_FROM_L2MISS_ALT,		0x401e8)
76 /* Alternate event code for  PM_CMPLU_STALL */
77 EVENT(PM_CMPLU_STALL_ALT,			0x1e054)
78 /* Two path branch */
79 EVENT(PM_BR_2PATH,				0x20036)
80 /* Alternate event code for PM_BR_2PATH */
81 EVENT(PM_BR_2PATH_ALT,				0x40036)
82 /* # PPC Dispatched */
83 EVENT(PM_INST_DISP,				0x200f2)
84 /* Alternate event code for PM_INST_DISP */
85 EVENT(PM_INST_DISP_ALT,				0x300f2)
86 /* Marked filter Match */
87 EVENT(PM_MRK_FILT_MATCH,			0x2013c)
88 /* Alternate event code for PM_MRK_FILT_MATCH */
89 EVENT(PM_MRK_FILT_MATCH_ALT,			0x3012e)
90 /* Alternate event code for PM_LD_MISS_L1 */
91 EVENT(PM_LD_MISS_L1_ALT,			0x400f0)
92 /*
93  * Memory Access Event -- mem_access
94  * Primary PMU event used here is PM_MRK_INST_CMPL, along with
95  * Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]).
96  */
97 EVENT(MEM_ACCESS,				0x10401e0)
98