1 /* 2 * Performance counter support for POWER7 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/perf_event.h> 13 #include <linux/string.h> 14 #include <asm/reg.h> 15 #include <asm/cputable.h> 16 17 /* 18 * Bits in event code for POWER7 19 */ 20 #define PM_PMC_SH 16 /* PMC number (1-based) for direct events */ 21 #define PM_PMC_MSK 0xf 22 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) 23 #define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */ 24 #define PM_UNIT_MSK 0xf 25 #define PM_COMBINE_SH 11 /* Combined event bit */ 26 #define PM_COMBINE_MSK 1 27 #define PM_COMBINE_MSKS 0x800 28 #define PM_L2SEL_SH 8 /* L2 event select */ 29 #define PM_L2SEL_MSK 7 30 #define PM_PMCSEL_MSK 0xff 31 32 /* 33 * Bits in MMCR1 for POWER7 34 */ 35 #define MMCR1_TTM0SEL_SH 60 36 #define MMCR1_TTM1SEL_SH 56 37 #define MMCR1_TTM2SEL_SH 52 38 #define MMCR1_TTM3SEL_SH 48 39 #define MMCR1_TTMSEL_MSK 0xf 40 #define MMCR1_L2SEL_SH 45 41 #define MMCR1_L2SEL_MSK 7 42 #define MMCR1_PMC1_COMBINE_SH 35 43 #define MMCR1_PMC2_COMBINE_SH 34 44 #define MMCR1_PMC3_COMBINE_SH 33 45 #define MMCR1_PMC4_COMBINE_SH 32 46 #define MMCR1_PMC1SEL_SH 24 47 #define MMCR1_PMC2SEL_SH 16 48 #define MMCR1_PMC3SEL_SH 8 49 #define MMCR1_PMC4SEL_SH 0 50 #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) 51 #define MMCR1_PMCSEL_MSK 0xff 52 53 /* 54 * Layout of constraint bits: 55 * 6666555555555544444444443333333333222222222211111111110000000000 56 * 3210987654321098765432109876543210987654321098765432109876543210 57 * < >< ><><><><><><> 58 * L2 NC P6P5P4P3P2P1 59 * 60 * L2 - 16-18 - Required L2SEL value (select field) 61 * 62 * NC - number of counters 63 * 15: NC error 0x8000 64 * 12-14: number of events needing PMC1-4 0x7000 65 * 66 * P6 67 * 11: P6 error 0x800 68 * 10-11: Count of events needing PMC6 69 * 70 * P1..P5 71 * 0-9: Count of events needing PMC1..PMC5 72 */ 73 74 static int power7_get_constraint(u64 event, unsigned long *maskp, 75 unsigned long *valp) 76 { 77 int pmc, sh, unit; 78 unsigned long mask = 0, value = 0; 79 80 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 81 if (pmc) { 82 if (pmc > 6) 83 return -1; 84 sh = (pmc - 1) * 2; 85 mask |= 2 << sh; 86 value |= 1 << sh; 87 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4)) 88 return -1; 89 } 90 if (pmc < 5) { 91 /* need a counter from PMC1-4 set */ 92 mask |= 0x8000; 93 value |= 0x1000; 94 } 95 96 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; 97 if (unit == 6) { 98 /* L2SEL must be identical across events */ 99 int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK; 100 mask |= 0x7 << 16; 101 value |= l2sel << 16; 102 } 103 104 *maskp = mask; 105 *valp = value; 106 return 0; 107 } 108 109 #define MAX_ALT 2 /* at most 2 alternatives for any event */ 110 111 static const unsigned int event_alternatives[][MAX_ALT] = { 112 { 0x200f2, 0x300f2 }, /* PM_INST_DISP */ 113 { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */ 114 { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */ 115 }; 116 117 /* 118 * Scan the alternatives table for a match and return the 119 * index into the alternatives table if found, else -1. 120 */ 121 static int find_alternative(u64 event) 122 { 123 int i, j; 124 125 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { 126 if (event < event_alternatives[i][0]) 127 break; 128 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) 129 if (event == event_alternatives[i][j]) 130 return i; 131 } 132 return -1; 133 } 134 135 static s64 find_alternative_decode(u64 event) 136 { 137 int pmc, psel; 138 139 /* this only handles the 4x decode events */ 140 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 141 psel = event & PM_PMCSEL_MSK; 142 if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40) 143 return event - (1 << PM_PMC_SH) + 8; 144 if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48) 145 return event + (1 << PM_PMC_SH) - 8; 146 return -1; 147 } 148 149 static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 150 { 151 int i, j, nalt = 1; 152 s64 ae; 153 154 alt[0] = event; 155 nalt = 1; 156 i = find_alternative(event); 157 if (i >= 0) { 158 for (j = 0; j < MAX_ALT; ++j) { 159 ae = event_alternatives[i][j]; 160 if (ae && ae != event) 161 alt[nalt++] = ae; 162 } 163 } else { 164 ae = find_alternative_decode(event); 165 if (ae > 0) 166 alt[nalt++] = ae; 167 } 168 169 if (flags & PPMU_ONLY_COUNT_RUN) { 170 /* 171 * We're only counting in RUN state, 172 * so PM_CYC is equivalent to PM_RUN_CYC 173 * and PM_INST_CMPL === PM_RUN_INST_CMPL. 174 * This doesn't include alternatives that don't provide 175 * any extra flexibility in assigning PMCs. 176 */ 177 j = nalt; 178 for (i = 0; i < nalt; ++i) { 179 switch (alt[i]) { 180 case 0x1e: /* PM_CYC */ 181 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 182 break; 183 case 0x600f4: /* PM_RUN_CYC */ 184 alt[j++] = 0x1e; 185 break; 186 case 0x2: /* PM_PPC_CMPL */ 187 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 188 break; 189 case 0x500fa: /* PM_RUN_INST_CMPL */ 190 alt[j++] = 0x2; /* PM_PPC_CMPL */ 191 break; 192 } 193 } 194 nalt = j; 195 } 196 197 return nalt; 198 } 199 200 /* 201 * Returns 1 if event counts things relating to marked instructions 202 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. 203 */ 204 static int power7_marked_instr_event(u64 event) 205 { 206 int pmc, psel; 207 int unit; 208 209 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 210 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; 211 psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */ 212 if (pmc >= 5) 213 return 0; 214 215 switch (psel >> 4) { 216 case 2: 217 return pmc == 2 || pmc == 4; 218 case 3: 219 if (psel == 0x3c) 220 return pmc == 1; 221 if (psel == 0x3e) 222 return pmc != 2; 223 return 1; 224 case 4: 225 case 5: 226 return unit == 0xd; 227 case 6: 228 if (psel == 0x64) 229 return pmc >= 3; 230 case 8: 231 return unit == 0xd; 232 } 233 return 0; 234 } 235 236 static int power7_compute_mmcr(u64 event[], int n_ev, 237 unsigned int hwc[], unsigned long mmcr[]) 238 { 239 unsigned long mmcr1 = 0; 240 unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS; 241 unsigned int pmc, unit, combine, l2sel, psel; 242 unsigned int pmc_inuse = 0; 243 int i; 244 245 /* First pass to count resource use */ 246 for (i = 0; i < n_ev; ++i) { 247 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; 248 if (pmc) { 249 if (pmc > 6) 250 return -1; 251 if (pmc_inuse & (1 << (pmc - 1))) 252 return -1; 253 pmc_inuse |= 1 << (pmc - 1); 254 } 255 } 256 257 /* Second pass: assign PMCs, set all MMCR1 fields */ 258 for (i = 0; i < n_ev; ++i) { 259 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; 260 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; 261 combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK; 262 l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK; 263 psel = event[i] & PM_PMCSEL_MSK; 264 if (!pmc) { 265 /* Bus event or any-PMC direct event */ 266 for (pmc = 0; pmc < 4; ++pmc) { 267 if (!(pmc_inuse & (1 << pmc))) 268 break; 269 } 270 if (pmc >= 4) 271 return -1; 272 pmc_inuse |= 1 << pmc; 273 } else { 274 /* Direct or decoded event */ 275 --pmc; 276 } 277 if (pmc <= 3) { 278 mmcr1 |= (unsigned long) unit 279 << (MMCR1_TTM0SEL_SH - 4 * pmc); 280 mmcr1 |= (unsigned long) combine 281 << (MMCR1_PMC1_COMBINE_SH - pmc); 282 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); 283 if (unit == 6) /* L2 events */ 284 mmcr1 |= (unsigned long) l2sel 285 << MMCR1_L2SEL_SH; 286 } 287 if (power7_marked_instr_event(event[i])) 288 mmcra |= MMCRA_SAMPLE_ENABLE; 289 hwc[i] = pmc; 290 } 291 292 /* Return MMCRx values */ 293 mmcr[0] = 0; 294 if (pmc_inuse & 1) 295 mmcr[0] = MMCR0_PMC1CE; 296 if (pmc_inuse & 0x3e) 297 mmcr[0] |= MMCR0_PMCjCE; 298 mmcr[1] = mmcr1; 299 mmcr[2] = mmcra; 300 return 0; 301 } 302 303 static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 304 { 305 if (pmc <= 3) 306 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); 307 } 308 309 static int power7_generic_events[] = { 310 [PERF_COUNT_HW_CPU_CYCLES] = 0x1e, 311 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 0x100f8, /* GCT_NOSLOT_CYC */ 312 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 0x4000a, /* CMPLU_STALL */ 313 [PERF_COUNT_HW_INSTRUCTIONS] = 2, 314 [PERF_COUNT_HW_CACHE_REFERENCES] = 0xc880, /* LD_REF_L1_LSU*/ 315 [PERF_COUNT_HW_CACHE_MISSES] = 0x400f0, /* LD_MISS_L1 */ 316 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x10068, /* BRU_FIN */ 317 [PERF_COUNT_HW_BRANCH_MISSES] = 0x400f6, /* BR_MPRED */ 318 }; 319 320 #define C(x) PERF_COUNT_HW_CACHE_##x 321 322 /* 323 * Table of generalized cache-related events. 324 * 0 means not supported, -1 means nonsensical, other values 325 * are event codes. 326 */ 327 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 328 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ 329 [C(OP_READ)] = { 0xc880, 0x400f0 }, 330 [C(OP_WRITE)] = { 0, 0x300f0 }, 331 [C(OP_PREFETCH)] = { 0xd8b8, 0 }, 332 }, 333 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ 334 [C(OP_READ)] = { 0, 0x200fc }, 335 [C(OP_WRITE)] = { -1, -1 }, 336 [C(OP_PREFETCH)] = { 0x408a, 0 }, 337 }, 338 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ 339 [C(OP_READ)] = { 0x16080, 0x26080 }, 340 [C(OP_WRITE)] = { 0x16082, 0x26082 }, 341 [C(OP_PREFETCH)] = { 0, 0 }, 342 }, 343 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ 344 [C(OP_READ)] = { 0, 0x300fc }, 345 [C(OP_WRITE)] = { -1, -1 }, 346 [C(OP_PREFETCH)] = { -1, -1 }, 347 }, 348 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ 349 [C(OP_READ)] = { 0, 0x400fc }, 350 [C(OP_WRITE)] = { -1, -1 }, 351 [C(OP_PREFETCH)] = { -1, -1 }, 352 }, 353 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ 354 [C(OP_READ)] = { 0x10068, 0x400f6 }, 355 [C(OP_WRITE)] = { -1, -1 }, 356 [C(OP_PREFETCH)] = { -1, -1 }, 357 }, 358 [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ 359 [C(OP_READ)] = { -1, -1 }, 360 [C(OP_WRITE)] = { -1, -1 }, 361 [C(OP_PREFETCH)] = { -1, -1 }, 362 }, 363 }; 364 365 static struct power_pmu power7_pmu = { 366 .name = "POWER7", 367 .n_counter = 6, 368 .max_alternatives = MAX_ALT + 1, 369 .add_fields = 0x1555ul, 370 .test_adder = 0x3000ul, 371 .compute_mmcr = power7_compute_mmcr, 372 .get_constraint = power7_get_constraint, 373 .get_alternatives = power7_get_alternatives, 374 .disable_pmc = power7_disable_pmc, 375 .flags = PPMU_ALT_SIPR, 376 .n_generic = ARRAY_SIZE(power7_generic_events), 377 .generic_events = power7_generic_events, 378 .cache_events = &power7_cache_events, 379 }; 380 381 static int __init init_power7_pmu(void) 382 { 383 if (!cur_cpu_spec->oprofile_cpu_type || 384 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) 385 return -ENODEV; 386 387 if (pvr_version_is(PVR_POWER7p)) 388 power7_pmu.flags |= PPMU_SIAR_VALID; 389 390 return register_power_pmu(&power7_pmu); 391 } 392 393 early_initcall(init_power7_pmu); 394