1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance counter support for POWER7 processors. 4 * 5 * Copyright 2009 Paul Mackerras, IBM Corporation. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/perf_event.h> 9 #include <linux/string.h> 10 #include <asm/reg.h> 11 #include <asm/cputable.h> 12 13 /* 14 * Bits in event code for POWER7 15 */ 16 #define PM_PMC_SH 16 /* PMC number (1-based) for direct events */ 17 #define PM_PMC_MSK 0xf 18 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) 19 #define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */ 20 #define PM_UNIT_MSK 0xf 21 #define PM_COMBINE_SH 11 /* Combined event bit */ 22 #define PM_COMBINE_MSK 1 23 #define PM_COMBINE_MSKS 0x800 24 #define PM_L2SEL_SH 8 /* L2 event select */ 25 #define PM_L2SEL_MSK 7 26 #define PM_PMCSEL_MSK 0xff 27 28 /* 29 * Bits in MMCR1 for POWER7 30 */ 31 #define MMCR1_TTM0SEL_SH 60 32 #define MMCR1_TTM1SEL_SH 56 33 #define MMCR1_TTM2SEL_SH 52 34 #define MMCR1_TTM3SEL_SH 48 35 #define MMCR1_TTMSEL_MSK 0xf 36 #define MMCR1_L2SEL_SH 45 37 #define MMCR1_L2SEL_MSK 7 38 #define MMCR1_PMC1_COMBINE_SH 35 39 #define MMCR1_PMC2_COMBINE_SH 34 40 #define MMCR1_PMC3_COMBINE_SH 33 41 #define MMCR1_PMC4_COMBINE_SH 32 42 #define MMCR1_PMC1SEL_SH 24 43 #define MMCR1_PMC2SEL_SH 16 44 #define MMCR1_PMC3SEL_SH 8 45 #define MMCR1_PMC4SEL_SH 0 46 #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) 47 #define MMCR1_PMCSEL_MSK 0xff 48 49 /* 50 * Power7 event codes. 51 */ 52 #define EVENT(_name, _code) \ 53 _name = _code, 54 55 enum { 56 #include "power7-events-list.h" 57 }; 58 #undef EVENT 59 60 /* 61 * Layout of constraint bits: 62 * 6666555555555544444444443333333333222222222211111111110000000000 63 * 3210987654321098765432109876543210987654321098765432109876543210 64 * < >< ><><><><><><> 65 * L2 NC P6P5P4P3P2P1 66 * 67 * L2 - 16-18 - Required L2SEL value (select field) 68 * 69 * NC - number of counters 70 * 15: NC error 0x8000 71 * 12-14: number of events needing PMC1-4 0x7000 72 * 73 * P6 74 * 11: P6 error 0x800 75 * 10-11: Count of events needing PMC6 76 * 77 * P1..P5 78 * 0-9: Count of events needing PMC1..PMC5 79 */ 80 81 static int power7_get_constraint(u64 event, unsigned long *maskp, 82 unsigned long *valp) 83 { 84 int pmc, sh, unit; 85 unsigned long mask = 0, value = 0; 86 87 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 88 if (pmc) { 89 if (pmc > 6) 90 return -1; 91 sh = (pmc - 1) * 2; 92 mask |= 2 << sh; 93 value |= 1 << sh; 94 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4)) 95 return -1; 96 } 97 if (pmc < 5) { 98 /* need a counter from PMC1-4 set */ 99 mask |= 0x8000; 100 value |= 0x1000; 101 } 102 103 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; 104 if (unit == 6) { 105 /* L2SEL must be identical across events */ 106 int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK; 107 mask |= 0x7 << 16; 108 value |= l2sel << 16; 109 } 110 111 *maskp = mask; 112 *valp = value; 113 return 0; 114 } 115 116 #define MAX_ALT 2 /* at most 2 alternatives for any event */ 117 118 static const unsigned int event_alternatives[][MAX_ALT] = { 119 { 0x200f2, 0x300f2 }, /* PM_INST_DISP */ 120 { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */ 121 { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */ 122 }; 123 124 /* 125 * Scan the alternatives table for a match and return the 126 * index into the alternatives table if found, else -1. 127 */ 128 static int find_alternative(u64 event) 129 { 130 int i, j; 131 132 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { 133 if (event < event_alternatives[i][0]) 134 break; 135 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) 136 if (event == event_alternatives[i][j]) 137 return i; 138 } 139 return -1; 140 } 141 142 static s64 find_alternative_decode(u64 event) 143 { 144 int pmc, psel; 145 146 /* this only handles the 4x decode events */ 147 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 148 psel = event & PM_PMCSEL_MSK; 149 if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40) 150 return event - (1 << PM_PMC_SH) + 8; 151 if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48) 152 return event + (1 << PM_PMC_SH) - 8; 153 return -1; 154 } 155 156 static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 157 { 158 int i, j, nalt = 1; 159 s64 ae; 160 161 alt[0] = event; 162 nalt = 1; 163 i = find_alternative(event); 164 if (i >= 0) { 165 for (j = 0; j < MAX_ALT; ++j) { 166 ae = event_alternatives[i][j]; 167 if (ae && ae != event) 168 alt[nalt++] = ae; 169 } 170 } else { 171 ae = find_alternative_decode(event); 172 if (ae > 0) 173 alt[nalt++] = ae; 174 } 175 176 if (flags & PPMU_ONLY_COUNT_RUN) { 177 /* 178 * We're only counting in RUN state, 179 * so PM_CYC is equivalent to PM_RUN_CYC 180 * and PM_INST_CMPL === PM_RUN_INST_CMPL. 181 * This doesn't include alternatives that don't provide 182 * any extra flexibility in assigning PMCs. 183 */ 184 j = nalt; 185 for (i = 0; i < nalt; ++i) { 186 switch (alt[i]) { 187 case 0x1e: /* PM_CYC */ 188 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 189 break; 190 case 0x600f4: /* PM_RUN_CYC */ 191 alt[j++] = 0x1e; 192 break; 193 case 0x2: /* PM_PPC_CMPL */ 194 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 195 break; 196 case 0x500fa: /* PM_RUN_INST_CMPL */ 197 alt[j++] = 0x2; /* PM_PPC_CMPL */ 198 break; 199 } 200 } 201 nalt = j; 202 } 203 204 return nalt; 205 } 206 207 /* 208 * Returns 1 if event counts things relating to marked instructions 209 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. 210 */ 211 static int power7_marked_instr_event(u64 event) 212 { 213 int pmc, psel; 214 int unit; 215 216 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 217 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; 218 psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */ 219 if (pmc >= 5) 220 return 0; 221 222 switch (psel >> 4) { 223 case 2: 224 return pmc == 2 || pmc == 4; 225 case 3: 226 if (psel == 0x3c) 227 return pmc == 1; 228 if (psel == 0x3e) 229 return pmc != 2; 230 return 1; 231 case 4: 232 case 5: 233 return unit == 0xd; 234 case 6: 235 if (psel == 0x64) 236 return pmc >= 3; 237 break; 238 case 8: 239 return unit == 0xd; 240 } 241 return 0; 242 } 243 244 static int power7_compute_mmcr(u64 event[], int n_ev, 245 unsigned int hwc[], unsigned long mmcr[], struct perf_event *pevents[]) 246 { 247 unsigned long mmcr1 = 0; 248 unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS; 249 unsigned int pmc, unit, combine, l2sel, psel; 250 unsigned int pmc_inuse = 0; 251 int i; 252 253 /* First pass to count resource use */ 254 for (i = 0; i < n_ev; ++i) { 255 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; 256 if (pmc) { 257 if (pmc > 6) 258 return -1; 259 if (pmc_inuse & (1 << (pmc - 1))) 260 return -1; 261 pmc_inuse |= 1 << (pmc - 1); 262 } 263 } 264 265 /* Second pass: assign PMCs, set all MMCR1 fields */ 266 for (i = 0; i < n_ev; ++i) { 267 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; 268 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; 269 combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK; 270 l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK; 271 psel = event[i] & PM_PMCSEL_MSK; 272 if (!pmc) { 273 /* Bus event or any-PMC direct event */ 274 for (pmc = 0; pmc < 4; ++pmc) { 275 if (!(pmc_inuse & (1 << pmc))) 276 break; 277 } 278 if (pmc >= 4) 279 return -1; 280 pmc_inuse |= 1 << pmc; 281 } else { 282 /* Direct or decoded event */ 283 --pmc; 284 } 285 if (pmc <= 3) { 286 mmcr1 |= (unsigned long) unit 287 << (MMCR1_TTM0SEL_SH - 4 * pmc); 288 mmcr1 |= (unsigned long) combine 289 << (MMCR1_PMC1_COMBINE_SH - pmc); 290 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); 291 if (unit == 6) /* L2 events */ 292 mmcr1 |= (unsigned long) l2sel 293 << MMCR1_L2SEL_SH; 294 } 295 if (power7_marked_instr_event(event[i])) 296 mmcra |= MMCRA_SAMPLE_ENABLE; 297 hwc[i] = pmc; 298 } 299 300 /* Return MMCRx values */ 301 mmcr[0] = 0; 302 if (pmc_inuse & 1) 303 mmcr[0] = MMCR0_PMC1CE; 304 if (pmc_inuse & 0x3e) 305 mmcr[0] |= MMCR0_PMCjCE; 306 mmcr[1] = mmcr1; 307 mmcr[2] = mmcra; 308 return 0; 309 } 310 311 static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 312 { 313 if (pmc <= 3) 314 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); 315 } 316 317 static int power7_generic_events[] = { 318 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 319 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC, 320 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL, 321 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL, 322 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 323 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 324 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN, 325 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED, 326 }; 327 328 #define C(x) PERF_COUNT_HW_CACHE_##x 329 330 /* 331 * Table of generalized cache-related events. 332 * 0 means not supported, -1 means nonsensical, other values 333 * are event codes. 334 */ 335 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 336 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ 337 [C(OP_READ)] = { 0xc880, 0x400f0 }, 338 [C(OP_WRITE)] = { 0, 0x300f0 }, 339 [C(OP_PREFETCH)] = { 0xd8b8, 0 }, 340 }, 341 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ 342 [C(OP_READ)] = { 0, 0x200fc }, 343 [C(OP_WRITE)] = { -1, -1 }, 344 [C(OP_PREFETCH)] = { 0x408a, 0 }, 345 }, 346 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ 347 [C(OP_READ)] = { 0x16080, 0x26080 }, 348 [C(OP_WRITE)] = { 0x16082, 0x26082 }, 349 [C(OP_PREFETCH)] = { 0, 0 }, 350 }, 351 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ 352 [C(OP_READ)] = { 0, 0x300fc }, 353 [C(OP_WRITE)] = { -1, -1 }, 354 [C(OP_PREFETCH)] = { -1, -1 }, 355 }, 356 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ 357 [C(OP_READ)] = { 0, 0x400fc }, 358 [C(OP_WRITE)] = { -1, -1 }, 359 [C(OP_PREFETCH)] = { -1, -1 }, 360 }, 361 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ 362 [C(OP_READ)] = { 0x10068, 0x400f6 }, 363 [C(OP_WRITE)] = { -1, -1 }, 364 [C(OP_PREFETCH)] = { -1, -1 }, 365 }, 366 [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ 367 [C(OP_READ)] = { -1, -1 }, 368 [C(OP_WRITE)] = { -1, -1 }, 369 [C(OP_PREFETCH)] = { -1, -1 }, 370 }, 371 }; 372 373 374 GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC); 375 GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC); 376 GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL); 377 GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL); 378 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 379 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); 380 GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN); 381 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED); 382 383 #define EVENT(_name, _code) POWER_EVENT_ATTR(_name, _name); 384 #include "power7-events-list.h" 385 #undef EVENT 386 387 #define EVENT(_name, _code) POWER_EVENT_PTR(_name), 388 389 static struct attribute *power7_events_attr[] = { 390 GENERIC_EVENT_PTR(PM_CYC), 391 GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC), 392 GENERIC_EVENT_PTR(PM_CMPLU_STALL), 393 GENERIC_EVENT_PTR(PM_INST_CMPL), 394 GENERIC_EVENT_PTR(PM_LD_REF_L1), 395 GENERIC_EVENT_PTR(PM_LD_MISS_L1), 396 GENERIC_EVENT_PTR(PM_BRU_FIN), 397 GENERIC_EVENT_PTR(PM_BR_MPRED), 398 399 #include "power7-events-list.h" 400 #undef EVENT 401 NULL 402 }; 403 404 static struct attribute_group power7_pmu_events_group = { 405 .name = "events", 406 .attrs = power7_events_attr, 407 }; 408 409 PMU_FORMAT_ATTR(event, "config:0-19"); 410 411 static struct attribute *power7_pmu_format_attr[] = { 412 &format_attr_event.attr, 413 NULL, 414 }; 415 416 static struct attribute_group power7_pmu_format_group = { 417 .name = "format", 418 .attrs = power7_pmu_format_attr, 419 }; 420 421 static const struct attribute_group *power7_pmu_attr_groups[] = { 422 &power7_pmu_format_group, 423 &power7_pmu_events_group, 424 NULL, 425 }; 426 427 static struct power_pmu power7_pmu = { 428 .name = "POWER7", 429 .n_counter = 6, 430 .max_alternatives = MAX_ALT + 1, 431 .add_fields = 0x1555ul, 432 .test_adder = 0x3000ul, 433 .compute_mmcr = power7_compute_mmcr, 434 .get_constraint = power7_get_constraint, 435 .get_alternatives = power7_get_alternatives, 436 .disable_pmc = power7_disable_pmc, 437 .flags = PPMU_ALT_SIPR, 438 .attr_groups = power7_pmu_attr_groups, 439 .n_generic = ARRAY_SIZE(power7_generic_events), 440 .generic_events = power7_generic_events, 441 .cache_events = &power7_cache_events, 442 }; 443 444 int init_power7_pmu(void) 445 { 446 if (!cur_cpu_spec->oprofile_cpu_type || 447 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) 448 return -ENODEV; 449 450 if (pvr_version_is(PVR_POWER7p)) 451 power7_pmu.flags |= PPMU_SIAR_VALID; 452 453 return register_power_pmu(&power7_pmu); 454 } 455