1 /* 2 * Performance counter support for POWER7 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 #include <linux/kernel.h> 12 #include <linux/perf_event.h> 13 #include <linux/string.h> 14 #include <asm/reg.h> 15 #include <asm/cputable.h> 16 17 /* 18 * Bits in event code for POWER7 19 */ 20 #define PM_PMC_SH 16 /* PMC number (1-based) for direct events */ 21 #define PM_PMC_MSK 0xf 22 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH) 23 #define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */ 24 #define PM_UNIT_MSK 0xf 25 #define PM_COMBINE_SH 11 /* Combined event bit */ 26 #define PM_COMBINE_MSK 1 27 #define PM_COMBINE_MSKS 0x800 28 #define PM_L2SEL_SH 8 /* L2 event select */ 29 #define PM_L2SEL_MSK 7 30 #define PM_PMCSEL_MSK 0xff 31 32 /* 33 * Bits in MMCR1 for POWER7 34 */ 35 #define MMCR1_TTM0SEL_SH 60 36 #define MMCR1_TTM1SEL_SH 56 37 #define MMCR1_TTM2SEL_SH 52 38 #define MMCR1_TTM3SEL_SH 48 39 #define MMCR1_TTMSEL_MSK 0xf 40 #define MMCR1_L2SEL_SH 45 41 #define MMCR1_L2SEL_MSK 7 42 #define MMCR1_PMC1_COMBINE_SH 35 43 #define MMCR1_PMC2_COMBINE_SH 34 44 #define MMCR1_PMC3_COMBINE_SH 33 45 #define MMCR1_PMC4_COMBINE_SH 32 46 #define MMCR1_PMC1SEL_SH 24 47 #define MMCR1_PMC2SEL_SH 16 48 #define MMCR1_PMC3SEL_SH 8 49 #define MMCR1_PMC4SEL_SH 0 50 #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) 51 #define MMCR1_PMCSEL_MSK 0xff 52 53 /* 54 * Power7 event codes. 55 */ 56 #define PME_PM_CYC 0x1e 57 #define PME_PM_GCT_NOSLOT_CYC 0x100f8 58 #define PME_PM_CMPLU_STALL 0x4000a 59 #define PME_PM_INST_CMPL 0x2 60 #define PME_PM_LD_REF_L1 0xc880 61 #define PME_PM_LD_MISS_L1 0x400f0 62 #define PME_PM_BRU_FIN 0x10068 63 #define PME_PM_BR_MPRED 0x400f6 64 65 #define PME_PM_CMPLU_STALL_FXU 0x20014 66 #define PME_PM_CMPLU_STALL_DIV 0x40014 67 #define PME_PM_CMPLU_STALL_SCALAR 0x40012 68 #define PME_PM_CMPLU_STALL_SCALAR_LONG 0x20018 69 #define PME_PM_CMPLU_STALL_VECTOR 0x2001c 70 #define PME_PM_CMPLU_STALL_VECTOR_LONG 0x4004a 71 #define PME_PM_CMPLU_STALL_LSU 0x20012 72 #define PME_PM_CMPLU_STALL_REJECT 0x40016 73 #define PME_PM_CMPLU_STALL_ERAT_MISS 0x40018 74 #define PME_PM_CMPLU_STALL_DCACHE_MISS 0x20016 75 #define PME_PM_CMPLU_STALL_STORE 0x2004a 76 #define PME_PM_CMPLU_STALL_THRD 0x1001c 77 #define PME_PM_CMPLU_STALL_IFU 0x4004c 78 #define PME_PM_CMPLU_STALL_BRU 0x4004e 79 #define PME_PM_GCT_NOSLOT_IC_MISS 0x2001a 80 #define PME_PM_GCT_NOSLOT_BR_MPRED 0x4001a 81 #define PME_PM_GCT_NOSLOT_BR_MPRED_IC_MISS 0x4001c 82 #define PME_PM_GRP_CMPL 0x30004 83 #define PME_PM_1PLUS_PPC_CMPL 0x100f2 84 #define PME_PM_CMPLU_STALL_DFU 0x2003c 85 #define PME_PM_RUN_CYC 0x200f4 86 #define PME_PM_RUN_INST_CMPL 0x400fa 87 88 /* 89 * Layout of constraint bits: 90 * 6666555555555544444444443333333333222222222211111111110000000000 91 * 3210987654321098765432109876543210987654321098765432109876543210 92 * < >< ><><><><><><> 93 * L2 NC P6P5P4P3P2P1 94 * 95 * L2 - 16-18 - Required L2SEL value (select field) 96 * 97 * NC - number of counters 98 * 15: NC error 0x8000 99 * 12-14: number of events needing PMC1-4 0x7000 100 * 101 * P6 102 * 11: P6 error 0x800 103 * 10-11: Count of events needing PMC6 104 * 105 * P1..P5 106 * 0-9: Count of events needing PMC1..PMC5 107 */ 108 109 static int power7_get_constraint(u64 event, unsigned long *maskp, 110 unsigned long *valp) 111 { 112 int pmc, sh, unit; 113 unsigned long mask = 0, value = 0; 114 115 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 116 if (pmc) { 117 if (pmc > 6) 118 return -1; 119 sh = (pmc - 1) * 2; 120 mask |= 2 << sh; 121 value |= 1 << sh; 122 if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4)) 123 return -1; 124 } 125 if (pmc < 5) { 126 /* need a counter from PMC1-4 set */ 127 mask |= 0x8000; 128 value |= 0x1000; 129 } 130 131 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; 132 if (unit == 6) { 133 /* L2SEL must be identical across events */ 134 int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK; 135 mask |= 0x7 << 16; 136 value |= l2sel << 16; 137 } 138 139 *maskp = mask; 140 *valp = value; 141 return 0; 142 } 143 144 #define MAX_ALT 2 /* at most 2 alternatives for any event */ 145 146 static const unsigned int event_alternatives[][MAX_ALT] = { 147 { 0x200f2, 0x300f2 }, /* PM_INST_DISP */ 148 { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */ 149 { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */ 150 }; 151 152 /* 153 * Scan the alternatives table for a match and return the 154 * index into the alternatives table if found, else -1. 155 */ 156 static int find_alternative(u64 event) 157 { 158 int i, j; 159 160 for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) { 161 if (event < event_alternatives[i][0]) 162 break; 163 for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j) 164 if (event == event_alternatives[i][j]) 165 return i; 166 } 167 return -1; 168 } 169 170 static s64 find_alternative_decode(u64 event) 171 { 172 int pmc, psel; 173 174 /* this only handles the 4x decode events */ 175 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 176 psel = event & PM_PMCSEL_MSK; 177 if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40) 178 return event - (1 << PM_PMC_SH) + 8; 179 if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48) 180 return event + (1 << PM_PMC_SH) - 8; 181 return -1; 182 } 183 184 static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 185 { 186 int i, j, nalt = 1; 187 s64 ae; 188 189 alt[0] = event; 190 nalt = 1; 191 i = find_alternative(event); 192 if (i >= 0) { 193 for (j = 0; j < MAX_ALT; ++j) { 194 ae = event_alternatives[i][j]; 195 if (ae && ae != event) 196 alt[nalt++] = ae; 197 } 198 } else { 199 ae = find_alternative_decode(event); 200 if (ae > 0) 201 alt[nalt++] = ae; 202 } 203 204 if (flags & PPMU_ONLY_COUNT_RUN) { 205 /* 206 * We're only counting in RUN state, 207 * so PM_CYC is equivalent to PM_RUN_CYC 208 * and PM_INST_CMPL === PM_RUN_INST_CMPL. 209 * This doesn't include alternatives that don't provide 210 * any extra flexibility in assigning PMCs. 211 */ 212 j = nalt; 213 for (i = 0; i < nalt; ++i) { 214 switch (alt[i]) { 215 case 0x1e: /* PM_CYC */ 216 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 217 break; 218 case 0x600f4: /* PM_RUN_CYC */ 219 alt[j++] = 0x1e; 220 break; 221 case 0x2: /* PM_PPC_CMPL */ 222 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 223 break; 224 case 0x500fa: /* PM_RUN_INST_CMPL */ 225 alt[j++] = 0x2; /* PM_PPC_CMPL */ 226 break; 227 } 228 } 229 nalt = j; 230 } 231 232 return nalt; 233 } 234 235 /* 236 * Returns 1 if event counts things relating to marked instructions 237 * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not. 238 */ 239 static int power7_marked_instr_event(u64 event) 240 { 241 int pmc, psel; 242 int unit; 243 244 pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; 245 unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK; 246 psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */ 247 if (pmc >= 5) 248 return 0; 249 250 switch (psel >> 4) { 251 case 2: 252 return pmc == 2 || pmc == 4; 253 case 3: 254 if (psel == 0x3c) 255 return pmc == 1; 256 if (psel == 0x3e) 257 return pmc != 2; 258 return 1; 259 case 4: 260 case 5: 261 return unit == 0xd; 262 case 6: 263 if (psel == 0x64) 264 return pmc >= 3; 265 case 8: 266 return unit == 0xd; 267 } 268 return 0; 269 } 270 271 static int power7_compute_mmcr(u64 event[], int n_ev, 272 unsigned int hwc[], unsigned long mmcr[]) 273 { 274 unsigned long mmcr1 = 0; 275 unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS; 276 unsigned int pmc, unit, combine, l2sel, psel; 277 unsigned int pmc_inuse = 0; 278 int i; 279 280 /* First pass to count resource use */ 281 for (i = 0; i < n_ev; ++i) { 282 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; 283 if (pmc) { 284 if (pmc > 6) 285 return -1; 286 if (pmc_inuse & (1 << (pmc - 1))) 287 return -1; 288 pmc_inuse |= 1 << (pmc - 1); 289 } 290 } 291 292 /* Second pass: assign PMCs, set all MMCR1 fields */ 293 for (i = 0; i < n_ev; ++i) { 294 pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK; 295 unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK; 296 combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK; 297 l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK; 298 psel = event[i] & PM_PMCSEL_MSK; 299 if (!pmc) { 300 /* Bus event or any-PMC direct event */ 301 for (pmc = 0; pmc < 4; ++pmc) { 302 if (!(pmc_inuse & (1 << pmc))) 303 break; 304 } 305 if (pmc >= 4) 306 return -1; 307 pmc_inuse |= 1 << pmc; 308 } else { 309 /* Direct or decoded event */ 310 --pmc; 311 } 312 if (pmc <= 3) { 313 mmcr1 |= (unsigned long) unit 314 << (MMCR1_TTM0SEL_SH - 4 * pmc); 315 mmcr1 |= (unsigned long) combine 316 << (MMCR1_PMC1_COMBINE_SH - pmc); 317 mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); 318 if (unit == 6) /* L2 events */ 319 mmcr1 |= (unsigned long) l2sel 320 << MMCR1_L2SEL_SH; 321 } 322 if (power7_marked_instr_event(event[i])) 323 mmcra |= MMCRA_SAMPLE_ENABLE; 324 hwc[i] = pmc; 325 } 326 327 /* Return MMCRx values */ 328 mmcr[0] = 0; 329 if (pmc_inuse & 1) 330 mmcr[0] = MMCR0_PMC1CE; 331 if (pmc_inuse & 0x3e) 332 mmcr[0] |= MMCR0_PMCjCE; 333 mmcr[1] = mmcr1; 334 mmcr[2] = mmcra; 335 return 0; 336 } 337 338 static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 339 { 340 if (pmc <= 3) 341 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc)); 342 } 343 344 static int power7_generic_events[] = { 345 [PERF_COUNT_HW_CPU_CYCLES] = PME_PM_CYC, 346 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PME_PM_GCT_NOSLOT_CYC, 347 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PME_PM_CMPLU_STALL, 348 [PERF_COUNT_HW_INSTRUCTIONS] = PME_PM_INST_CMPL, 349 [PERF_COUNT_HW_CACHE_REFERENCES] = PME_PM_LD_REF_L1, 350 [PERF_COUNT_HW_CACHE_MISSES] = PME_PM_LD_MISS_L1, 351 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PME_PM_BRU_FIN, 352 [PERF_COUNT_HW_BRANCH_MISSES] = PME_PM_BR_MPRED, 353 }; 354 355 #define C(x) PERF_COUNT_HW_CACHE_##x 356 357 /* 358 * Table of generalized cache-related events. 359 * 0 means not supported, -1 means nonsensical, other values 360 * are event codes. 361 */ 362 static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 363 [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */ 364 [C(OP_READ)] = { 0xc880, 0x400f0 }, 365 [C(OP_WRITE)] = { 0, 0x300f0 }, 366 [C(OP_PREFETCH)] = { 0xd8b8, 0 }, 367 }, 368 [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */ 369 [C(OP_READ)] = { 0, 0x200fc }, 370 [C(OP_WRITE)] = { -1, -1 }, 371 [C(OP_PREFETCH)] = { 0x408a, 0 }, 372 }, 373 [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */ 374 [C(OP_READ)] = { 0x16080, 0x26080 }, 375 [C(OP_WRITE)] = { 0x16082, 0x26082 }, 376 [C(OP_PREFETCH)] = { 0, 0 }, 377 }, 378 [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */ 379 [C(OP_READ)] = { 0, 0x300fc }, 380 [C(OP_WRITE)] = { -1, -1 }, 381 [C(OP_PREFETCH)] = { -1, -1 }, 382 }, 383 [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */ 384 [C(OP_READ)] = { 0, 0x400fc }, 385 [C(OP_WRITE)] = { -1, -1 }, 386 [C(OP_PREFETCH)] = { -1, -1 }, 387 }, 388 [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */ 389 [C(OP_READ)] = { 0x10068, 0x400f6 }, 390 [C(OP_WRITE)] = { -1, -1 }, 391 [C(OP_PREFETCH)] = { -1, -1 }, 392 }, 393 [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */ 394 [C(OP_READ)] = { -1, -1 }, 395 [C(OP_WRITE)] = { -1, -1 }, 396 [C(OP_PREFETCH)] = { -1, -1 }, 397 }, 398 }; 399 400 401 GENERIC_EVENT_ATTR(cpu-cycles, CYC); 402 GENERIC_EVENT_ATTR(stalled-cycles-frontend, GCT_NOSLOT_CYC); 403 GENERIC_EVENT_ATTR(stalled-cycles-backend, CMPLU_STALL); 404 GENERIC_EVENT_ATTR(instructions, INST_CMPL); 405 GENERIC_EVENT_ATTR(cache-references, LD_REF_L1); 406 GENERIC_EVENT_ATTR(cache-misses, LD_MISS_L1); 407 GENERIC_EVENT_ATTR(branch-instructions, BRU_FIN); 408 GENERIC_EVENT_ATTR(branch-misses, BR_MPRED); 409 410 POWER_EVENT_ATTR(CYC, CYC); 411 POWER_EVENT_ATTR(GCT_NOSLOT_CYC, GCT_NOSLOT_CYC); 412 POWER_EVENT_ATTR(CMPLU_STALL, CMPLU_STALL); 413 POWER_EVENT_ATTR(INST_CMPL, INST_CMPL); 414 POWER_EVENT_ATTR(LD_REF_L1, LD_REF_L1); 415 POWER_EVENT_ATTR(LD_MISS_L1, LD_MISS_L1); 416 POWER_EVENT_ATTR(BRU_FIN, BRU_FIN) 417 POWER_EVENT_ATTR(BR_MPRED, BR_MPRED); 418 419 POWER_EVENT_ATTR(CMPLU_STALL_FXU, CMPLU_STALL_FXU); 420 POWER_EVENT_ATTR(CMPLU_STALL_DIV, CMPLU_STALL_DIV); 421 POWER_EVENT_ATTR(CMPLU_STALL_SCALAR, CMPLU_STALL_SCALAR); 422 POWER_EVENT_ATTR(CMPLU_STALL_SCALAR_LONG, CMPLU_STALL_SCALAR_LONG); 423 POWER_EVENT_ATTR(CMPLU_STALL_VECTOR, CMPLU_STALL_VECTOR); 424 POWER_EVENT_ATTR(CMPLU_STALL_VECTOR_LONG, CMPLU_STALL_VECTOR_LONG); 425 POWER_EVENT_ATTR(CMPLU_STALL_LSU, CMPLU_STALL_LSU); 426 POWER_EVENT_ATTR(CMPLU_STALL_REJECT, CMPLU_STALL_REJECT); 427 428 POWER_EVENT_ATTR(CMPLU_STALL_ERAT_MISS, CMPLU_STALL_ERAT_MISS); 429 POWER_EVENT_ATTR(CMPLU_STALL_DCACHE_MISS, CMPLU_STALL_DCACHE_MISS); 430 POWER_EVENT_ATTR(CMPLU_STALL_STORE, CMPLU_STALL_STORE); 431 POWER_EVENT_ATTR(CMPLU_STALL_THRD, CMPLU_STALL_THRD); 432 POWER_EVENT_ATTR(CMPLU_STALL_IFU, CMPLU_STALL_IFU); 433 POWER_EVENT_ATTR(CMPLU_STALL_BRU, CMPLU_STALL_BRU); 434 POWER_EVENT_ATTR(GCT_NOSLOT_IC_MISS, GCT_NOSLOT_IC_MISS); 435 436 POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED, GCT_NOSLOT_BR_MPRED); 437 POWER_EVENT_ATTR(GCT_NOSLOT_BR_MPRED_IC_MISS, GCT_NOSLOT_BR_MPRED_IC_MISS); 438 POWER_EVENT_ATTR(GRP_CMPL, GRP_CMPL); 439 POWER_EVENT_ATTR(1PLUS_PPC_CMPL, 1PLUS_PPC_CMPL); 440 POWER_EVENT_ATTR(CMPLU_STALL_DFU, CMPLU_STALL_DFU); 441 POWER_EVENT_ATTR(RUN_CYC, RUN_CYC); 442 POWER_EVENT_ATTR(RUN_INST_CMPL, RUN_INST_CMPL); 443 444 static struct attribute *power7_events_attr[] = { 445 GENERIC_EVENT_PTR(CYC), 446 GENERIC_EVENT_PTR(GCT_NOSLOT_CYC), 447 GENERIC_EVENT_PTR(CMPLU_STALL), 448 GENERIC_EVENT_PTR(INST_CMPL), 449 GENERIC_EVENT_PTR(LD_REF_L1), 450 GENERIC_EVENT_PTR(LD_MISS_L1), 451 GENERIC_EVENT_PTR(BRU_FIN), 452 GENERIC_EVENT_PTR(BR_MPRED), 453 454 POWER_EVENT_PTR(CYC), 455 POWER_EVENT_PTR(GCT_NOSLOT_CYC), 456 POWER_EVENT_PTR(CMPLU_STALL), 457 POWER_EVENT_PTR(INST_CMPL), 458 POWER_EVENT_PTR(LD_REF_L1), 459 POWER_EVENT_PTR(LD_MISS_L1), 460 POWER_EVENT_PTR(BRU_FIN), 461 POWER_EVENT_PTR(BR_MPRED), 462 463 POWER_EVENT_PTR(CMPLU_STALL_FXU), 464 POWER_EVENT_PTR(CMPLU_STALL_DIV), 465 POWER_EVENT_PTR(CMPLU_STALL_SCALAR), 466 POWER_EVENT_PTR(CMPLU_STALL_SCALAR_LONG), 467 POWER_EVENT_PTR(CMPLU_STALL_VECTOR), 468 POWER_EVENT_PTR(CMPLU_STALL_VECTOR_LONG), 469 POWER_EVENT_PTR(CMPLU_STALL_LSU), 470 POWER_EVENT_PTR(CMPLU_STALL_REJECT), 471 472 POWER_EVENT_PTR(CMPLU_STALL_ERAT_MISS), 473 POWER_EVENT_PTR(CMPLU_STALL_DCACHE_MISS), 474 POWER_EVENT_PTR(CMPLU_STALL_STORE), 475 POWER_EVENT_PTR(CMPLU_STALL_THRD), 476 POWER_EVENT_PTR(CMPLU_STALL_IFU), 477 POWER_EVENT_PTR(CMPLU_STALL_BRU), 478 POWER_EVENT_PTR(GCT_NOSLOT_IC_MISS), 479 POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED), 480 481 POWER_EVENT_PTR(GCT_NOSLOT_BR_MPRED_IC_MISS), 482 POWER_EVENT_PTR(GRP_CMPL), 483 POWER_EVENT_PTR(1PLUS_PPC_CMPL), 484 POWER_EVENT_PTR(CMPLU_STALL_DFU), 485 POWER_EVENT_PTR(RUN_CYC), 486 POWER_EVENT_PTR(RUN_INST_CMPL), 487 NULL 488 }; 489 490 491 static struct attribute_group power7_pmu_events_group = { 492 .name = "events", 493 .attrs = power7_events_attr, 494 }; 495 496 PMU_FORMAT_ATTR(event, "config:0-19"); 497 498 static struct attribute *power7_pmu_format_attr[] = { 499 &format_attr_event.attr, 500 NULL, 501 }; 502 503 struct attribute_group power7_pmu_format_group = { 504 .name = "format", 505 .attrs = power7_pmu_format_attr, 506 }; 507 508 static const struct attribute_group *power7_pmu_attr_groups[] = { 509 &power7_pmu_format_group, 510 &power7_pmu_events_group, 511 NULL, 512 }; 513 514 static struct power_pmu power7_pmu = { 515 .name = "POWER7", 516 .n_counter = 6, 517 .max_alternatives = MAX_ALT + 1, 518 .add_fields = 0x1555ul, 519 .test_adder = 0x3000ul, 520 .compute_mmcr = power7_compute_mmcr, 521 .get_constraint = power7_get_constraint, 522 .get_alternatives = power7_get_alternatives, 523 .disable_pmc = power7_disable_pmc, 524 .flags = PPMU_ALT_SIPR, 525 .attr_groups = power7_pmu_attr_groups, 526 .n_generic = ARRAY_SIZE(power7_generic_events), 527 .generic_events = power7_generic_events, 528 .cache_events = &power7_cache_events, 529 }; 530 531 static int __init init_power7_pmu(void) 532 { 533 if (!cur_cpu_spec->oprofile_cpu_type || 534 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7")) 535 return -ENODEV; 536 537 if (pvr_version_is(PVR_POWER7p)) 538 power7_pmu.flags |= PPMU_SIAR_VALID; 539 540 return register_power_pmu(&power7_pmu); 541 } 542 543 early_initcall(init_power7_pmu); 544