1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance counter support for POWER10 processors. 4 * 5 * Copyright 2020 Madhavan Srinivasan, IBM Corporation. 6 * Copyright 2020 Athira Rajeev, IBM Corporation. 7 */ 8 9 #define pr_fmt(fmt) "power10-pmu: " fmt 10 11 #include "isa207-common.h" 12 13 /* 14 * Raw event encoding for Power10: 15 * 16 * 60 56 52 48 44 40 36 32 17 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 18 * | | [ ] [ src_match ] [ src_mask ] | [ ] [ l2l3_sel ] [ thresh_ctl ] 19 * | | | | | | 20 * | | *- IFM (Linux) | | thresh start/stop -* 21 * | *- BHRB (Linux) | src_sel 22 * *- EBB (Linux) *invert_bit 23 * 24 * 28 24 20 16 12 8 4 0 25 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 26 * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] | m [ pmcxsel ] 27 * | | | | | | | 28 * | | | | | | *- mark 29 * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual 30 * | | sdar_mode | 31 * | *- sampling mode for marked events *- combine 32 * | 33 * *- thresh_sel 34 * 35 * Below uses IBM bit numbering. 36 * 37 * MMCR1[x:y] = unit (PMCxUNIT) 38 * MMCR1[24] = pmc1combine[0] 39 * MMCR1[25] = pmc1combine[1] 40 * MMCR1[26] = pmc2combine[0] 41 * MMCR1[27] = pmc2combine[1] 42 * MMCR1[28] = pmc3combine[0] 43 * MMCR1[29] = pmc3combine[1] 44 * MMCR1[30] = pmc4combine[0] 45 * MMCR1[31] = pmc4combine[1] 46 * 47 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 48 * MMCR1[20:27] = thresh_ctl 49 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 50 * MMCR1[20:27] = thresh_ctl 51 * else 52 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 53 * 54 * if thresh_sel: 55 * MMCRA[45:47] = thresh_sel 56 * 57 * if l2l3_sel: 58 * MMCR2[56:60] = l2l3_sel[0:4] 59 * 60 * MMCR1[16] = cache_sel[0] 61 * MMCR1[17] = cache_sel[1] 62 * MMCR1[18] = radix_scope_qual 63 * 64 * if mark: 65 * MMCRA[63] = 1 (SAMPLE_ENABLE) 66 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 67 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 68 * 69 * if EBB and BHRB: 70 * MMCRA[32:33] = IFM 71 * 72 * MMCRA[SDAR_MODE] = sdar_mode[0:1] 73 */ 74 75 /* 76 * Some power10 event codes. 77 */ 78 #define EVENT(_name, _code) enum{_name = _code} 79 80 #include "power10-events-list.h" 81 82 #undef EVENT 83 84 /* MMCRA IFM bits - POWER10 */ 85 #define POWER10_MMCRA_IFM1 0x0000000040000000UL 86 #define POWER10_MMCRA_IFM2 0x0000000080000000UL 87 #define POWER10_MMCRA_IFM3 0x00000000C0000000UL 88 #define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL 89 90 extern u64 PERF_REG_EXTENDED_MASK; 91 92 /* Table of alternatives, sorted by column 0 */ 93 static const unsigned int power10_event_alternatives[][MAX_ALT] = { 94 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 95 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 96 }; 97 98 static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 99 { 100 int num_alt = 0; 101 102 num_alt = isa207_get_alternatives(event, alt, 103 ARRAY_SIZE(power10_event_alternatives), flags, 104 power10_event_alternatives); 105 106 return num_alt; 107 } 108 109 GENERIC_EVENT_ATTR(cpu-cycles, PM_RUN_CYC); 110 GENERIC_EVENT_ATTR(instructions, PM_RUN_INST_CMPL); 111 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 112 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 113 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 114 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); 115 GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS); 116 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES); 117 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_FIN); 118 GENERIC_EVENT_ATTR(branch-misses, PM_MPRED_BR_FIN); 119 GENERIC_EVENT_ATTR(cache-misses, PM_LD_DEMAND_MISS_L1_FIN); 120 121 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 122 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 123 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS); 124 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 125 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 126 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 127 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ); 128 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 129 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 130 CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PF_MISS_L3); 131 CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); 132 CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); 133 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 134 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 135 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 136 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 137 138 static struct attribute *power10_events_attr_dd1[] = { 139 GENERIC_EVENT_PTR(PM_RUN_CYC), 140 GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), 141 GENERIC_EVENT_PTR(PM_BR_CMPL), 142 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 143 GENERIC_EVENT_PTR(PM_LD_REF_L1), 144 GENERIC_EVENT_PTR(PM_LD_MISS_L1), 145 GENERIC_EVENT_PTR(MEM_LOADS), 146 GENERIC_EVENT_PTR(MEM_STORES), 147 CACHE_EVENT_PTR(PM_LD_MISS_L1), 148 CACHE_EVENT_PTR(PM_LD_REF_L1), 149 CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS), 150 CACHE_EVENT_PTR(PM_ST_MISS_L1), 151 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 152 CACHE_EVENT_PTR(PM_INST_FROM_L1), 153 CACHE_EVENT_PTR(PM_IC_PREF_REQ), 154 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 155 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 156 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 157 CACHE_EVENT_PTR(PM_BR_CMPL), 158 CACHE_EVENT_PTR(PM_DTLB_MISS), 159 CACHE_EVENT_PTR(PM_ITLB_MISS), 160 NULL 161 }; 162 163 static struct attribute *power10_events_attr[] = { 164 GENERIC_EVENT_PTR(PM_RUN_CYC), 165 GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), 166 GENERIC_EVENT_PTR(PM_BR_FIN), 167 GENERIC_EVENT_PTR(PM_MPRED_BR_FIN), 168 GENERIC_EVENT_PTR(PM_LD_REF_L1), 169 GENERIC_EVENT_PTR(PM_LD_DEMAND_MISS_L1_FIN), 170 GENERIC_EVENT_PTR(MEM_LOADS), 171 GENERIC_EVENT_PTR(MEM_STORES), 172 CACHE_EVENT_PTR(PM_LD_MISS_L1), 173 CACHE_EVENT_PTR(PM_LD_REF_L1), 174 CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS), 175 CACHE_EVENT_PTR(PM_ST_MISS_L1), 176 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 177 CACHE_EVENT_PTR(PM_INST_FROM_L1), 178 CACHE_EVENT_PTR(PM_IC_PREF_REQ), 179 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 180 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 181 CACHE_EVENT_PTR(PM_L3_PF_MISS_L3), 182 CACHE_EVENT_PTR(PM_L2_ST_MISS), 183 CACHE_EVENT_PTR(PM_L2_ST), 184 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 185 CACHE_EVENT_PTR(PM_BR_CMPL), 186 CACHE_EVENT_PTR(PM_DTLB_MISS), 187 CACHE_EVENT_PTR(PM_ITLB_MISS), 188 NULL 189 }; 190 191 static struct attribute_group power10_pmu_events_group_dd1 = { 192 .name = "events", 193 .attrs = power10_events_attr_dd1, 194 }; 195 196 static struct attribute_group power10_pmu_events_group = { 197 .name = "events", 198 .attrs = power10_events_attr, 199 }; 200 201 PMU_FORMAT_ATTR(event, "config:0-59"); 202 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 203 PMU_FORMAT_ATTR(mark, "config:8"); 204 PMU_FORMAT_ATTR(combine, "config:10-11"); 205 PMU_FORMAT_ATTR(unit, "config:12-15"); 206 PMU_FORMAT_ATTR(pmc, "config:16-19"); 207 PMU_FORMAT_ATTR(cache_sel, "config:20-21"); 208 PMU_FORMAT_ATTR(sdar_mode, "config:22-23"); 209 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 210 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 211 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 212 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 213 PMU_FORMAT_ATTR(l2l3_sel, "config:40-44"); 214 PMU_FORMAT_ATTR(src_sel, "config:45-46"); 215 PMU_FORMAT_ATTR(invert_bit, "config:47"); 216 PMU_FORMAT_ATTR(src_mask, "config:48-53"); 217 PMU_FORMAT_ATTR(src_match, "config:54-59"); 218 PMU_FORMAT_ATTR(radix_scope, "config:9"); 219 PMU_FORMAT_ATTR(thresh_cmp, "config1:0-17"); 220 221 static struct attribute *power10_pmu_format_attr[] = { 222 &format_attr_event.attr, 223 &format_attr_pmcxsel.attr, 224 &format_attr_mark.attr, 225 &format_attr_combine.attr, 226 &format_attr_unit.attr, 227 &format_attr_pmc.attr, 228 &format_attr_cache_sel.attr, 229 &format_attr_sdar_mode.attr, 230 &format_attr_sample_mode.attr, 231 &format_attr_thresh_sel.attr, 232 &format_attr_thresh_stop.attr, 233 &format_attr_thresh_start.attr, 234 &format_attr_l2l3_sel.attr, 235 &format_attr_src_sel.attr, 236 &format_attr_invert_bit.attr, 237 &format_attr_src_mask.attr, 238 &format_attr_src_match.attr, 239 &format_attr_radix_scope.attr, 240 &format_attr_thresh_cmp.attr, 241 NULL, 242 }; 243 244 static struct attribute_group power10_pmu_format_group = { 245 .name = "format", 246 .attrs = power10_pmu_format_attr, 247 }; 248 249 static const struct attribute_group *power10_pmu_attr_groups_dd1[] = { 250 &power10_pmu_format_group, 251 &power10_pmu_events_group_dd1, 252 NULL, 253 }; 254 255 static const struct attribute_group *power10_pmu_attr_groups[] = { 256 &power10_pmu_format_group, 257 &power10_pmu_events_group, 258 NULL, 259 }; 260 261 static int power10_generic_events_dd1[] = { 262 [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC, 263 [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL, 264 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 265 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 266 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 267 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 268 }; 269 270 static int power10_generic_events[] = { 271 [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC, 272 [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL, 273 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_FIN, 274 [PERF_COUNT_HW_BRANCH_MISSES] = PM_MPRED_BR_FIN, 275 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 276 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_DEMAND_MISS_L1_FIN, 277 }; 278 279 static u64 power10_bhrb_filter_map(u64 branch_sample_type) 280 { 281 u64 pmu_bhrb_filter = 0; 282 283 /* BHRB and regular PMU events share the same privilege state 284 * filter configuration. BHRB is always recorded along with a 285 * regular PMU event. As the privilege state filter is handled 286 * in the basic PMC configuration of the accompanying regular 287 * PMU event, we ignore any separate BHRB specific request. 288 */ 289 290 /* No branch filter requested */ 291 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 292 return pmu_bhrb_filter; 293 294 /* Invalid branch filter options - HW does not support */ 295 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 296 return -1; 297 298 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) { 299 pmu_bhrb_filter |= POWER10_MMCRA_IFM2; 300 return pmu_bhrb_filter; 301 } 302 303 if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) { 304 pmu_bhrb_filter |= POWER10_MMCRA_IFM3; 305 return pmu_bhrb_filter; 306 } 307 308 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 309 return -1; 310 311 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 312 pmu_bhrb_filter |= POWER10_MMCRA_IFM1; 313 return pmu_bhrb_filter; 314 } 315 316 /* Every thing else is unsupported */ 317 return -1; 318 } 319 320 static void power10_config_bhrb(u64 pmu_bhrb_filter) 321 { 322 pmu_bhrb_filter &= POWER10_MMCRA_BHRB_MASK; 323 324 /* Enable BHRB filter in PMU */ 325 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 326 } 327 328 #define C(x) PERF_COUNT_HW_CACHE_##x 329 330 /* 331 * Table of generalized cache-related events. 332 * 0 means not supported, -1 means nonsensical, other values 333 * are event codes. 334 */ 335 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 336 [C(L1D)] = { 337 [C(OP_READ)] = { 338 [C(RESULT_ACCESS)] = PM_LD_REF_L1, 339 [C(RESULT_MISS)] = PM_LD_MISS_L1, 340 }, 341 [C(OP_WRITE)] = { 342 [C(RESULT_ACCESS)] = 0, 343 [C(RESULT_MISS)] = PM_ST_MISS_L1, 344 }, 345 [C(OP_PREFETCH)] = { 346 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS, 347 [C(RESULT_MISS)] = 0, 348 }, 349 }, 350 [C(L1I)] = { 351 [C(OP_READ)] = { 352 [C(RESULT_ACCESS)] = PM_INST_FROM_L1, 353 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS, 354 }, 355 [C(OP_WRITE)] = { 356 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS, 357 [C(RESULT_MISS)] = -1, 358 }, 359 [C(OP_PREFETCH)] = { 360 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ, 361 [C(RESULT_MISS)] = 0, 362 }, 363 }, 364 [C(LL)] = { 365 [C(OP_READ)] = { 366 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3, 367 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS, 368 }, 369 [C(OP_WRITE)] = { 370 [C(RESULT_ACCESS)] = -1, 371 [C(RESULT_MISS)] = -1, 372 }, 373 [C(OP_PREFETCH)] = { 374 [C(RESULT_ACCESS)] = -1, 375 [C(RESULT_MISS)] = 0, 376 }, 377 }, 378 [C(DTLB)] = { 379 [C(OP_READ)] = { 380 [C(RESULT_ACCESS)] = 0, 381 [C(RESULT_MISS)] = PM_DTLB_MISS, 382 }, 383 [C(OP_WRITE)] = { 384 [C(RESULT_ACCESS)] = -1, 385 [C(RESULT_MISS)] = -1, 386 }, 387 [C(OP_PREFETCH)] = { 388 [C(RESULT_ACCESS)] = -1, 389 [C(RESULT_MISS)] = -1, 390 }, 391 }, 392 [C(ITLB)] = { 393 [C(OP_READ)] = { 394 [C(RESULT_ACCESS)] = 0, 395 [C(RESULT_MISS)] = PM_ITLB_MISS, 396 }, 397 [C(OP_WRITE)] = { 398 [C(RESULT_ACCESS)] = -1, 399 [C(RESULT_MISS)] = -1, 400 }, 401 [C(OP_PREFETCH)] = { 402 [C(RESULT_ACCESS)] = -1, 403 [C(RESULT_MISS)] = -1, 404 }, 405 }, 406 [C(BPU)] = { 407 [C(OP_READ)] = { 408 [C(RESULT_ACCESS)] = PM_BR_CMPL, 409 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL, 410 }, 411 [C(OP_WRITE)] = { 412 [C(RESULT_ACCESS)] = -1, 413 [C(RESULT_MISS)] = -1, 414 }, 415 [C(OP_PREFETCH)] = { 416 [C(RESULT_ACCESS)] = -1, 417 [C(RESULT_MISS)] = -1, 418 }, 419 }, 420 [C(NODE)] = { 421 [C(OP_READ)] = { 422 [C(RESULT_ACCESS)] = -1, 423 [C(RESULT_MISS)] = -1, 424 }, 425 [C(OP_WRITE)] = { 426 [C(RESULT_ACCESS)] = -1, 427 [C(RESULT_MISS)] = -1, 428 }, 429 [C(OP_PREFETCH)] = { 430 [C(RESULT_ACCESS)] = -1, 431 [C(RESULT_MISS)] = -1, 432 }, 433 }, 434 }; 435 436 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 437 [C(L1D)] = { 438 [C(OP_READ)] = { 439 [C(RESULT_ACCESS)] = PM_LD_REF_L1, 440 [C(RESULT_MISS)] = PM_LD_MISS_L1, 441 }, 442 [C(OP_WRITE)] = { 443 [C(RESULT_ACCESS)] = 0, 444 [C(RESULT_MISS)] = PM_ST_MISS_L1, 445 }, 446 [C(OP_PREFETCH)] = { 447 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS, 448 [C(RESULT_MISS)] = 0, 449 }, 450 }, 451 [C(L1I)] = { 452 [C(OP_READ)] = { 453 [C(RESULT_ACCESS)] = PM_INST_FROM_L1, 454 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS, 455 }, 456 [C(OP_WRITE)] = { 457 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS, 458 [C(RESULT_MISS)] = -1, 459 }, 460 [C(OP_PREFETCH)] = { 461 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ, 462 [C(RESULT_MISS)] = 0, 463 }, 464 }, 465 [C(LL)] = { 466 [C(OP_READ)] = { 467 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3, 468 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS, 469 }, 470 [C(OP_WRITE)] = { 471 [C(RESULT_ACCESS)] = PM_L2_ST, 472 [C(RESULT_MISS)] = PM_L2_ST_MISS, 473 }, 474 [C(OP_PREFETCH)] = { 475 [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3, 476 [C(RESULT_MISS)] = 0, 477 }, 478 }, 479 [C(DTLB)] = { 480 [C(OP_READ)] = { 481 [C(RESULT_ACCESS)] = 0, 482 [C(RESULT_MISS)] = PM_DTLB_MISS, 483 }, 484 [C(OP_WRITE)] = { 485 [C(RESULT_ACCESS)] = -1, 486 [C(RESULT_MISS)] = -1, 487 }, 488 [C(OP_PREFETCH)] = { 489 [C(RESULT_ACCESS)] = -1, 490 [C(RESULT_MISS)] = -1, 491 }, 492 }, 493 [C(ITLB)] = { 494 [C(OP_READ)] = { 495 [C(RESULT_ACCESS)] = 0, 496 [C(RESULT_MISS)] = PM_ITLB_MISS, 497 }, 498 [C(OP_WRITE)] = { 499 [C(RESULT_ACCESS)] = -1, 500 [C(RESULT_MISS)] = -1, 501 }, 502 [C(OP_PREFETCH)] = { 503 [C(RESULT_ACCESS)] = -1, 504 [C(RESULT_MISS)] = -1, 505 }, 506 }, 507 [C(BPU)] = { 508 [C(OP_READ)] = { 509 [C(RESULT_ACCESS)] = PM_BR_CMPL, 510 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL, 511 }, 512 [C(OP_WRITE)] = { 513 [C(RESULT_ACCESS)] = -1, 514 [C(RESULT_MISS)] = -1, 515 }, 516 [C(OP_PREFETCH)] = { 517 [C(RESULT_ACCESS)] = -1, 518 [C(RESULT_MISS)] = -1, 519 }, 520 }, 521 [C(NODE)] = { 522 [C(OP_READ)] = { 523 [C(RESULT_ACCESS)] = -1, 524 [C(RESULT_MISS)] = -1, 525 }, 526 [C(OP_WRITE)] = { 527 [C(RESULT_ACCESS)] = -1, 528 [C(RESULT_MISS)] = -1, 529 }, 530 [C(OP_PREFETCH)] = { 531 [C(RESULT_ACCESS)] = -1, 532 [C(RESULT_MISS)] = -1, 533 }, 534 }, 535 }; 536 537 #undef C 538 539 static struct power_pmu power10_pmu = { 540 .name = "POWER10", 541 .n_counter = MAX_PMU_COUNTERS, 542 .add_fields = ISA207_ADD_FIELDS, 543 .test_adder = ISA207_TEST_ADDER, 544 .group_constraint_mask = CNST_CACHE_PMC4_MASK, 545 .group_constraint_val = CNST_CACHE_PMC4_VAL, 546 .compute_mmcr = isa207_compute_mmcr, 547 .config_bhrb = power10_config_bhrb, 548 .bhrb_filter_map = power10_bhrb_filter_map, 549 .get_constraint = isa207_get_constraint, 550 .get_alternatives = power10_get_alternatives, 551 .get_mem_data_src = isa207_get_mem_data_src, 552 .get_mem_weight = isa207_get_mem_weight, 553 .disable_pmc = isa207_disable_pmc, 554 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S | 555 PPMU_ARCH_31 | PPMU_HAS_ATTR_CONFIG1, 556 .n_generic = ARRAY_SIZE(power10_generic_events), 557 .generic_events = power10_generic_events, 558 .cache_events = &power10_cache_events, 559 .attr_groups = power10_pmu_attr_groups, 560 .bhrb_nr = 32, 561 .capabilities = PERF_PMU_CAP_EXTENDED_REGS, 562 }; 563 564 int init_power10_pmu(void) 565 { 566 unsigned int pvr; 567 int rc; 568 569 /* Comes from cpu_specs[] */ 570 if (!cur_cpu_spec->oprofile_cpu_type || 571 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10")) 572 return -ENODEV; 573 574 pvr = mfspr(SPRN_PVR); 575 /* Add the ppmu flag for power10 DD1 */ 576 if ((PVR_CFG(pvr) == 1)) 577 power10_pmu.flags |= PPMU_P10_DD1; 578 579 /* Set the PERF_REG_EXTENDED_MASK here */ 580 PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31; 581 582 if ((PVR_CFG(pvr) == 1)) { 583 power10_pmu.generic_events = power10_generic_events_dd1; 584 power10_pmu.attr_groups = power10_pmu_attr_groups_dd1; 585 power10_pmu.cache_events = &power10_cache_events_dd1; 586 } 587 588 rc = register_power_pmu(&power10_pmu); 589 if (rc) 590 return rc; 591 592 /* Tell userspace that EBB is supported */ 593 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 594 595 return 0; 596 } 597