1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance counter support for POWER10 processors. 4 * 5 * Copyright 2020 Madhavan Srinivasan, IBM Corporation. 6 * Copyright 2020 Athira Rajeev, IBM Corporation. 7 */ 8 9 #define pr_fmt(fmt) "power10-pmu: " fmt 10 11 #include "isa207-common.h" 12 #include "internal.h" 13 14 /* 15 * Raw event encoding for Power10: 16 * 17 * 60 56 52 48 44 40 36 32 18 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 19 * | | [ ] [ src_match ] [ src_mask ] | [ ] [ l2l3_sel ] [ thresh_ctl ] 20 * | | | | | | 21 * | | *- IFM (Linux) | | thresh start/stop -* 22 * | *- BHRB (Linux) | src_sel 23 * *- EBB (Linux) *invert_bit 24 * 25 * 28 24 20 16 12 8 4 0 26 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 27 * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] m [ pmcxsel ] 28 * | | | | | | 29 * | | | | | *- mark 30 * | | | *- L1/L2/L3 cache_sel | 31 * | | sdar_mode | 32 * | *- sampling mode for marked events *- combine 33 * | 34 * *- thresh_sel 35 * 36 * Below uses IBM bit numbering. 37 * 38 * MMCR1[x:y] = unit (PMCxUNIT) 39 * MMCR1[24] = pmc1combine[0] 40 * MMCR1[25] = pmc1combine[1] 41 * MMCR1[26] = pmc2combine[0] 42 * MMCR1[27] = pmc2combine[1] 43 * MMCR1[28] = pmc3combine[0] 44 * MMCR1[29] = pmc3combine[1] 45 * MMCR1[30] = pmc4combine[0] 46 * MMCR1[31] = pmc4combine[1] 47 * 48 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 49 * MMCR1[20:27] = thresh_ctl 50 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 51 * MMCR1[20:27] = thresh_ctl 52 * else 53 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 54 * 55 * if thresh_sel: 56 * MMCRA[45:47] = thresh_sel 57 * 58 * if l2l3_sel: 59 * MMCR2[56:60] = l2l3_sel[0:4] 60 * 61 * MMCR1[16] = cache_sel[0] 62 * MMCR1[17] = cache_sel[1] 63 * 64 * if mark: 65 * MMCRA[63] = 1 (SAMPLE_ENABLE) 66 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 67 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 68 * 69 * if EBB and BHRB: 70 * MMCRA[32:33] = IFM 71 * 72 * MMCRA[SDAR_MODE] = sdar_mode[0:1] 73 */ 74 75 /* 76 * Some power10 event codes. 77 */ 78 #define EVENT(_name, _code) enum{_name = _code} 79 80 #include "power10-events-list.h" 81 82 #undef EVENT 83 84 /* MMCRA IFM bits - POWER10 */ 85 #define POWER10_MMCRA_IFM1 0x0000000040000000UL 86 #define POWER10_MMCRA_IFM2 0x0000000080000000UL 87 #define POWER10_MMCRA_IFM3 0x00000000C0000000UL 88 #define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL 89 90 extern u64 PERF_REG_EXTENDED_MASK; 91 92 /* Table of alternatives, sorted by column 0 */ 93 static const unsigned int power10_event_alternatives[][MAX_ALT] = { 94 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 95 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 96 }; 97 98 static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 99 { 100 int num_alt = 0; 101 102 num_alt = isa207_get_alternatives(event, alt, 103 ARRAY_SIZE(power10_event_alternatives), flags, 104 power10_event_alternatives); 105 106 return num_alt; 107 } 108 109 GENERIC_EVENT_ATTR(cpu-cycles, PM_RUN_CYC); 110 GENERIC_EVENT_ATTR(instructions, PM_RUN_INST_CMPL); 111 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 112 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 113 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 114 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); 115 GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS); 116 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES); 117 118 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 119 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 120 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS); 121 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 122 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 123 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 124 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ); 125 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 126 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 127 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 128 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 129 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 130 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 131 132 static struct attribute *power10_events_attr[] = { 133 GENERIC_EVENT_PTR(PM_RUN_CYC), 134 GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), 135 GENERIC_EVENT_PTR(PM_BR_CMPL), 136 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 137 GENERIC_EVENT_PTR(PM_LD_REF_L1), 138 GENERIC_EVENT_PTR(PM_LD_MISS_L1), 139 GENERIC_EVENT_PTR(MEM_LOADS), 140 GENERIC_EVENT_PTR(MEM_STORES), 141 CACHE_EVENT_PTR(PM_LD_MISS_L1), 142 CACHE_EVENT_PTR(PM_LD_REF_L1), 143 CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS), 144 CACHE_EVENT_PTR(PM_ST_MISS_L1), 145 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 146 CACHE_EVENT_PTR(PM_INST_FROM_L1), 147 CACHE_EVENT_PTR(PM_IC_PREF_REQ), 148 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 149 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 150 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 151 CACHE_EVENT_PTR(PM_BR_CMPL), 152 CACHE_EVENT_PTR(PM_DTLB_MISS), 153 CACHE_EVENT_PTR(PM_ITLB_MISS), 154 NULL 155 }; 156 157 static struct attribute_group power10_pmu_events_group = { 158 .name = "events", 159 .attrs = power10_events_attr, 160 }; 161 162 PMU_FORMAT_ATTR(event, "config:0-59"); 163 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 164 PMU_FORMAT_ATTR(mark, "config:8"); 165 PMU_FORMAT_ATTR(combine, "config:10-11"); 166 PMU_FORMAT_ATTR(unit, "config:12-15"); 167 PMU_FORMAT_ATTR(pmc, "config:16-19"); 168 PMU_FORMAT_ATTR(cache_sel, "config:20-21"); 169 PMU_FORMAT_ATTR(sdar_mode, "config:22-23"); 170 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 171 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 172 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 173 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 174 PMU_FORMAT_ATTR(l2l3_sel, "config:40-44"); 175 PMU_FORMAT_ATTR(src_sel, "config:45-46"); 176 PMU_FORMAT_ATTR(invert_bit, "config:47"); 177 PMU_FORMAT_ATTR(src_mask, "config:48-53"); 178 PMU_FORMAT_ATTR(src_match, "config:54-59"); 179 180 static struct attribute *power10_pmu_format_attr[] = { 181 &format_attr_event.attr, 182 &format_attr_pmcxsel.attr, 183 &format_attr_mark.attr, 184 &format_attr_combine.attr, 185 &format_attr_unit.attr, 186 &format_attr_pmc.attr, 187 &format_attr_cache_sel.attr, 188 &format_attr_sdar_mode.attr, 189 &format_attr_sample_mode.attr, 190 &format_attr_thresh_sel.attr, 191 &format_attr_thresh_stop.attr, 192 &format_attr_thresh_start.attr, 193 &format_attr_l2l3_sel.attr, 194 &format_attr_src_sel.attr, 195 &format_attr_invert_bit.attr, 196 &format_attr_src_mask.attr, 197 &format_attr_src_match.attr, 198 NULL, 199 }; 200 201 static struct attribute_group power10_pmu_format_group = { 202 .name = "format", 203 .attrs = power10_pmu_format_attr, 204 }; 205 206 static const struct attribute_group *power10_pmu_attr_groups[] = { 207 &power10_pmu_format_group, 208 &power10_pmu_events_group, 209 NULL, 210 }; 211 212 static int power10_generic_events[] = { 213 [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC, 214 [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL, 215 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 216 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 217 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 218 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 219 }; 220 221 static u64 power10_bhrb_filter_map(u64 branch_sample_type) 222 { 223 u64 pmu_bhrb_filter = 0; 224 225 /* BHRB and regular PMU events share the same privilege state 226 * filter configuration. BHRB is always recorded along with a 227 * regular PMU event. As the privilege state filter is handled 228 * in the basic PMC configuration of the accompanying regular 229 * PMU event, we ignore any separate BHRB specific request. 230 */ 231 232 /* No branch filter requested */ 233 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 234 return pmu_bhrb_filter; 235 236 /* Invalid branch filter options - HW does not support */ 237 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 238 return -1; 239 240 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) { 241 pmu_bhrb_filter |= POWER10_MMCRA_IFM2; 242 return pmu_bhrb_filter; 243 } 244 245 if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) { 246 pmu_bhrb_filter |= POWER10_MMCRA_IFM3; 247 return pmu_bhrb_filter; 248 } 249 250 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 251 return -1; 252 253 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 254 pmu_bhrb_filter |= POWER10_MMCRA_IFM1; 255 return pmu_bhrb_filter; 256 } 257 258 /* Every thing else is unsupported */ 259 return -1; 260 } 261 262 static void power10_config_bhrb(u64 pmu_bhrb_filter) 263 { 264 pmu_bhrb_filter &= POWER10_MMCRA_BHRB_MASK; 265 266 /* Enable BHRB filter in PMU */ 267 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 268 } 269 270 #define C(x) PERF_COUNT_HW_CACHE_##x 271 272 /* 273 * Table of generalized cache-related events. 274 * 0 means not supported, -1 means nonsensical, other values 275 * are event codes. 276 */ 277 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 278 [C(L1D)] = { 279 [C(OP_READ)] = { 280 [C(RESULT_ACCESS)] = PM_LD_REF_L1, 281 [C(RESULT_MISS)] = PM_LD_MISS_L1, 282 }, 283 [C(OP_WRITE)] = { 284 [C(RESULT_ACCESS)] = 0, 285 [C(RESULT_MISS)] = PM_ST_MISS_L1, 286 }, 287 [C(OP_PREFETCH)] = { 288 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS, 289 [C(RESULT_MISS)] = 0, 290 }, 291 }, 292 [C(L1I)] = { 293 [C(OP_READ)] = { 294 [C(RESULT_ACCESS)] = PM_INST_FROM_L1, 295 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS, 296 }, 297 [C(OP_WRITE)] = { 298 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS, 299 [C(RESULT_MISS)] = -1, 300 }, 301 [C(OP_PREFETCH)] = { 302 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ, 303 [C(RESULT_MISS)] = 0, 304 }, 305 }, 306 [C(LL)] = { 307 [C(OP_READ)] = { 308 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3, 309 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS, 310 }, 311 [C(OP_WRITE)] = { 312 [C(RESULT_ACCESS)] = -1, 313 [C(RESULT_MISS)] = -1, 314 }, 315 [C(OP_PREFETCH)] = { 316 [C(RESULT_ACCESS)] = -1, 317 [C(RESULT_MISS)] = 0, 318 }, 319 }, 320 [C(DTLB)] = { 321 [C(OP_READ)] = { 322 [C(RESULT_ACCESS)] = 0, 323 [C(RESULT_MISS)] = PM_DTLB_MISS, 324 }, 325 [C(OP_WRITE)] = { 326 [C(RESULT_ACCESS)] = -1, 327 [C(RESULT_MISS)] = -1, 328 }, 329 [C(OP_PREFETCH)] = { 330 [C(RESULT_ACCESS)] = -1, 331 [C(RESULT_MISS)] = -1, 332 }, 333 }, 334 [C(ITLB)] = { 335 [C(OP_READ)] = { 336 [C(RESULT_ACCESS)] = 0, 337 [C(RESULT_MISS)] = PM_ITLB_MISS, 338 }, 339 [C(OP_WRITE)] = { 340 [C(RESULT_ACCESS)] = -1, 341 [C(RESULT_MISS)] = -1, 342 }, 343 [C(OP_PREFETCH)] = { 344 [C(RESULT_ACCESS)] = -1, 345 [C(RESULT_MISS)] = -1, 346 }, 347 }, 348 [C(BPU)] = { 349 [C(OP_READ)] = { 350 [C(RESULT_ACCESS)] = PM_BR_CMPL, 351 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL, 352 }, 353 [C(OP_WRITE)] = { 354 [C(RESULT_ACCESS)] = -1, 355 [C(RESULT_MISS)] = -1, 356 }, 357 [C(OP_PREFETCH)] = { 358 [C(RESULT_ACCESS)] = -1, 359 [C(RESULT_MISS)] = -1, 360 }, 361 }, 362 [C(NODE)] = { 363 [C(OP_READ)] = { 364 [C(RESULT_ACCESS)] = -1, 365 [C(RESULT_MISS)] = -1, 366 }, 367 [C(OP_WRITE)] = { 368 [C(RESULT_ACCESS)] = -1, 369 [C(RESULT_MISS)] = -1, 370 }, 371 [C(OP_PREFETCH)] = { 372 [C(RESULT_ACCESS)] = -1, 373 [C(RESULT_MISS)] = -1, 374 }, 375 }, 376 }; 377 378 #undef C 379 380 static struct power_pmu power10_pmu = { 381 .name = "POWER10", 382 .n_counter = MAX_PMU_COUNTERS, 383 .add_fields = ISA207_ADD_FIELDS, 384 .test_adder = ISA207_TEST_ADDER, 385 .group_constraint_mask = CNST_CACHE_PMC4_MASK, 386 .group_constraint_val = CNST_CACHE_PMC4_VAL, 387 .compute_mmcr = isa207_compute_mmcr, 388 .config_bhrb = power10_config_bhrb, 389 .bhrb_filter_map = power10_bhrb_filter_map, 390 .get_constraint = isa207_get_constraint, 391 .get_alternatives = power10_get_alternatives, 392 .get_mem_data_src = isa207_get_mem_data_src, 393 .get_mem_weight = isa207_get_mem_weight, 394 .disable_pmc = isa207_disable_pmc, 395 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S | 396 PPMU_ARCH_31, 397 .n_generic = ARRAY_SIZE(power10_generic_events), 398 .generic_events = power10_generic_events, 399 .cache_events = &power10_cache_events, 400 .attr_groups = power10_pmu_attr_groups, 401 .bhrb_nr = 32, 402 .capabilities = PERF_PMU_CAP_EXTENDED_REGS, 403 }; 404 405 int init_power10_pmu(void) 406 { 407 int rc; 408 409 /* Comes from cpu_specs[] */ 410 if (!cur_cpu_spec->oprofile_cpu_type || 411 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10")) 412 return -ENODEV; 413 414 /* Set the PERF_REG_EXTENDED_MASK here */ 415 PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31; 416 417 rc = register_power_pmu(&power10_pmu); 418 if (rc) 419 return rc; 420 421 /* Tell userspace that EBB is supported */ 422 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 423 424 return 0; 425 } 426