1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance counter support for POWER10 processors. 4 * 5 * Copyright 2020 Madhavan Srinivasan, IBM Corporation. 6 * Copyright 2020 Athira Rajeev, IBM Corporation. 7 */ 8 9 #define pr_fmt(fmt) "power10-pmu: " fmt 10 11 #include "isa207-common.h" 12 #include "internal.h" 13 14 /* 15 * Raw event encoding for Power10: 16 * 17 * 60 56 52 48 44 40 36 32 18 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 19 * | | [ ] [ src_match ] [ src_mask ] | [ ] [ l2l3_sel ] [ thresh_ctl ] 20 * | | | | | | 21 * | | *- IFM (Linux) | | thresh start/stop -* 22 * | *- BHRB (Linux) | src_sel 23 * *- EBB (Linux) *invert_bit 24 * 25 * 28 24 20 16 12 8 4 0 26 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 27 * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] m [ pmcxsel ] 28 * | | | | | | 29 * | | | | | *- mark 30 * | | | *- L1/L2/L3 cache_sel | 31 * | | sdar_mode | 32 * | *- sampling mode for marked events *- combine 33 * | 34 * *- thresh_sel 35 * 36 * Below uses IBM bit numbering. 37 * 38 * MMCR1[x:y] = unit (PMCxUNIT) 39 * MMCR1[24] = pmc1combine[0] 40 * MMCR1[25] = pmc1combine[1] 41 * MMCR1[26] = pmc2combine[0] 42 * MMCR1[27] = pmc2combine[1] 43 * MMCR1[28] = pmc3combine[0] 44 * MMCR1[29] = pmc3combine[1] 45 * MMCR1[30] = pmc4combine[0] 46 * MMCR1[31] = pmc4combine[1] 47 * 48 * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011 49 * MMCR1[20:27] = thresh_ctl 50 * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001 51 * MMCR1[20:27] = thresh_ctl 52 * else 53 * MMCRA[48:55] = thresh_ctl (THRESH START/END) 54 * 55 * if thresh_sel: 56 * MMCRA[45:47] = thresh_sel 57 * 58 * if l2l3_sel: 59 * MMCR2[56:60] = l2l3_sel[0:4] 60 * 61 * MMCR1[16] = cache_sel[0] 62 * MMCR1[17] = cache_sel[1] 63 * 64 * if mark: 65 * MMCRA[63] = 1 (SAMPLE_ENABLE) 66 * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG) 67 * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE) 68 * 69 * if EBB and BHRB: 70 * MMCRA[32:33] = IFM 71 * 72 * MMCRA[SDAR_MODE] = sdar_mode[0:1] 73 */ 74 75 /* 76 * Some power10 event codes. 77 */ 78 #define EVENT(_name, _code) enum{_name = _code} 79 80 #include "power10-events-list.h" 81 82 #undef EVENT 83 84 /* MMCRA IFM bits - POWER10 */ 85 #define POWER10_MMCRA_IFM1 0x0000000040000000UL 86 #define POWER10_MMCRA_IFM2 0x0000000080000000UL 87 #define POWER10_MMCRA_IFM3 0x00000000C0000000UL 88 #define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL 89 90 /* Table of alternatives, sorted by column 0 */ 91 static const unsigned int power10_event_alternatives[][MAX_ALT] = { 92 { PM_RUN_CYC_ALT, PM_RUN_CYC }, 93 { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL }, 94 }; 95 96 static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[]) 97 { 98 int num_alt = 0; 99 100 num_alt = isa207_get_alternatives(event, alt, 101 ARRAY_SIZE(power10_event_alternatives), flags, 102 power10_event_alternatives); 103 104 return num_alt; 105 } 106 107 GENERIC_EVENT_ATTR(cpu-cycles, PM_RUN_CYC); 108 GENERIC_EVENT_ATTR(instructions, PM_RUN_INST_CMPL); 109 GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL); 110 GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL); 111 GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1); 112 GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1); 113 GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS); 114 GENERIC_EVENT_ATTR(mem-stores, MEM_STORES); 115 116 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1); 117 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1); 118 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS); 119 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1); 120 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS); 121 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); 122 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ); 123 CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); 124 CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); 125 CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); 126 CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); 127 CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); 128 CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS); 129 130 static struct attribute *power10_events_attr[] = { 131 GENERIC_EVENT_PTR(PM_RUN_CYC), 132 GENERIC_EVENT_PTR(PM_RUN_INST_CMPL), 133 GENERIC_EVENT_PTR(PM_BR_CMPL), 134 GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL), 135 GENERIC_EVENT_PTR(PM_LD_REF_L1), 136 GENERIC_EVENT_PTR(PM_LD_MISS_L1), 137 GENERIC_EVENT_PTR(MEM_LOADS), 138 GENERIC_EVENT_PTR(MEM_STORES), 139 CACHE_EVENT_PTR(PM_LD_MISS_L1), 140 CACHE_EVENT_PTR(PM_LD_REF_L1), 141 CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS), 142 CACHE_EVENT_PTR(PM_ST_MISS_L1), 143 CACHE_EVENT_PTR(PM_L1_ICACHE_MISS), 144 CACHE_EVENT_PTR(PM_INST_FROM_L1), 145 CACHE_EVENT_PTR(PM_IC_PREF_REQ), 146 CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), 147 CACHE_EVENT_PTR(PM_DATA_FROM_L3), 148 CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), 149 CACHE_EVENT_PTR(PM_BR_CMPL), 150 CACHE_EVENT_PTR(PM_DTLB_MISS), 151 CACHE_EVENT_PTR(PM_ITLB_MISS), 152 NULL 153 }; 154 155 static struct attribute_group power10_pmu_events_group = { 156 .name = "events", 157 .attrs = power10_events_attr, 158 }; 159 160 PMU_FORMAT_ATTR(event, "config:0-59"); 161 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 162 PMU_FORMAT_ATTR(mark, "config:8"); 163 PMU_FORMAT_ATTR(combine, "config:10-11"); 164 PMU_FORMAT_ATTR(unit, "config:12-15"); 165 PMU_FORMAT_ATTR(pmc, "config:16-19"); 166 PMU_FORMAT_ATTR(cache_sel, "config:20-21"); 167 PMU_FORMAT_ATTR(sdar_mode, "config:22-23"); 168 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 169 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 170 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 171 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 172 PMU_FORMAT_ATTR(l2l3_sel, "config:40-44"); 173 PMU_FORMAT_ATTR(src_sel, "config:45-46"); 174 PMU_FORMAT_ATTR(invert_bit, "config:47"); 175 PMU_FORMAT_ATTR(src_mask, "config:48-53"); 176 PMU_FORMAT_ATTR(src_match, "config:54-59"); 177 178 static struct attribute *power10_pmu_format_attr[] = { 179 &format_attr_event.attr, 180 &format_attr_pmcxsel.attr, 181 &format_attr_mark.attr, 182 &format_attr_combine.attr, 183 &format_attr_unit.attr, 184 &format_attr_pmc.attr, 185 &format_attr_cache_sel.attr, 186 &format_attr_sdar_mode.attr, 187 &format_attr_sample_mode.attr, 188 &format_attr_thresh_sel.attr, 189 &format_attr_thresh_stop.attr, 190 &format_attr_thresh_start.attr, 191 &format_attr_l2l3_sel.attr, 192 &format_attr_src_sel.attr, 193 &format_attr_invert_bit.attr, 194 &format_attr_src_mask.attr, 195 &format_attr_src_match.attr, 196 NULL, 197 }; 198 199 static struct attribute_group power10_pmu_format_group = { 200 .name = "format", 201 .attrs = power10_pmu_format_attr, 202 }; 203 204 static const struct attribute_group *power10_pmu_attr_groups[] = { 205 &power10_pmu_format_group, 206 &power10_pmu_events_group, 207 NULL, 208 }; 209 210 static int power10_generic_events[] = { 211 [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC, 212 [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL, 213 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL, 214 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL, 215 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1, 216 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1, 217 }; 218 219 static u64 power10_bhrb_filter_map(u64 branch_sample_type) 220 { 221 u64 pmu_bhrb_filter = 0; 222 223 /* BHRB and regular PMU events share the same privilege state 224 * filter configuration. BHRB is always recorded along with a 225 * regular PMU event. As the privilege state filter is handled 226 * in the basic PMC configuration of the accompanying regular 227 * PMU event, we ignore any separate BHRB specific request. 228 */ 229 230 /* No branch filter requested */ 231 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY) 232 return pmu_bhrb_filter; 233 234 /* Invalid branch filter options - HW does not support */ 235 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN) 236 return -1; 237 238 if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) { 239 pmu_bhrb_filter |= POWER10_MMCRA_IFM2; 240 return pmu_bhrb_filter; 241 } 242 243 if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) { 244 pmu_bhrb_filter |= POWER10_MMCRA_IFM3; 245 return pmu_bhrb_filter; 246 } 247 248 if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL) 249 return -1; 250 251 if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) { 252 pmu_bhrb_filter |= POWER10_MMCRA_IFM1; 253 return pmu_bhrb_filter; 254 } 255 256 /* Every thing else is unsupported */ 257 return -1; 258 } 259 260 static void power10_config_bhrb(u64 pmu_bhrb_filter) 261 { 262 pmu_bhrb_filter &= POWER10_MMCRA_BHRB_MASK; 263 264 /* Enable BHRB filter in PMU */ 265 mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter)); 266 } 267 268 #define C(x) PERF_COUNT_HW_CACHE_##x 269 270 /* 271 * Table of generalized cache-related events. 272 * 0 means not supported, -1 means nonsensical, other values 273 * are event codes. 274 */ 275 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { 276 [C(L1D)] = { 277 [C(OP_READ)] = { 278 [C(RESULT_ACCESS)] = PM_LD_REF_L1, 279 [C(RESULT_MISS)] = PM_LD_MISS_L1, 280 }, 281 [C(OP_WRITE)] = { 282 [C(RESULT_ACCESS)] = 0, 283 [C(RESULT_MISS)] = PM_ST_MISS_L1, 284 }, 285 [C(OP_PREFETCH)] = { 286 [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS, 287 [C(RESULT_MISS)] = 0, 288 }, 289 }, 290 [C(L1I)] = { 291 [C(OP_READ)] = { 292 [C(RESULT_ACCESS)] = PM_INST_FROM_L1, 293 [C(RESULT_MISS)] = PM_L1_ICACHE_MISS, 294 }, 295 [C(OP_WRITE)] = { 296 [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS, 297 [C(RESULT_MISS)] = -1, 298 }, 299 [C(OP_PREFETCH)] = { 300 [C(RESULT_ACCESS)] = PM_IC_PREF_REQ, 301 [C(RESULT_MISS)] = 0, 302 }, 303 }, 304 [C(LL)] = { 305 [C(OP_READ)] = { 306 [C(RESULT_ACCESS)] = PM_DATA_FROM_L3, 307 [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS, 308 }, 309 [C(OP_WRITE)] = { 310 [C(RESULT_ACCESS)] = -1, 311 [C(RESULT_MISS)] = -1, 312 }, 313 [C(OP_PREFETCH)] = { 314 [C(RESULT_ACCESS)] = -1, 315 [C(RESULT_MISS)] = 0, 316 }, 317 }, 318 [C(DTLB)] = { 319 [C(OP_READ)] = { 320 [C(RESULT_ACCESS)] = 0, 321 [C(RESULT_MISS)] = PM_DTLB_MISS, 322 }, 323 [C(OP_WRITE)] = { 324 [C(RESULT_ACCESS)] = -1, 325 [C(RESULT_MISS)] = -1, 326 }, 327 [C(OP_PREFETCH)] = { 328 [C(RESULT_ACCESS)] = -1, 329 [C(RESULT_MISS)] = -1, 330 }, 331 }, 332 [C(ITLB)] = { 333 [C(OP_READ)] = { 334 [C(RESULT_ACCESS)] = 0, 335 [C(RESULT_MISS)] = PM_ITLB_MISS, 336 }, 337 [C(OP_WRITE)] = { 338 [C(RESULT_ACCESS)] = -1, 339 [C(RESULT_MISS)] = -1, 340 }, 341 [C(OP_PREFETCH)] = { 342 [C(RESULT_ACCESS)] = -1, 343 [C(RESULT_MISS)] = -1, 344 }, 345 }, 346 [C(BPU)] = { 347 [C(OP_READ)] = { 348 [C(RESULT_ACCESS)] = PM_BR_CMPL, 349 [C(RESULT_MISS)] = PM_BR_MPRED_CMPL, 350 }, 351 [C(OP_WRITE)] = { 352 [C(RESULT_ACCESS)] = -1, 353 [C(RESULT_MISS)] = -1, 354 }, 355 [C(OP_PREFETCH)] = { 356 [C(RESULT_ACCESS)] = -1, 357 [C(RESULT_MISS)] = -1, 358 }, 359 }, 360 [C(NODE)] = { 361 [C(OP_READ)] = { 362 [C(RESULT_ACCESS)] = -1, 363 [C(RESULT_MISS)] = -1, 364 }, 365 [C(OP_WRITE)] = { 366 [C(RESULT_ACCESS)] = -1, 367 [C(RESULT_MISS)] = -1, 368 }, 369 [C(OP_PREFETCH)] = { 370 [C(RESULT_ACCESS)] = -1, 371 [C(RESULT_MISS)] = -1, 372 }, 373 }, 374 }; 375 376 #undef C 377 378 static struct power_pmu power10_pmu = { 379 .name = "POWER10", 380 .n_counter = MAX_PMU_COUNTERS, 381 .add_fields = ISA207_ADD_FIELDS, 382 .test_adder = ISA207_TEST_ADDER, 383 .group_constraint_mask = CNST_CACHE_PMC4_MASK, 384 .group_constraint_val = CNST_CACHE_PMC4_VAL, 385 .compute_mmcr = isa207_compute_mmcr, 386 .config_bhrb = power10_config_bhrb, 387 .bhrb_filter_map = power10_bhrb_filter_map, 388 .get_constraint = isa207_get_constraint, 389 .get_alternatives = power10_get_alternatives, 390 .get_mem_data_src = isa207_get_mem_data_src, 391 .get_mem_weight = isa207_get_mem_weight, 392 .disable_pmc = isa207_disable_pmc, 393 .flags = PPMU_HAS_SIER | PPMU_ARCH_207S | 394 PPMU_ARCH_31, 395 .n_generic = ARRAY_SIZE(power10_generic_events), 396 .generic_events = power10_generic_events, 397 .cache_events = &power10_cache_events, 398 .attr_groups = power10_pmu_attr_groups, 399 .bhrb_nr = 32, 400 }; 401 402 int init_power10_pmu(void) 403 { 404 int rc; 405 406 /* Comes from cpu_specs[] */ 407 if (!cur_cpu_spec->oprofile_cpu_type || 408 strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10")) 409 return -ENODEV; 410 411 rc = register_power_pmu(&power10_pmu); 412 if (rc) 413 return rc; 414 415 /* Tell userspace that EBB is supported */ 416 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB; 417 418 return 0; 419 } 420