1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright 2009 Paul Mackerras, IBM Corporation.
4  * Copyright 2013 Michael Ellerman, IBM Corporation.
5  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
6  */
7 
8 #ifndef _LINUX_POWERPC_PERF_ISA207_COMMON_H_
9 #define _LINUX_POWERPC_PERF_ISA207_COMMON_H_
10 
11 #include <linux/kernel.h>
12 #include <linux/perf_event.h>
13 #include <asm/firmware.h>
14 #include <asm/cputable.h>
15 
16 #include "internal.h"
17 
18 #define EVENT_EBB_MASK		1ull
19 #define EVENT_EBB_SHIFT		PERF_EVENT_CONFIG_EBB_SHIFT
20 #define EVENT_BHRB_MASK		1ull
21 #define EVENT_BHRB_SHIFT	62
22 #define EVENT_WANTS_BHRB	(EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
23 #define EVENT_IFM_MASK		3ull
24 #define EVENT_IFM_SHIFT		60
25 #define EVENT_THR_CMP_SHIFT	40	/* Threshold CMP value */
26 #define EVENT_THR_CMP_MASK	0x3ff
27 #define EVENT_THR_CTL_SHIFT	32	/* Threshold control value (start/stop) */
28 #define EVENT_THR_CTL_MASK	0xffull
29 #define EVENT_THR_SEL_SHIFT	29	/* Threshold select value */
30 #define EVENT_THR_SEL_MASK	0x7
31 #define EVENT_THRESH_SHIFT	29	/* All threshold bits */
32 #define EVENT_THRESH_MASK	0x1fffffull
33 #define EVENT_SAMPLE_SHIFT	24	/* Sampling mode & eligibility */
34 #define EVENT_SAMPLE_MASK	0x1f
35 #define EVENT_CACHE_SEL_SHIFT	20	/* L2/L3 cache select */
36 #define EVENT_CACHE_SEL_MASK	0xf
37 #define EVENT_IS_L1		(4 << EVENT_CACHE_SEL_SHIFT)
38 #define EVENT_PMC_SHIFT		16	/* PMC number (1-based) */
39 #define EVENT_PMC_MASK		0xf
40 #define EVENT_UNIT_SHIFT	12	/* Unit */
41 #define EVENT_UNIT_MASK		0xf
42 #define EVENT_COMBINE_SHIFT	11	/* Combine bit */
43 #define EVENT_COMBINE_MASK	0x1
44 #define EVENT_COMBINE(v)	(((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK)
45 #define EVENT_MARKED_SHIFT	8	/* Marked bit */
46 #define EVENT_MARKED_MASK	0x1
47 #define EVENT_IS_MARKED		(EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
48 #define EVENT_PSEL_MASK		0xff	/* PMCxSEL value */
49 
50 /* Bits defined by Linux */
51 #define EVENT_LINUX_MASK	\
52 	((EVENT_EBB_MASK  << EVENT_EBB_SHIFT)			|	\
53 	 (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)			|	\
54 	 (EVENT_IFM_MASK  << EVENT_IFM_SHIFT))
55 
56 #define EVENT_VALID_MASK	\
57 	((EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)		|	\
58 	 (EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)		|	\
59 	 (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT)	|	\
60 	 (EVENT_PMC_MASK       << EVENT_PMC_SHIFT)		|	\
61 	 (EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)		|	\
62 	 (EVENT_COMBINE_MASK   << EVENT_COMBINE_SHIFT)		|	\
63 	 (EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)		|	\
64 	  EVENT_LINUX_MASK					|	\
65 	  EVENT_PSEL_MASK)
66 
67 #define ONLY_PLM \
68 	(PERF_SAMPLE_BRANCH_USER        |\
69 	 PERF_SAMPLE_BRANCH_KERNEL      |\
70 	 PERF_SAMPLE_BRANCH_HV)
71 
72 /* Contants to support power9 raw encoding format */
73 #define p9_EVENT_COMBINE_SHIFT	10	/* Combine bit */
74 #define p9_EVENT_COMBINE_MASK	0x3ull
75 #define p9_EVENT_COMBINE(v)	(((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK)
76 #define p9_SDAR_MODE_SHIFT	50
77 #define p9_SDAR_MODE_MASK	0x3ull
78 #define p9_SDAR_MODE(v)		(((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK)
79 
80 #define p9_EVENT_VALID_MASK		\
81 	((p9_SDAR_MODE_MASK   << p9_SDAR_MODE_SHIFT		|	\
82 	(EVENT_THRESH_MASK    << EVENT_THRESH_SHIFT)		|	\
83 	(EVENT_SAMPLE_MASK    << EVENT_SAMPLE_SHIFT)		|	\
84 	(EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT)		|	\
85 	(EVENT_PMC_MASK       << EVENT_PMC_SHIFT)		|	\
86 	(EVENT_UNIT_MASK      << EVENT_UNIT_SHIFT)		|	\
87 	(p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT)	|	\
88 	(EVENT_MARKED_MASK    << EVENT_MARKED_SHIFT)		|	\
89 	 EVENT_LINUX_MASK					|	\
90 	 EVENT_PSEL_MASK))
91 
92 /* Contants to support power10 raw encoding format */
93 #define p10_SDAR_MODE_SHIFT		22
94 #define p10_SDAR_MODE_MASK		0x3ull
95 #define p10_SDAR_MODE(v)		(((v) >> p10_SDAR_MODE_SHIFT) & \
96 					p10_SDAR_MODE_MASK)
97 #define p10_EVENT_L2L3_SEL_MASK		0x1f
98 #define p10_L2L3_SEL_SHIFT		3
99 #define p10_L2L3_EVENT_SHIFT		40
100 #define p10_EVENT_THRESH_MASK		0xffffull
101 #define p10_EVENT_CACHE_SEL_MASK	0x3ull
102 #define p10_EVENT_MMCR3_MASK		0x7fffull
103 #define p10_EVENT_MMCR3_SHIFT		45
104 #define p10_EVENT_RADIX_SCOPE_QUAL_SHIFT	9
105 #define p10_EVENT_RADIX_SCOPE_QUAL_MASK	0x1
106 #define p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT	45
107 
108 /* Event Threshold Compare bit constant for power10 in config1 attribute */
109 #define p10_EVENT_THR_CMP_SHIFT        0
110 #define p10_EVENT_THR_CMP_MASK 0x3FFFFull
111 
112 #define p10_EVENT_VALID_MASK		\
113 	((p10_SDAR_MODE_MASK   << p10_SDAR_MODE_SHIFT		|	\
114 	(p10_EVENT_THRESH_MASK  << EVENT_THRESH_SHIFT)		|	\
115 	(EVENT_SAMPLE_MASK     << EVENT_SAMPLE_SHIFT)		|	\
116 	(p10_EVENT_CACHE_SEL_MASK  << EVENT_CACHE_SEL_SHIFT)	|	\
117 	(EVENT_PMC_MASK        << EVENT_PMC_SHIFT)		|	\
118 	(EVENT_UNIT_MASK       << EVENT_UNIT_SHIFT)		|	\
119 	(p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT)	|	\
120 	(p10_EVENT_MMCR3_MASK  << p10_EVENT_MMCR3_SHIFT)	|	\
121 	(EVENT_MARKED_MASK     << EVENT_MARKED_SHIFT)		|	\
122 	(p10_EVENT_RADIX_SCOPE_QUAL_MASK << p10_EVENT_RADIX_SCOPE_QUAL_SHIFT)	|	\
123 	 EVENT_LINUX_MASK					|	\
124 	EVENT_PSEL_MASK))
125 /*
126  * Layout of constraint bits:
127  *
128  *        60        56        52        48        44        40        36        32
129  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
130  *   [   fab_match   ]         [       thresh_cmp      ] [   thresh_ctl    ] [   ]
131  *                                          |                                  |
132  *                           [  thresh_cmp bits for p10]           thresh_sel -*
133  *
134  *        28        24        20        16        12         8         4         0
135  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
136  *               [ ] |   [ ] |  [  sample ]   [     ]   [6] [5]   [4] [3]   [2] [1]
137  *                |  |    |  |                  |
138  *      BHRB IFM -*  |    |  |*radix_scope      |      Count of events for each PMC.
139  *              EBB -*    |                     |        p1, p2, p3, p4, p5, p6.
140  *      L1 I/D qualifier -*                     |
141  *                     nc - number of counters -*
142  *
143  * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
144  * we want the low bit of each field to be added to any existing value.
145  *
146  * Everything else is a value field.
147  */
148 
149 #define CNST_FAB_MATCH_VAL(v)	(((v) & EVENT_THR_CTL_MASK) << 56)
150 #define CNST_FAB_MATCH_MASK	CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
151 
152 /* We just throw all the threshold bits into the constraint */
153 #define CNST_THRESH_VAL(v)	(((v) & EVENT_THRESH_MASK) << 32)
154 #define CNST_THRESH_MASK	CNST_THRESH_VAL(EVENT_THRESH_MASK)
155 
156 #define CNST_THRESH_CTL_SEL_VAL(v)	(((v) & 0x7ffull) << 32)
157 #define CNST_THRESH_CTL_SEL_MASK	CNST_THRESH_CTL_SEL_VAL(0x7ff)
158 
159 #define p10_CNST_THRESH_CMP_VAL(v) (((v) & 0x7ffull) << 43)
160 #define p10_CNST_THRESH_CMP_MASK   p10_CNST_THRESH_CMP_VAL(0x7ff)
161 
162 #define CNST_EBB_VAL(v)		(((v) & EVENT_EBB_MASK) << 24)
163 #define CNST_EBB_MASK		CNST_EBB_VAL(EVENT_EBB_MASK)
164 
165 #define CNST_IFM_VAL(v)		(((v) & EVENT_IFM_MASK) << 25)
166 #define CNST_IFM_MASK		CNST_IFM_VAL(EVENT_IFM_MASK)
167 
168 #define CNST_L1_QUAL_VAL(v)	(((v) & 3) << 22)
169 #define CNST_L1_QUAL_MASK	CNST_L1_QUAL_VAL(3)
170 
171 #define CNST_SAMPLE_VAL(v)	(((v) & EVENT_SAMPLE_MASK) << 16)
172 #define CNST_SAMPLE_MASK	CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
173 
174 #define CNST_CACHE_GROUP_VAL(v)	(((v) & 0xffull) << 55)
175 #define CNST_CACHE_GROUP_MASK	CNST_CACHE_GROUP_VAL(0xff)
176 #define CNST_CACHE_PMC4_VAL	(1ull << 54)
177 #define CNST_CACHE_PMC4_MASK	CNST_CACHE_PMC4_VAL
178 
179 #define CNST_L2L3_GROUP_VAL(v)	(((v) & 0x1full) << 55)
180 #define CNST_L2L3_GROUP_MASK	CNST_L2L3_GROUP_VAL(0x1f)
181 
182 #define CNST_RADIX_SCOPE_GROUP_VAL(v)	(((v) & 0x1ull) << 21)
183 #define CNST_RADIX_SCOPE_GROUP_MASK	CNST_RADIX_SCOPE_GROUP_VAL(1)
184 
185 /*
186  * For NC we are counting up to 4 events. This requires three bits, and we need
187  * the fifth event to overflow and set the 4th bit. To achieve that we bias the
188  * fields by 3 in test_adder.
189  */
190 #define CNST_NC_SHIFT		12
191 #define CNST_NC_VAL		(1 << CNST_NC_SHIFT)
192 #define CNST_NC_MASK		(8 << CNST_NC_SHIFT)
193 #define ISA207_TEST_ADDER	(3 << CNST_NC_SHIFT)
194 
195 /*
196  * For the per-PMC fields we have two bits. The low bit is added, so if two
197  * events ask for the same PMC the sum will overflow, setting the high bit,
198  * indicating an error. So our mask sets the high bit.
199  */
200 #define CNST_PMC_SHIFT(pmc)	((pmc - 1) * 2)
201 #define CNST_PMC_VAL(pmc)	(1 << CNST_PMC_SHIFT(pmc))
202 #define CNST_PMC_MASK(pmc)	(2 << CNST_PMC_SHIFT(pmc))
203 
204 /* Our add_fields is defined as: */
205 #define ISA207_ADD_FIELDS	\
206 	CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
207 	CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
208 
209 /* Bits in MMCR1 for PowerISA v2.07 */
210 #define MMCR1_UNIT_SHIFT(pmc)		(60 - (4 * ((pmc) - 1)))
211 #define MMCR1_COMBINE_SHIFT(pmc)	(35 - ((pmc) - 1))
212 #define MMCR1_PMCSEL_SHIFT(pmc)		(24 - (((pmc) - 1)) * 8)
213 #define MMCR1_FAB_SHIFT			36
214 #define MMCR1_DC_IC_QUAL_MASK		0x3
215 #define MMCR1_DC_IC_QUAL_SHIFT		46
216 
217 /* MMCR1 Combine bits macro for power9 */
218 #define p9_MMCR1_COMBINE_SHIFT(pmc)	(38 - ((pmc - 1) * 2))
219 
220 /* Bits in MMCRA for PowerISA v2.07 */
221 #define MMCRA_SAMP_MODE_SHIFT		1
222 #define MMCRA_SAMP_ELIG_SHIFT		4
223 #define MMCRA_THR_CTL_SHIFT		8
224 #define MMCRA_THR_SEL_SHIFT		16
225 #define MMCRA_THR_CMP_SHIFT		32
226 #define MMCRA_SDAR_MODE_SHIFT		42
227 #define MMCRA_SDAR_MODE_TLB		(1ull << MMCRA_SDAR_MODE_SHIFT)
228 #define MMCRA_SDAR_MODE_NO_UPDATES	~(0x3ull << MMCRA_SDAR_MODE_SHIFT)
229 #define MMCRA_SDAR_MODE_DCACHE		(2ull << MMCRA_SDAR_MODE_SHIFT)
230 #define MMCRA_IFM_SHIFT			30
231 #define MMCRA_THR_CTR_MANT_SHIFT	19
232 #define MMCRA_THR_CTR_MANT_MASK		0x7Ful
233 #define MMCRA_THR_CTR_MANT(v)		(((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
234 						MMCRA_THR_CTR_MANT_MASK)
235 
236 #define MMCRA_THR_CTR_EXP_SHIFT		27
237 #define MMCRA_THR_CTR_EXP_MASK		0x7ul
238 #define MMCRA_THR_CTR_EXP(v)		(((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
239 						MMCRA_THR_CTR_EXP_MASK)
240 
241 #define P10_MMCRA_THR_CTR_MANT_MASK	0xFFul
242 #define P10_MMCRA_THR_CTR_MANT(v)	(((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
243 						P10_MMCRA_THR_CTR_MANT_MASK)
244 
245 /* MMCRA Threshold Compare bit constant for power9 */
246 #define p9_MMCRA_THR_CMP_SHIFT	45
247 
248 /* Bits in MMCR2 for PowerISA v2.07 */
249 #define MMCR2_FCS(pmc)			(1ull << (63 - (((pmc) - 1) * 9)))
250 #define MMCR2_FCP(pmc)			(1ull << (62 - (((pmc) - 1) * 9)))
251 #define MMCR2_FCH(pmc)			(1ull << (57 - (((pmc) - 1) * 9)))
252 
253 #define MAX_ALT				2
254 #define MAX_PMU_COUNTERS		6
255 
256 /* Bits in MMCR3 for PowerISA v3.10 */
257 #define MMCR3_SHIFT(pmc)		(49 - (15 * ((pmc) - 1)))
258 
259 #define ISA207_SIER_TYPE_SHIFT		15
260 #define ISA207_SIER_TYPE_MASK		(0x7ull << ISA207_SIER_TYPE_SHIFT)
261 
262 #define ISA207_SIER_LDST_SHIFT		1
263 #define ISA207_SIER_LDST_MASK		(0x7ull << ISA207_SIER_LDST_SHIFT)
264 
265 #define ISA207_SIER_DATA_SRC_SHIFT	53
266 #define ISA207_SIER_DATA_SRC_MASK	(0x7ull << ISA207_SIER_DATA_SRC_SHIFT)
267 
268 #define P(a, b)				PERF_MEM_S(a, b)
269 #define PH(a, b)			(P(LVL, HIT) | P(a, b))
270 #define PM(a, b)			(P(LVL, MISS) | P(a, b))
271 
272 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1);
273 int isa207_compute_mmcr(u64 event[], int n_ev,
274 				unsigned int hwc[], struct mmcr_regs *mmcr,
275 				struct perf_event *pevents[], u32 flags);
276 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr);
277 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
278 					const unsigned int ev_alt[][MAX_ALT]);
279 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
280 							struct pt_regs *regs);
281 void isa207_get_mem_weight(u64 *weight);
282 
283 #endif
284