1 /* 2 * Copyright 2009 Paul Mackerras, IBM Corporation. 3 * Copyright 2013 Michael Ellerman, IBM Corporation. 4 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or any later version. 10 */ 11 12 #ifndef _LINUX_POWERPC_PERF_ISA207_COMMON_H_ 13 #define _LINUX_POWERPC_PERF_ISA207_COMMON_H_ 14 15 #include <linux/kernel.h> 16 #include <linux/perf_event.h> 17 #include <asm/firmware.h> 18 #include <asm/cputable.h> 19 20 #define EVENT_EBB_MASK 1ull 21 #define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT 22 #define EVENT_BHRB_MASK 1ull 23 #define EVENT_BHRB_SHIFT 62 24 #define EVENT_WANTS_BHRB (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT) 25 #define EVENT_IFM_MASK 3ull 26 #define EVENT_IFM_SHIFT 60 27 #define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */ 28 #define EVENT_THR_CMP_MASK 0x3ff 29 #define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */ 30 #define EVENT_THR_CTL_MASK 0xffull 31 #define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */ 32 #define EVENT_THR_SEL_MASK 0x7 33 #define EVENT_THRESH_SHIFT 29 /* All threshold bits */ 34 #define EVENT_THRESH_MASK 0x1fffffull 35 #define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */ 36 #define EVENT_SAMPLE_MASK 0x1f 37 #define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */ 38 #define EVENT_CACHE_SEL_MASK 0xf 39 #define EVENT_IS_L1 (4 << EVENT_CACHE_SEL_SHIFT) 40 #define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */ 41 #define EVENT_PMC_MASK 0xf 42 #define EVENT_UNIT_SHIFT 12 /* Unit */ 43 #define EVENT_UNIT_MASK 0xf 44 #define EVENT_COMBINE_SHIFT 11 /* Combine bit */ 45 #define EVENT_COMBINE_MASK 0x1 46 #define EVENT_COMBINE(v) (((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK) 47 #define EVENT_MARKED_SHIFT 8 /* Marked bit */ 48 #define EVENT_MARKED_MASK 0x1 49 #define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) 50 #define EVENT_PSEL_MASK 0xff /* PMCxSEL value */ 51 52 /* Bits defined by Linux */ 53 #define EVENT_LINUX_MASK \ 54 ((EVENT_EBB_MASK << EVENT_EBB_SHIFT) | \ 55 (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT) | \ 56 (EVENT_IFM_MASK << EVENT_IFM_SHIFT)) 57 58 #define EVENT_VALID_MASK \ 59 ((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \ 60 (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \ 61 (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \ 62 (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \ 63 (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \ 64 (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \ 65 (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \ 66 EVENT_LINUX_MASK | \ 67 EVENT_PSEL_MASK) 68 69 #define ONLY_PLM \ 70 (PERF_SAMPLE_BRANCH_USER |\ 71 PERF_SAMPLE_BRANCH_KERNEL |\ 72 PERF_SAMPLE_BRANCH_HV) 73 74 /* Contants to support power9 raw encoding format */ 75 #define p9_EVENT_COMBINE_SHIFT 10 /* Combine bit */ 76 #define p9_EVENT_COMBINE_MASK 0x3ull 77 #define p9_EVENT_COMBINE(v) (((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK) 78 #define p9_SDAR_MODE_SHIFT 50 79 #define p9_SDAR_MODE_MASK 0x3ull 80 #define p9_SDAR_MODE(v) (((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK) 81 82 #define p9_EVENT_VALID_MASK \ 83 ((p9_SDAR_MODE_MASK << p9_SDAR_MODE_SHIFT | \ 84 (EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \ 85 (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \ 86 (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \ 87 (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \ 88 (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \ 89 (p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \ 90 (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \ 91 EVENT_LINUX_MASK | \ 92 EVENT_PSEL_MASK)) 93 94 /* 95 * Layout of constraint bits: 96 * 97 * 60 56 52 48 44 40 36 32 98 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 99 * [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ] 100 * | 101 * thresh_sel -* 102 * 103 * 28 24 20 16 12 8 4 0 104 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | 105 * [ ] | [ ] [ sample ] [ ] [6] [5] [4] [3] [2] [1] 106 * | | | | 107 * BHRB IFM -* | | | Count of events for each PMC. 108 * EBB -* | | p1, p2, p3, p4, p5, p6. 109 * L1 I/D qualifier -* | 110 * nc - number of counters -* 111 * 112 * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints 113 * we want the low bit of each field to be added to any existing value. 114 * 115 * Everything else is a value field. 116 */ 117 118 #define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56) 119 #define CNST_FAB_MATCH_MASK CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK) 120 121 /* We just throw all the threshold bits into the constraint */ 122 #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32) 123 #define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK) 124 125 #define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24) 126 #define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK) 127 128 #define CNST_IFM_VAL(v) (((v) & EVENT_IFM_MASK) << 25) 129 #define CNST_IFM_MASK CNST_IFM_VAL(EVENT_IFM_MASK) 130 131 #define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22) 132 #define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3) 133 134 #define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16) 135 #define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK) 136 137 #define CNST_CACHE_GROUP_VAL(v) (((v) & 0xffull) << 55) 138 #define CNST_CACHE_GROUP_MASK CNST_CACHE_GROUP_VAL(0xff) 139 #define CNST_CACHE_PMC4_VAL (1ull << 54) 140 #define CNST_CACHE_PMC4_MASK CNST_CACHE_PMC4_VAL 141 142 /* 143 * For NC we are counting up to 4 events. This requires three bits, and we need 144 * the fifth event to overflow and set the 4th bit. To achieve that we bias the 145 * fields by 3 in test_adder. 146 */ 147 #define CNST_NC_SHIFT 12 148 #define CNST_NC_VAL (1 << CNST_NC_SHIFT) 149 #define CNST_NC_MASK (8 << CNST_NC_SHIFT) 150 #define ISA207_TEST_ADDER (3 << CNST_NC_SHIFT) 151 152 /* 153 * For the per-PMC fields we have two bits. The low bit is added, so if two 154 * events ask for the same PMC the sum will overflow, setting the high bit, 155 * indicating an error. So our mask sets the high bit. 156 */ 157 #define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2) 158 #define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc)) 159 #define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc)) 160 161 /* Our add_fields is defined as: */ 162 #define ISA207_ADD_FIELDS \ 163 CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \ 164 CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL 165 166 /* Bits in MMCR1 for PowerISA v2.07 */ 167 #define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1))) 168 #define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1)) 169 #define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8) 170 #define MMCR1_FAB_SHIFT 36 171 #define MMCR1_DC_IC_QUAL_MASK 0x3 172 #define MMCR1_DC_IC_QUAL_SHIFT 46 173 174 /* MMCR1 Combine bits macro for power9 */ 175 #define p9_MMCR1_COMBINE_SHIFT(pmc) (38 - ((pmc - 1) * 2)) 176 177 /* Bits in MMCRA for PowerISA v2.07 */ 178 #define MMCRA_SAMP_MODE_SHIFT 1 179 #define MMCRA_SAMP_ELIG_SHIFT 4 180 #define MMCRA_THR_CTL_SHIFT 8 181 #define MMCRA_THR_SEL_SHIFT 16 182 #define MMCRA_THR_CMP_SHIFT 32 183 #define MMCRA_SDAR_MODE_SHIFT 42 184 #define MMCRA_SDAR_MODE_TLB (1ull << MMCRA_SDAR_MODE_SHIFT) 185 #define MMCRA_SDAR_MODE_NO_UPDATES ~(0x3ull << MMCRA_SDAR_MODE_SHIFT) 186 #define MMCRA_SDAR_MODE_DCACHE (2ull << MMCRA_SDAR_MODE_SHIFT) 187 #define MMCRA_IFM_SHIFT 30 188 #define MMCRA_THR_CTR_MANT_SHIFT 19 189 #define MMCRA_THR_CTR_MANT_MASK 0x7Ful 190 #define MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\ 191 MMCRA_THR_CTR_MANT_MASK) 192 193 #define MMCRA_THR_CTR_EXP_SHIFT 27 194 #define MMCRA_THR_CTR_EXP_MASK 0x7ul 195 #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\ 196 MMCRA_THR_CTR_EXP_MASK) 197 198 /* MMCR1 Threshold Compare bit constant for power9 */ 199 #define p9_MMCRA_THR_CMP_SHIFT 45 200 201 /* Bits in MMCR2 for PowerISA v2.07 */ 202 #define MMCR2_FCS(pmc) (1ull << (63 - (((pmc) - 1) * 9))) 203 #define MMCR2_FCP(pmc) (1ull << (62 - (((pmc) - 1) * 9))) 204 #define MMCR2_FCH(pmc) (1ull << (57 - (((pmc) - 1) * 9))) 205 206 #define MAX_ALT 2 207 #define MAX_PMU_COUNTERS 6 208 209 #define ISA207_SIER_TYPE_SHIFT 15 210 #define ISA207_SIER_TYPE_MASK (0x7ull << ISA207_SIER_TYPE_SHIFT) 211 212 #define ISA207_SIER_LDST_SHIFT 1 213 #define ISA207_SIER_LDST_MASK (0x7ull << ISA207_SIER_LDST_SHIFT) 214 215 #define ISA207_SIER_DATA_SRC_SHIFT 53 216 #define ISA207_SIER_DATA_SRC_MASK (0x7ull << ISA207_SIER_DATA_SRC_SHIFT) 217 218 #define P(a, b) PERF_MEM_S(a, b) 219 #define PH(a, b) (P(LVL, HIT) | P(a, b)) 220 #define PM(a, b) (P(LVL, MISS) | P(a, b)) 221 222 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp); 223 int isa207_compute_mmcr(u64 event[], int n_ev, 224 unsigned int hwc[], unsigned long mmcr[], 225 struct perf_event *pevents[]); 226 void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]); 227 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, 228 const unsigned int ev_alt[][MAX_ALT]); 229 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 230 struct pt_regs *regs); 231 void isa207_get_mem_weight(u64 *weight); 232 233 #endif 234