1 /* 2 * Common Performance counter support functions for PowerISA v2.07 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * Copyright 2013 Michael Ellerman, IBM Corporation. 6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 #include "isa207-common.h" 14 15 PMU_FORMAT_ATTR(event, "config:0-49"); 16 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 17 PMU_FORMAT_ATTR(mark, "config:8"); 18 PMU_FORMAT_ATTR(combine, "config:11"); 19 PMU_FORMAT_ATTR(unit, "config:12-15"); 20 PMU_FORMAT_ATTR(pmc, "config:16-19"); 21 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 22 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 23 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 24 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 25 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 26 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 27 28 struct attribute *isa207_pmu_format_attr[] = { 29 &format_attr_event.attr, 30 &format_attr_pmcxsel.attr, 31 &format_attr_mark.attr, 32 &format_attr_combine.attr, 33 &format_attr_unit.attr, 34 &format_attr_pmc.attr, 35 &format_attr_cache_sel.attr, 36 &format_attr_sample_mode.attr, 37 &format_attr_thresh_sel.attr, 38 &format_attr_thresh_stop.attr, 39 &format_attr_thresh_start.attr, 40 &format_attr_thresh_cmp.attr, 41 NULL, 42 }; 43 44 struct attribute_group isa207_pmu_format_group = { 45 .name = "format", 46 .attrs = isa207_pmu_format_attr, 47 }; 48 49 static inline bool event_is_fab_match(u64 event) 50 { 51 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 52 event &= 0xff0fe; 53 54 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 55 return (event == 0x30056 || event == 0x4f052); 56 } 57 58 static bool is_event_valid(u64 event) 59 { 60 u64 valid_mask = EVENT_VALID_MASK; 61 62 if (cpu_has_feature(CPU_FTR_ARCH_300)) 63 valid_mask = p9_EVENT_VALID_MASK; 64 65 return !(event & ~valid_mask); 66 } 67 68 static inline bool is_event_marked(u64 event) 69 { 70 if (event & EVENT_IS_MARKED) 71 return true; 72 73 return false; 74 } 75 76 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) 77 { 78 /* 79 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in 80 * continous sampling mode. 81 * 82 * Incase of Power8: 83 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling 84 * mode and will be un-changed when setting MMCRA[63] (Marked events). 85 * 86 * Incase of Power9: 87 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'), 88 * or if group already have any marked events. 89 * For rest 90 * MMCRA[SDAR_MODE] will be set from event code. 91 * If sdar_mode from event is zero, default to 0b01. Hardware 92 * requires that we set a non-zero value. 93 */ 94 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 95 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) 96 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES; 97 else if (p9_SDAR_MODE(event)) 98 *mmcra |= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT; 99 else 100 *mmcra |= MMCRA_SDAR_MODE_DCACHE; 101 } else 102 *mmcra |= MMCRA_SDAR_MODE_TLB; 103 } 104 105 static u64 thresh_cmp_val(u64 value) 106 { 107 if (cpu_has_feature(CPU_FTR_ARCH_300)) 108 return value << p9_MMCRA_THR_CMP_SHIFT; 109 110 return value << MMCRA_THR_CMP_SHIFT; 111 } 112 113 static unsigned long combine_from_event(u64 event) 114 { 115 if (cpu_has_feature(CPU_FTR_ARCH_300)) 116 return p9_EVENT_COMBINE(event); 117 118 return EVENT_COMBINE(event); 119 } 120 121 static unsigned long combine_shift(unsigned long pmc) 122 { 123 if (cpu_has_feature(CPU_FTR_ARCH_300)) 124 return p9_MMCR1_COMBINE_SHIFT(pmc); 125 126 return MMCR1_COMBINE_SHIFT(pmc); 127 } 128 129 static inline bool event_is_threshold(u64 event) 130 { 131 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 132 } 133 134 static bool is_thresh_cmp_valid(u64 event) 135 { 136 unsigned int cmp, exp; 137 138 /* 139 * Check the mantissa upper two bits are not zero, unless the 140 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 141 */ 142 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 143 exp = cmp >> 7; 144 145 if (exp && (cmp & 0x60) == 0) 146 return false; 147 148 return true; 149 } 150 151 static unsigned int dc_ic_rld_quad_l1_sel(u64 event) 152 { 153 unsigned int cache; 154 155 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; 156 return cache; 157 } 158 159 static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 160 { 161 u64 ret = PERF_MEM_NA; 162 163 switch(idx) { 164 case 0: 165 /* Nothing to do */ 166 break; 167 case 1: 168 ret = PH(LVL, L1); 169 break; 170 case 2: 171 ret = PH(LVL, L2); 172 break; 173 case 3: 174 ret = PH(LVL, L3); 175 break; 176 case 4: 177 if (sub_idx <= 1) 178 ret = PH(LVL, LOC_RAM); 179 else if (sub_idx > 1 && sub_idx <= 2) 180 ret = PH(LVL, REM_RAM1); 181 else 182 ret = PH(LVL, REM_RAM2); 183 ret |= P(SNOOP, HIT); 184 break; 185 case 5: 186 ret = PH(LVL, REM_CCE1); 187 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4)) 188 ret |= P(SNOOP, HIT); 189 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5)) 190 ret |= P(SNOOP, HITM); 191 break; 192 case 6: 193 ret = PH(LVL, REM_CCE2); 194 if ((sub_idx == 0) || (sub_idx == 2)) 195 ret |= P(SNOOP, HIT); 196 else if ((sub_idx == 1) || (sub_idx == 3)) 197 ret |= P(SNOOP, HITM); 198 break; 199 case 7: 200 ret = PM(LVL, L1); 201 break; 202 } 203 204 return ret; 205 } 206 207 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 208 struct pt_regs *regs) 209 { 210 u64 idx; 211 u32 sub_idx; 212 u64 sier; 213 u64 val; 214 215 /* Skip if no SIER support */ 216 if (!(flags & PPMU_HAS_SIER)) { 217 dsrc->val = 0; 218 return; 219 } 220 221 sier = mfspr(SPRN_SIER); 222 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 223 if (val == 1 || val == 2) { 224 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT; 225 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT; 226 227 dsrc->val = isa207_find_source(idx, sub_idx); 228 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); 229 } 230 } 231 232 void isa207_get_mem_weight(u64 *weight) 233 { 234 u64 mmcra = mfspr(SPRN_MMCRA); 235 u64 exp = MMCRA_THR_CTR_EXP(mmcra); 236 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra); 237 u64 sier = mfspr(SPRN_SIER); 238 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 239 240 if (val == 0 || val == 7) 241 *weight = 0; 242 else 243 *weight = mantissa << (2 * exp); 244 } 245 246 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 247 { 248 unsigned int unit, pmc, cache, ebb; 249 unsigned long mask, value; 250 251 mask = value = 0; 252 253 if (!is_event_valid(event)) 254 return -1; 255 256 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 257 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 258 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; 259 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 260 261 if (pmc) { 262 u64 base_event; 263 264 if (pmc > 6) 265 return -1; 266 267 /* Ignore Linux defined bits when checking event below */ 268 base_event = event & ~EVENT_LINUX_MASK; 269 270 if (pmc >= 5 && base_event != 0x500fa && 271 base_event != 0x600f4) 272 return -1; 273 274 mask |= CNST_PMC_MASK(pmc); 275 value |= CNST_PMC_VAL(pmc); 276 } 277 278 if (pmc <= 4) { 279 /* 280 * Add to number of counters in use. Note this includes events with 281 * a PMC of 0 - they still need a PMC, it's just assigned later. 282 * Don't count events on PMC 5 & 6, there is only one valid event 283 * on each of those counters, and they are handled above. 284 */ 285 mask |= CNST_NC_MASK; 286 value |= CNST_NC_VAL; 287 } 288 289 if (unit >= 6 && unit <= 9) { 290 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 291 mask |= CNST_CACHE_GROUP_MASK; 292 value |= CNST_CACHE_GROUP_VAL(event & 0xff); 293 294 mask |= CNST_CACHE_PMC4_MASK; 295 if (pmc == 4) 296 value |= CNST_CACHE_PMC4_VAL; 297 } else if (cache & 0x7) { 298 /* 299 * L2/L3 events contain a cache selector field, which is 300 * supposed to be programmed into MMCRC. However MMCRC is only 301 * HV writable, and there is no API for guest kernels to modify 302 * it. The solution is for the hypervisor to initialise the 303 * field to zeroes, and for us to only ever allow events that 304 * have a cache selector of zero. The bank selector (bit 3) is 305 * irrelevant, as long as the rest of the value is 0. 306 */ 307 return -1; 308 } 309 310 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { 311 mask |= CNST_L1_QUAL_MASK; 312 value |= CNST_L1_QUAL_VAL(cache); 313 } 314 315 if (is_event_marked(event)) { 316 mask |= CNST_SAMPLE_MASK; 317 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 318 } 319 320 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 321 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 322 mask |= CNST_THRESH_MASK; 323 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 324 } 325 } else { 326 /* 327 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 328 * the threshold control bits are used for the match value. 329 */ 330 if (event_is_fab_match(event)) { 331 mask |= CNST_FAB_MATCH_MASK; 332 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 333 } else { 334 if (!is_thresh_cmp_valid(event)) 335 return -1; 336 337 mask |= CNST_THRESH_MASK; 338 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 339 } 340 } 341 342 if (!pmc && ebb) 343 /* EBB events must specify the PMC */ 344 return -1; 345 346 if (event & EVENT_WANTS_BHRB) { 347 if (!ebb) 348 /* Only EBB events can request BHRB */ 349 return -1; 350 351 mask |= CNST_IFM_MASK; 352 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 353 } 354 355 /* 356 * All events must agree on EBB, either all request it or none. 357 * EBB events are pinned & exclusive, so this should never actually 358 * hit, but we leave it as a fallback in case. 359 */ 360 mask |= CNST_EBB_VAL(ebb); 361 value |= CNST_EBB_MASK; 362 363 *maskp = mask; 364 *valp = value; 365 366 return 0; 367 } 368 369 int isa207_compute_mmcr(u64 event[], int n_ev, 370 unsigned int hwc[], unsigned long mmcr[], 371 struct perf_event *pevents[]) 372 { 373 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 374 unsigned int pmc, pmc_inuse; 375 int i; 376 377 pmc_inuse = 0; 378 379 /* First pass to count resource use */ 380 for (i = 0; i < n_ev; ++i) { 381 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 382 if (pmc) 383 pmc_inuse |= 1 << pmc; 384 } 385 386 mmcra = mmcr1 = mmcr2 = 0; 387 388 /* Second pass: assign PMCs, set all MMCR1 fields */ 389 for (i = 0; i < n_ev; ++i) { 390 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 391 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 392 combine = combine_from_event(event[i]); 393 psel = event[i] & EVENT_PSEL_MASK; 394 395 if (!pmc) { 396 for (pmc = 1; pmc <= 4; ++pmc) { 397 if (!(pmc_inuse & (1 << pmc))) 398 break; 399 } 400 401 pmc_inuse |= 1 << pmc; 402 } 403 404 if (pmc <= 4) { 405 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 406 mmcr1 |= combine << combine_shift(pmc); 407 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 408 } 409 410 /* In continuous sampling mode, update SDAR on TLB miss */ 411 mmcra_sdar_mode(event[i], &mmcra); 412 413 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 414 cache = dc_ic_rld_quad_l1_sel(event[i]); 415 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 416 } else { 417 if (event[i] & EVENT_IS_L1) { 418 cache = dc_ic_rld_quad_l1_sel(event[i]); 419 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 420 } 421 } 422 423 if (is_event_marked(event[i])) { 424 mmcra |= MMCRA_SAMPLE_ENABLE; 425 426 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 427 if (val) { 428 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 429 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 430 } 431 } 432 433 /* 434 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 435 * the threshold bits are used for the match value. 436 */ 437 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 438 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 439 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 440 } else { 441 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 442 mmcra |= val << MMCRA_THR_CTL_SHIFT; 443 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 444 mmcra |= val << MMCRA_THR_SEL_SHIFT; 445 val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 446 mmcra |= thresh_cmp_val(val); 447 } 448 449 if (event[i] & EVENT_WANTS_BHRB) { 450 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 451 mmcra |= val << MMCRA_IFM_SHIFT; 452 } 453 454 if (pevents[i]->attr.exclude_user) 455 mmcr2 |= MMCR2_FCP(pmc); 456 457 if (pevents[i]->attr.exclude_hv) 458 mmcr2 |= MMCR2_FCH(pmc); 459 460 if (pevents[i]->attr.exclude_kernel) { 461 if (cpu_has_feature(CPU_FTR_HVMODE)) 462 mmcr2 |= MMCR2_FCH(pmc); 463 else 464 mmcr2 |= MMCR2_FCS(pmc); 465 } 466 467 hwc[i] = pmc - 1; 468 } 469 470 /* Return MMCRx values */ 471 mmcr[0] = 0; 472 473 /* pmc_inuse is 1-based */ 474 if (pmc_inuse & 2) 475 mmcr[0] = MMCR0_PMC1CE; 476 477 if (pmc_inuse & 0x7c) 478 mmcr[0] |= MMCR0_PMCjCE; 479 480 /* If we're not using PMC 5 or 6, freeze them */ 481 if (!(pmc_inuse & 0x60)) 482 mmcr[0] |= MMCR0_FC56; 483 484 mmcr[1] = mmcr1; 485 mmcr[2] = mmcra; 486 mmcr[3] = mmcr2; 487 488 return 0; 489 } 490 491 void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 492 { 493 if (pmc <= 3) 494 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 495 } 496 497 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 498 { 499 int i, j; 500 501 for (i = 0; i < size; ++i) { 502 if (event < ev_alt[i][0]) 503 break; 504 505 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 506 if (event == ev_alt[i][j]) 507 return i; 508 } 509 510 return -1; 511 } 512 513 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, 514 const unsigned int ev_alt[][MAX_ALT]) 515 { 516 int i, j, num_alt = 0; 517 u64 alt_event; 518 519 alt[num_alt++] = event; 520 i = find_alternative(event, ev_alt, size); 521 if (i >= 0) { 522 /* Filter out the original event, it's already in alt[0] */ 523 for (j = 0; j < MAX_ALT; ++j) { 524 alt_event = ev_alt[i][j]; 525 if (alt_event && alt_event != event) 526 alt[num_alt++] = alt_event; 527 } 528 } 529 530 if (flags & PPMU_ONLY_COUNT_RUN) { 531 /* 532 * We're only counting in RUN state, so PM_CYC is equivalent to 533 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. 534 */ 535 j = num_alt; 536 for (i = 0; i < num_alt; ++i) { 537 switch (alt[i]) { 538 case 0x1e: /* PMC_CYC */ 539 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 540 break; 541 case 0x600f4: 542 alt[j++] = 0x1e; 543 break; 544 case 0x2: /* PM_INST_CMPL */ 545 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 546 break; 547 case 0x500fa: 548 alt[j++] = 0x2; 549 break; 550 } 551 } 552 num_alt = j; 553 } 554 555 return num_alt; 556 } 557