1 /* 2 * Common Performance counter support functions for PowerISA v2.07 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * Copyright 2013 Michael Ellerman, IBM Corporation. 6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 #include "isa207-common.h" 14 15 PMU_FORMAT_ATTR(event, "config:0-49"); 16 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 17 PMU_FORMAT_ATTR(mark, "config:8"); 18 PMU_FORMAT_ATTR(combine, "config:11"); 19 PMU_FORMAT_ATTR(unit, "config:12-15"); 20 PMU_FORMAT_ATTR(pmc, "config:16-19"); 21 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 22 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 23 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 24 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 25 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 26 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 27 28 struct attribute *isa207_pmu_format_attr[] = { 29 &format_attr_event.attr, 30 &format_attr_pmcxsel.attr, 31 &format_attr_mark.attr, 32 &format_attr_combine.attr, 33 &format_attr_unit.attr, 34 &format_attr_pmc.attr, 35 &format_attr_cache_sel.attr, 36 &format_attr_sample_mode.attr, 37 &format_attr_thresh_sel.attr, 38 &format_attr_thresh_stop.attr, 39 &format_attr_thresh_start.attr, 40 &format_attr_thresh_cmp.attr, 41 NULL, 42 }; 43 44 struct attribute_group isa207_pmu_format_group = { 45 .name = "format", 46 .attrs = isa207_pmu_format_attr, 47 }; 48 49 static inline bool event_is_fab_match(u64 event) 50 { 51 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 52 event &= 0xff0fe; 53 54 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 55 return (event == 0x30056 || event == 0x4f052); 56 } 57 58 static bool is_event_valid(u64 event) 59 { 60 u64 valid_mask = EVENT_VALID_MASK; 61 62 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 63 valid_mask = p9_EVENT_VALID_MASK; 64 65 return !(event & ~valid_mask); 66 } 67 68 static inline bool is_event_marked(u64 event) 69 { 70 if (event & EVENT_IS_MARKED) 71 return true; 72 73 return false; 74 } 75 76 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) 77 { 78 /* 79 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in 80 * continous sampling mode. 81 * 82 * Incase of Power8: 83 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling 84 * mode and will be un-changed when setting MMCRA[63] (Marked events). 85 * 86 * Incase of Power9: 87 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'), 88 * or if group already have any marked events. 89 * Non-Marked events (for DD1): 90 * MMCRA[SDAR_MODE] will be set to 0b01 91 * For rest 92 * MMCRA[SDAR_MODE] will be set from event code. 93 * If sdar_mode from event is zero, default to 0b01. Hardware 94 * requires that we set a non-zero value. 95 */ 96 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 97 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) 98 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES; 99 else if (!cpu_has_feature(CPU_FTR_POWER9_DD1) && p9_SDAR_MODE(event)) 100 *mmcra |= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT; 101 else 102 *mmcra |= MMCRA_SDAR_MODE_DCACHE; 103 } else 104 *mmcra |= MMCRA_SDAR_MODE_TLB; 105 } 106 107 static u64 thresh_cmp_val(u64 value) 108 { 109 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 110 return value << p9_MMCRA_THR_CMP_SHIFT; 111 112 return value << MMCRA_THR_CMP_SHIFT; 113 } 114 115 static unsigned long combine_from_event(u64 event) 116 { 117 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 118 return p9_EVENT_COMBINE(event); 119 120 return EVENT_COMBINE(event); 121 } 122 123 static unsigned long combine_shift(unsigned long pmc) 124 { 125 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 126 return p9_MMCR1_COMBINE_SHIFT(pmc); 127 128 return MMCR1_COMBINE_SHIFT(pmc); 129 } 130 131 static inline bool event_is_threshold(u64 event) 132 { 133 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 134 } 135 136 static bool is_thresh_cmp_valid(u64 event) 137 { 138 unsigned int cmp, exp; 139 140 /* 141 * Check the mantissa upper two bits are not zero, unless the 142 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 143 */ 144 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 145 exp = cmp >> 7; 146 147 if (exp && (cmp & 0x60) == 0) 148 return false; 149 150 return true; 151 } 152 153 static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 154 { 155 u64 ret = PERF_MEM_NA; 156 157 switch(idx) { 158 case 0: 159 /* Nothing to do */ 160 break; 161 case 1: 162 ret = PH(LVL, L1); 163 break; 164 case 2: 165 ret = PH(LVL, L2); 166 break; 167 case 3: 168 ret = PH(LVL, L3); 169 break; 170 case 4: 171 if (sub_idx <= 1) 172 ret = PH(LVL, LOC_RAM); 173 else if (sub_idx > 1 && sub_idx <= 2) 174 ret = PH(LVL, REM_RAM1); 175 else 176 ret = PH(LVL, REM_RAM2); 177 ret |= P(SNOOP, HIT); 178 break; 179 case 5: 180 ret = PH(LVL, REM_CCE1); 181 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4)) 182 ret |= P(SNOOP, HIT); 183 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5)) 184 ret |= P(SNOOP, HITM); 185 break; 186 case 6: 187 ret = PH(LVL, REM_CCE2); 188 if ((sub_idx == 0) || (sub_idx == 2)) 189 ret |= P(SNOOP, HIT); 190 else if ((sub_idx == 1) || (sub_idx == 3)) 191 ret |= P(SNOOP, HITM); 192 break; 193 case 7: 194 ret = PM(LVL, L1); 195 break; 196 } 197 198 return ret; 199 } 200 201 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 202 struct pt_regs *regs) 203 { 204 u64 idx; 205 u32 sub_idx; 206 u64 sier; 207 u64 val; 208 209 /* Skip if no SIER support */ 210 if (!(flags & PPMU_HAS_SIER)) { 211 dsrc->val = 0; 212 return; 213 } 214 215 sier = mfspr(SPRN_SIER); 216 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 217 if (val == 1 || val == 2) { 218 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT; 219 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT; 220 221 dsrc->val = isa207_find_source(idx, sub_idx); 222 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); 223 } 224 } 225 226 void isa207_get_mem_weight(u64 *weight) 227 { 228 u64 mmcra = mfspr(SPRN_MMCRA); 229 u64 exp = MMCRA_THR_CTR_EXP(mmcra); 230 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra); 231 232 *weight = mantissa << (2 * exp); 233 } 234 235 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 236 { 237 unsigned int unit, pmc, cache, ebb; 238 unsigned long mask, value; 239 240 mask = value = 0; 241 242 if (!is_event_valid(event)) 243 return -1; 244 245 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 246 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 247 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; 248 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 249 250 if (pmc) { 251 u64 base_event; 252 253 if (pmc > 6) 254 return -1; 255 256 /* Ignore Linux defined bits when checking event below */ 257 base_event = event & ~EVENT_LINUX_MASK; 258 259 if (pmc >= 5 && base_event != 0x500fa && 260 base_event != 0x600f4) 261 return -1; 262 263 mask |= CNST_PMC_MASK(pmc); 264 value |= CNST_PMC_VAL(pmc); 265 } 266 267 if (pmc <= 4) { 268 /* 269 * Add to number of counters in use. Note this includes events with 270 * a PMC of 0 - they still need a PMC, it's just assigned later. 271 * Don't count events on PMC 5 & 6, there is only one valid event 272 * on each of those counters, and they are handled above. 273 */ 274 mask |= CNST_NC_MASK; 275 value |= CNST_NC_VAL; 276 } 277 278 if (unit >= 6 && unit <= 9) { 279 /* 280 * L2/L3 events contain a cache selector field, which is 281 * supposed to be programmed into MMCRC. However MMCRC is only 282 * HV writable, and there is no API for guest kernels to modify 283 * it. The solution is for the hypervisor to initialise the 284 * field to zeroes, and for us to only ever allow events that 285 * have a cache selector of zero. The bank selector (bit 3) is 286 * irrelevant, as long as the rest of the value is 0. 287 */ 288 if (cache & 0x7) 289 return -1; 290 291 } else if (event & EVENT_IS_L1) { 292 mask |= CNST_L1_QUAL_MASK; 293 value |= CNST_L1_QUAL_VAL(cache); 294 } 295 296 if (is_event_marked(event)) { 297 mask |= CNST_SAMPLE_MASK; 298 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 299 } 300 301 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 302 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 303 mask |= CNST_THRESH_MASK; 304 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 305 } 306 } else { 307 /* 308 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 309 * the threshold control bits are used for the match value. 310 */ 311 if (event_is_fab_match(event)) { 312 mask |= CNST_FAB_MATCH_MASK; 313 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 314 } else { 315 if (!is_thresh_cmp_valid(event)) 316 return -1; 317 318 mask |= CNST_THRESH_MASK; 319 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 320 } 321 } 322 323 if (!pmc && ebb) 324 /* EBB events must specify the PMC */ 325 return -1; 326 327 if (event & EVENT_WANTS_BHRB) { 328 if (!ebb) 329 /* Only EBB events can request BHRB */ 330 return -1; 331 332 mask |= CNST_IFM_MASK; 333 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 334 } 335 336 /* 337 * All events must agree on EBB, either all request it or none. 338 * EBB events are pinned & exclusive, so this should never actually 339 * hit, but we leave it as a fallback in case. 340 */ 341 mask |= CNST_EBB_VAL(ebb); 342 value |= CNST_EBB_MASK; 343 344 *maskp = mask; 345 *valp = value; 346 347 return 0; 348 } 349 350 int isa207_compute_mmcr(u64 event[], int n_ev, 351 unsigned int hwc[], unsigned long mmcr[], 352 struct perf_event *pevents[]) 353 { 354 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 355 unsigned int pmc, pmc_inuse; 356 int i; 357 358 pmc_inuse = 0; 359 360 /* First pass to count resource use */ 361 for (i = 0; i < n_ev; ++i) { 362 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 363 if (pmc) 364 pmc_inuse |= 1 << pmc; 365 } 366 367 mmcra = mmcr1 = mmcr2 = 0; 368 369 /* Second pass: assign PMCs, set all MMCR1 fields */ 370 for (i = 0; i < n_ev; ++i) { 371 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 372 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 373 combine = combine_from_event(event[i]); 374 psel = event[i] & EVENT_PSEL_MASK; 375 376 if (!pmc) { 377 for (pmc = 1; pmc <= 4; ++pmc) { 378 if (!(pmc_inuse & (1 << pmc))) 379 break; 380 } 381 382 pmc_inuse |= 1 << pmc; 383 } 384 385 if (pmc <= 4) { 386 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 387 mmcr1 |= combine << combine_shift(pmc); 388 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 389 } 390 391 /* In continuous sampling mode, update SDAR on TLB miss */ 392 mmcra_sdar_mode(event[i], &mmcra); 393 394 if (event[i] & EVENT_IS_L1) { 395 cache = event[i] >> EVENT_CACHE_SEL_SHIFT; 396 mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; 397 cache >>= 1; 398 mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; 399 } 400 401 if (is_event_marked(event[i])) { 402 mmcra |= MMCRA_SAMPLE_ENABLE; 403 404 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 405 if (val) { 406 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 407 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 408 } 409 } 410 411 /* 412 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 413 * the threshold bits are used for the match value. 414 */ 415 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 416 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 417 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 418 } else { 419 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 420 mmcra |= val << MMCRA_THR_CTL_SHIFT; 421 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 422 mmcra |= val << MMCRA_THR_SEL_SHIFT; 423 val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 424 mmcra |= thresh_cmp_val(val); 425 } 426 427 if (event[i] & EVENT_WANTS_BHRB) { 428 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 429 mmcra |= val << MMCRA_IFM_SHIFT; 430 } 431 432 if (pevents[i]->attr.exclude_user) 433 mmcr2 |= MMCR2_FCP(pmc); 434 435 if (pevents[i]->attr.exclude_hv) 436 mmcr2 |= MMCR2_FCH(pmc); 437 438 if (pevents[i]->attr.exclude_kernel) { 439 if (cpu_has_feature(CPU_FTR_HVMODE)) 440 mmcr2 |= MMCR2_FCH(pmc); 441 else 442 mmcr2 |= MMCR2_FCS(pmc); 443 } 444 445 hwc[i] = pmc - 1; 446 } 447 448 /* Return MMCRx values */ 449 mmcr[0] = 0; 450 451 /* pmc_inuse is 1-based */ 452 if (pmc_inuse & 2) 453 mmcr[0] = MMCR0_PMC1CE; 454 455 if (pmc_inuse & 0x7c) 456 mmcr[0] |= MMCR0_PMCjCE; 457 458 /* If we're not using PMC 5 or 6, freeze them */ 459 if (!(pmc_inuse & 0x60)) 460 mmcr[0] |= MMCR0_FC56; 461 462 mmcr[1] = mmcr1; 463 mmcr[2] = mmcra; 464 mmcr[3] = mmcr2; 465 466 return 0; 467 } 468 469 void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 470 { 471 if (pmc <= 3) 472 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 473 } 474 475 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 476 { 477 int i, j; 478 479 for (i = 0; i < size; ++i) { 480 if (event < ev_alt[i][0]) 481 break; 482 483 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 484 if (event == ev_alt[i][j]) 485 return i; 486 } 487 488 return -1; 489 } 490 491 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, 492 const unsigned int ev_alt[][MAX_ALT]) 493 { 494 int i, j, num_alt = 0; 495 u64 alt_event; 496 497 alt[num_alt++] = event; 498 i = find_alternative(event, ev_alt, size); 499 if (i >= 0) { 500 /* Filter out the original event, it's already in alt[0] */ 501 for (j = 0; j < MAX_ALT; ++j) { 502 alt_event = ev_alt[i][j]; 503 if (alt_event && alt_event != event) 504 alt[num_alt++] = alt_event; 505 } 506 } 507 508 if (flags & PPMU_ONLY_COUNT_RUN) { 509 /* 510 * We're only counting in RUN state, so PM_CYC is equivalent to 511 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. 512 */ 513 j = num_alt; 514 for (i = 0; i < num_alt; ++i) { 515 switch (alt[i]) { 516 case 0x1e: /* PMC_CYC */ 517 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 518 break; 519 case 0x600f4: 520 alt[j++] = 0x1e; 521 break; 522 case 0x2: /* PM_INST_CMPL */ 523 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 524 break; 525 case 0x500fa: 526 alt[j++] = 0x2; 527 break; 528 } 529 } 530 num_alt = j; 531 } 532 533 return num_alt; 534 } 535