1 /* 2 * Common Performance counter support functions for PowerISA v2.07 processors. 3 * 4 * Copyright 2009 Paul Mackerras, IBM Corporation. 5 * Copyright 2013 Michael Ellerman, IBM Corporation. 6 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 11 * 2 of the License, or (at your option) any later version. 12 */ 13 #include "isa207-common.h" 14 15 PMU_FORMAT_ATTR(event, "config:0-49"); 16 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 17 PMU_FORMAT_ATTR(mark, "config:8"); 18 PMU_FORMAT_ATTR(combine, "config:11"); 19 PMU_FORMAT_ATTR(unit, "config:12-15"); 20 PMU_FORMAT_ATTR(pmc, "config:16-19"); 21 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 22 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 23 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 24 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 25 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 26 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 27 28 struct attribute *isa207_pmu_format_attr[] = { 29 &format_attr_event.attr, 30 &format_attr_pmcxsel.attr, 31 &format_attr_mark.attr, 32 &format_attr_combine.attr, 33 &format_attr_unit.attr, 34 &format_attr_pmc.attr, 35 &format_attr_cache_sel.attr, 36 &format_attr_sample_mode.attr, 37 &format_attr_thresh_sel.attr, 38 &format_attr_thresh_stop.attr, 39 &format_attr_thresh_start.attr, 40 &format_attr_thresh_cmp.attr, 41 NULL, 42 }; 43 44 struct attribute_group isa207_pmu_format_group = { 45 .name = "format", 46 .attrs = isa207_pmu_format_attr, 47 }; 48 49 static inline bool event_is_fab_match(u64 event) 50 { 51 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 52 event &= 0xff0fe; 53 54 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 55 return (event == 0x30056 || event == 0x4f052); 56 } 57 58 static bool is_event_valid(u64 event) 59 { 60 u64 valid_mask = EVENT_VALID_MASK; 61 62 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 63 valid_mask = p9_EVENT_VALID_MASK; 64 65 return !(event & ~valid_mask); 66 } 67 68 static u64 mmcra_sdar_mode(u64 event) 69 { 70 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 71 return p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT; 72 73 return MMCRA_SDAR_MODE_TLB; 74 } 75 76 static u64 thresh_cmp_val(u64 value) 77 { 78 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 79 return value << p9_MMCRA_THR_CMP_SHIFT; 80 81 return value << MMCRA_THR_CMP_SHIFT; 82 } 83 84 static unsigned long combine_from_event(u64 event) 85 { 86 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 87 return p9_EVENT_COMBINE(event); 88 89 return EVENT_COMBINE(event); 90 } 91 92 static unsigned long combine_shift(unsigned long pmc) 93 { 94 if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 95 return p9_MMCR1_COMBINE_SHIFT(pmc); 96 97 return MMCR1_COMBINE_SHIFT(pmc); 98 } 99 100 static inline bool event_is_threshold(u64 event) 101 { 102 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 103 } 104 105 static bool is_thresh_cmp_valid(u64 event) 106 { 107 unsigned int cmp, exp; 108 109 /* 110 * Check the mantissa upper two bits are not zero, unless the 111 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 112 */ 113 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 114 exp = cmp >> 7; 115 116 if (exp && (cmp & 0x60) == 0) 117 return false; 118 119 return true; 120 } 121 122 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 123 { 124 unsigned int unit, pmc, cache, ebb; 125 unsigned long mask, value; 126 127 mask = value = 0; 128 129 if (!is_event_valid(event)) 130 return -1; 131 132 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 133 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 134 cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; 135 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 136 137 if (pmc) { 138 u64 base_event; 139 140 if (pmc > 6) 141 return -1; 142 143 /* Ignore Linux defined bits when checking event below */ 144 base_event = event & ~EVENT_LINUX_MASK; 145 146 if (pmc >= 5 && base_event != 0x500fa && 147 base_event != 0x600f4) 148 return -1; 149 150 mask |= CNST_PMC_MASK(pmc); 151 value |= CNST_PMC_VAL(pmc); 152 } 153 154 if (pmc <= 4) { 155 /* 156 * Add to number of counters in use. Note this includes events with 157 * a PMC of 0 - they still need a PMC, it's just assigned later. 158 * Don't count events on PMC 5 & 6, there is only one valid event 159 * on each of those counters, and they are handled above. 160 */ 161 mask |= CNST_NC_MASK; 162 value |= CNST_NC_VAL; 163 } 164 165 if (unit >= 6 && unit <= 9) { 166 /* 167 * L2/L3 events contain a cache selector field, which is 168 * supposed to be programmed into MMCRC. However MMCRC is only 169 * HV writable, and there is no API for guest kernels to modify 170 * it. The solution is for the hypervisor to initialise the 171 * field to zeroes, and for us to only ever allow events that 172 * have a cache selector of zero. The bank selector (bit 3) is 173 * irrelevant, as long as the rest of the value is 0. 174 */ 175 if (cache & 0x7) 176 return -1; 177 178 } else if (event & EVENT_IS_L1) { 179 mask |= CNST_L1_QUAL_MASK; 180 value |= CNST_L1_QUAL_VAL(cache); 181 } 182 183 if (event & EVENT_IS_MARKED) { 184 mask |= CNST_SAMPLE_MASK; 185 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 186 } 187 188 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 189 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 190 mask |= CNST_THRESH_MASK; 191 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 192 } 193 } else { 194 /* 195 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 196 * the threshold control bits are used for the match value. 197 */ 198 if (event_is_fab_match(event)) { 199 mask |= CNST_FAB_MATCH_MASK; 200 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 201 } else { 202 if (!is_thresh_cmp_valid(event)) 203 return -1; 204 205 mask |= CNST_THRESH_MASK; 206 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 207 } 208 } 209 210 if (!pmc && ebb) 211 /* EBB events must specify the PMC */ 212 return -1; 213 214 if (event & EVENT_WANTS_BHRB) { 215 if (!ebb) 216 /* Only EBB events can request BHRB */ 217 return -1; 218 219 mask |= CNST_IFM_MASK; 220 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 221 } 222 223 /* 224 * All events must agree on EBB, either all request it or none. 225 * EBB events are pinned & exclusive, so this should never actually 226 * hit, but we leave it as a fallback in case. 227 */ 228 mask |= CNST_EBB_VAL(ebb); 229 value |= CNST_EBB_MASK; 230 231 *maskp = mask; 232 *valp = value; 233 234 return 0; 235 } 236 237 int isa207_compute_mmcr(u64 event[], int n_ev, 238 unsigned int hwc[], unsigned long mmcr[], 239 struct perf_event *pevents[]) 240 { 241 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 242 unsigned int pmc, pmc_inuse; 243 int i; 244 245 pmc_inuse = 0; 246 247 /* First pass to count resource use */ 248 for (i = 0; i < n_ev; ++i) { 249 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 250 if (pmc) 251 pmc_inuse |= 1 << pmc; 252 } 253 254 mmcra = mmcr1 = mmcr2 = 0; 255 256 /* Second pass: assign PMCs, set all MMCR1 fields */ 257 for (i = 0; i < n_ev; ++i) { 258 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 259 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 260 combine = combine_from_event(event[i]); 261 psel = event[i] & EVENT_PSEL_MASK; 262 263 if (!pmc) { 264 for (pmc = 1; pmc <= 4; ++pmc) { 265 if (!(pmc_inuse & (1 << pmc))) 266 break; 267 } 268 269 pmc_inuse |= 1 << pmc; 270 } 271 272 if (pmc <= 4) { 273 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 274 mmcr1 |= combine << combine_shift(pmc); 275 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 276 } 277 278 /* In continuous sampling mode, update SDAR on TLB miss */ 279 mmcra |= mmcra_sdar_mode(event[i]); 280 281 if (event[i] & EVENT_IS_L1) { 282 cache = event[i] >> EVENT_CACHE_SEL_SHIFT; 283 mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; 284 cache >>= 1; 285 mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; 286 } 287 288 if (event[i] & EVENT_IS_MARKED) { 289 mmcra |= MMCRA_SAMPLE_ENABLE; 290 291 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 292 if (val) { 293 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 294 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 295 } 296 } 297 298 /* 299 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 300 * the threshold bits are used for the match value. 301 */ 302 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 303 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 304 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 305 } else { 306 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 307 mmcra |= val << MMCRA_THR_CTL_SHIFT; 308 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 309 mmcra |= val << MMCRA_THR_SEL_SHIFT; 310 val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 311 mmcra |= thresh_cmp_val(val); 312 } 313 314 if (event[i] & EVENT_WANTS_BHRB) { 315 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 316 mmcra |= val << MMCRA_IFM_SHIFT; 317 } 318 319 if (pevents[i]->attr.exclude_user) 320 mmcr2 |= MMCR2_FCP(pmc); 321 322 if (pevents[i]->attr.exclude_hv) 323 mmcr2 |= MMCR2_FCH(pmc); 324 325 if (pevents[i]->attr.exclude_kernel) { 326 if (cpu_has_feature(CPU_FTR_HVMODE)) 327 mmcr2 |= MMCR2_FCH(pmc); 328 else 329 mmcr2 |= MMCR2_FCS(pmc); 330 } 331 332 hwc[i] = pmc - 1; 333 } 334 335 /* Return MMCRx values */ 336 mmcr[0] = 0; 337 338 /* pmc_inuse is 1-based */ 339 if (pmc_inuse & 2) 340 mmcr[0] = MMCR0_PMC1CE; 341 342 if (pmc_inuse & 0x7c) 343 mmcr[0] |= MMCR0_PMCjCE; 344 345 /* If we're not using PMC 5 or 6, freeze them */ 346 if (!(pmc_inuse & 0x60)) 347 mmcr[0] |= MMCR0_FC56; 348 349 mmcr[1] = mmcr1; 350 mmcr[2] = mmcra; 351 mmcr[3] = mmcr2; 352 353 return 0; 354 } 355 356 void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 357 { 358 if (pmc <= 3) 359 mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 360 } 361 362 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 363 { 364 int i, j; 365 366 for (i = 0; i < size; ++i) { 367 if (event < ev_alt[i][0]) 368 break; 369 370 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 371 if (event == ev_alt[i][j]) 372 return i; 373 } 374 375 return -1; 376 } 377 378 int isa207_get_alternatives(u64 event, u64 alt[], 379 const unsigned int ev_alt[][MAX_ALT], int size) 380 { 381 int i, j, num_alt = 0; 382 u64 alt_event; 383 384 alt[num_alt++] = event; 385 i = find_alternative(event, ev_alt, size); 386 if (i >= 0) { 387 /* Filter out the original event, it's already in alt[0] */ 388 for (j = 0; j < MAX_ALT; ++j) { 389 alt_event = ev_alt[i][j]; 390 if (alt_event && alt_event != event) 391 alt[num_alt++] = alt_event; 392 } 393 } 394 395 return num_alt; 396 } 397