1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Common Performance counter support functions for PowerISA v2.07 processors. 4 * 5 * Copyright 2009 Paul Mackerras, IBM Corporation. 6 * Copyright 2013 Michael Ellerman, IBM Corporation. 7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 8 */ 9 #include "isa207-common.h" 10 11 PMU_FORMAT_ATTR(event, "config:0-49"); 12 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 13 PMU_FORMAT_ATTR(mark, "config:8"); 14 PMU_FORMAT_ATTR(combine, "config:11"); 15 PMU_FORMAT_ATTR(unit, "config:12-15"); 16 PMU_FORMAT_ATTR(pmc, "config:16-19"); 17 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 18 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 19 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 20 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 21 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 22 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 23 24 static struct attribute *isa207_pmu_format_attr[] = { 25 &format_attr_event.attr, 26 &format_attr_pmcxsel.attr, 27 &format_attr_mark.attr, 28 &format_attr_combine.attr, 29 &format_attr_unit.attr, 30 &format_attr_pmc.attr, 31 &format_attr_cache_sel.attr, 32 &format_attr_sample_mode.attr, 33 &format_attr_thresh_sel.attr, 34 &format_attr_thresh_stop.attr, 35 &format_attr_thresh_start.attr, 36 &format_attr_thresh_cmp.attr, 37 NULL, 38 }; 39 40 struct attribute_group isa207_pmu_format_group = { 41 .name = "format", 42 .attrs = isa207_pmu_format_attr, 43 }; 44 45 static inline bool event_is_fab_match(u64 event) 46 { 47 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 48 event &= 0xff0fe; 49 50 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 51 return (event == 0x30056 || event == 0x4f052); 52 } 53 54 static bool is_event_valid(u64 event) 55 { 56 u64 valid_mask = EVENT_VALID_MASK; 57 58 if (cpu_has_feature(CPU_FTR_ARCH_31)) 59 valid_mask = p10_EVENT_VALID_MASK; 60 else if (cpu_has_feature(CPU_FTR_ARCH_300)) 61 valid_mask = p9_EVENT_VALID_MASK; 62 63 return !(event & ~valid_mask); 64 } 65 66 static inline bool is_event_marked(u64 event) 67 { 68 if (event & EVENT_IS_MARKED) 69 return true; 70 71 return false; 72 } 73 74 static unsigned long sdar_mod_val(u64 event) 75 { 76 if (cpu_has_feature(CPU_FTR_ARCH_31)) 77 return p10_SDAR_MODE(event); 78 79 return p9_SDAR_MODE(event); 80 } 81 82 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) 83 { 84 /* 85 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in 86 * continous sampling mode. 87 * 88 * Incase of Power8: 89 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling 90 * mode and will be un-changed when setting MMCRA[63] (Marked events). 91 * 92 * Incase of Power9/power10: 93 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'), 94 * or if group already have any marked events. 95 * For rest 96 * MMCRA[SDAR_MODE] will be set from event code. 97 * If sdar_mode from event is zero, default to 0b01. Hardware 98 * requires that we set a non-zero value. 99 */ 100 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) 102 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES; 103 else if (sdar_mod_val(event)) 104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT; 105 else 106 *mmcra |= MMCRA_SDAR_MODE_DCACHE; 107 } else 108 *mmcra |= MMCRA_SDAR_MODE_TLB; 109 } 110 111 static u64 p10_thresh_cmp_val(u64 value) 112 { 113 int exp = 0; 114 u64 result = value; 115 116 if (!value) 117 return value; 118 119 /* 120 * Incase of P10, thresh_cmp value is not part of raw event code 121 * and provided via attr.config1 parameter. To program threshold in MMCRA, 122 * take a 18 bit number N and shift right 2 places and increment 123 * the exponent E by 1 until the upper 10 bits of N are zero. 124 * Write E to the threshold exponent and write the lower 8 bits of N 125 * to the threshold mantissa. 126 * The max threshold that can be written is 261120. 127 */ 128 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 129 if (value > 261120) 130 value = 261120; 131 while ((64 - __builtin_clzl(value)) > 8) { 132 exp++; 133 value >>= 2; 134 } 135 136 /* 137 * Note that it is invalid to write a mantissa with the 138 * upper 2 bits of mantissa being zero, unless the 139 * exponent is also zero. 140 */ 141 if (!(value & 0xC0) && exp) 142 result = 0; 143 else 144 result = (exp << 8) | value; 145 } 146 return result; 147 } 148 149 static u64 thresh_cmp_val(u64 value) 150 { 151 if (cpu_has_feature(CPU_FTR_ARCH_31)) 152 value = p10_thresh_cmp_val(value); 153 154 /* 155 * Since location of threshold compare bits in MMCRA 156 * is different for p8, using different shift value. 157 */ 158 if (cpu_has_feature(CPU_FTR_ARCH_300)) 159 return value << p9_MMCRA_THR_CMP_SHIFT; 160 else 161 return value << MMCRA_THR_CMP_SHIFT; 162 } 163 164 static unsigned long combine_from_event(u64 event) 165 { 166 if (cpu_has_feature(CPU_FTR_ARCH_300)) 167 return p9_EVENT_COMBINE(event); 168 169 return EVENT_COMBINE(event); 170 } 171 172 static unsigned long combine_shift(unsigned long pmc) 173 { 174 if (cpu_has_feature(CPU_FTR_ARCH_300)) 175 return p9_MMCR1_COMBINE_SHIFT(pmc); 176 177 return MMCR1_COMBINE_SHIFT(pmc); 178 } 179 180 static inline bool event_is_threshold(u64 event) 181 { 182 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 183 } 184 185 static bool is_thresh_cmp_valid(u64 event) 186 { 187 unsigned int cmp, exp; 188 189 if (cpu_has_feature(CPU_FTR_ARCH_31)) 190 return p10_thresh_cmp_val(event) != 0; 191 192 /* 193 * Check the mantissa upper two bits are not zero, unless the 194 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 195 */ 196 197 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 198 exp = cmp >> 7; 199 200 if (exp && (cmp & 0x60) == 0) 201 return false; 202 203 return true; 204 } 205 206 static unsigned int dc_ic_rld_quad_l1_sel(u64 event) 207 { 208 unsigned int cache; 209 210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; 211 return cache; 212 } 213 214 static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 215 { 216 u64 ret = PERF_MEM_NA; 217 218 switch(idx) { 219 case 0: 220 /* Nothing to do */ 221 break; 222 case 1: 223 ret = PH(LVL, L1); 224 break; 225 case 2: 226 ret = PH(LVL, L2); 227 break; 228 case 3: 229 ret = PH(LVL, L3); 230 break; 231 case 4: 232 if (sub_idx <= 1) 233 ret = PH(LVL, LOC_RAM); 234 else if (sub_idx > 1 && sub_idx <= 2) 235 ret = PH(LVL, REM_RAM1); 236 else 237 ret = PH(LVL, REM_RAM2); 238 ret |= P(SNOOP, HIT); 239 break; 240 case 5: 241 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 242 ret = REM | P(HOPS, 0); 243 244 if (sub_idx == 0 || sub_idx == 4) 245 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HIT); 246 else if (sub_idx == 1 || sub_idx == 5) 247 ret |= PH(LVL, L2) | LEVEL(L2) | P(SNOOP, HITM); 248 else if (sub_idx == 2 || sub_idx == 6) 249 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); 250 else if (sub_idx == 3 || sub_idx == 7) 251 ret |= PH(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); 252 } else { 253 if (sub_idx == 0) 254 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HIT) | P(HOPS, 0); 255 else if (sub_idx == 1) 256 ret = PH(LVL, L2) | LEVEL(L2) | REM | P(SNOOP, HITM) | P(HOPS, 0); 257 else if (sub_idx == 2 || sub_idx == 4) 258 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HIT) | P(HOPS, 0); 259 else if (sub_idx == 3 || sub_idx == 5) 260 ret = PH(LVL, L3) | LEVEL(L3) | REM | P(SNOOP, HITM) | P(HOPS, 0); 261 } 262 break; 263 case 6: 264 ret = PH(LVL, REM_CCE2); 265 if ((sub_idx == 0) || (sub_idx == 2)) 266 ret |= P(SNOOP, HIT); 267 else if ((sub_idx == 1) || (sub_idx == 3)) 268 ret |= P(SNOOP, HITM); 269 break; 270 case 7: 271 ret = PM(LVL, L1); 272 break; 273 } 274 275 return ret; 276 } 277 278 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 279 struct pt_regs *regs) 280 { 281 u64 idx; 282 u32 sub_idx; 283 u64 sier; 284 u64 val; 285 286 /* Skip if no SIER support */ 287 if (!(flags & PPMU_HAS_SIER)) { 288 dsrc->val = 0; 289 return; 290 } 291 292 sier = mfspr(SPRN_SIER); 293 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 294 if (val != 1 && val != 2 && !(val == 7 && cpu_has_feature(CPU_FTR_ARCH_31))) 295 return; 296 297 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT; 298 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT; 299 300 dsrc->val = isa207_find_source(idx, sub_idx); 301 if (val == 7) { 302 u64 mmcra; 303 u32 op_type; 304 305 /* 306 * Type 0b111 denotes either larx or stcx instruction. Use the 307 * MMCRA sampling bits [57:59] along with the type value 308 * to determine the exact instruction type. If the sampling 309 * criteria is neither load or store, set the type as default 310 * to NA. 311 */ 312 mmcra = mfspr(SPRN_MMCRA); 313 314 op_type = (mmcra >> MMCRA_SAMP_ELIG_SHIFT) & MMCRA_SAMP_ELIG_MASK; 315 switch (op_type) { 316 case 5: 317 dsrc->val |= P(OP, LOAD); 318 break; 319 case 7: 320 dsrc->val |= P(OP, STORE); 321 break; 322 default: 323 dsrc->val |= P(OP, NA); 324 break; 325 } 326 } else { 327 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); 328 } 329 } 330 331 void isa207_get_mem_weight(u64 *weight, u64 type) 332 { 333 union perf_sample_weight *weight_fields; 334 u64 weight_lat; 335 u64 mmcra = mfspr(SPRN_MMCRA); 336 u64 exp = MMCRA_THR_CTR_EXP(mmcra); 337 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra); 338 u64 sier = mfspr(SPRN_SIER); 339 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 340 341 if (cpu_has_feature(CPU_FTR_ARCH_31)) 342 mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); 343 344 if (val == 0 || (val == 7 && !cpu_has_feature(CPU_FTR_ARCH_31))) 345 weight_lat = 0; 346 else 347 weight_lat = mantissa << (2 * exp); 348 349 /* 350 * Use 64 bit weight field (full) if sample type is 351 * WEIGHT. 352 * 353 * if sample type is WEIGHT_STRUCT: 354 * - store memory latency in the lower 32 bits. 355 * - For ISA v3.1, use remaining two 16 bit fields of 356 * perf_sample_weight to store cycle counter values 357 * from sier2. 358 */ 359 weight_fields = (union perf_sample_weight *)weight; 360 if (type & PERF_SAMPLE_WEIGHT) 361 weight_fields->full = weight_lat; 362 else { 363 weight_fields->var1_dw = (u32)weight_lat; 364 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 365 weight_fields->var2_w = P10_SIER2_FINISH_CYC(mfspr(SPRN_SIER2)); 366 weight_fields->var3_w = P10_SIER2_DISPATCH_CYC(mfspr(SPRN_SIER2)); 367 } 368 } 369 } 370 371 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1) 372 { 373 unsigned int unit, pmc, cache, ebb; 374 unsigned long mask, value; 375 376 mask = value = 0; 377 378 if (!is_event_valid(event)) 379 return -1; 380 381 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 382 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 383 if (cpu_has_feature(CPU_FTR_ARCH_31)) 384 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 385 p10_EVENT_CACHE_SEL_MASK; 386 else 387 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 388 EVENT_CACHE_SEL_MASK; 389 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 390 391 if (pmc) { 392 u64 base_event; 393 394 if (pmc > 6) 395 return -1; 396 397 /* Ignore Linux defined bits when checking event below */ 398 base_event = event & ~EVENT_LINUX_MASK; 399 400 if (pmc >= 5 && base_event != 0x500fa && 401 base_event != 0x600f4) 402 return -1; 403 404 mask |= CNST_PMC_MASK(pmc); 405 value |= CNST_PMC_VAL(pmc); 406 407 /* 408 * PMC5 and PMC6 are used to count cycles and instructions and 409 * they do not support most of the constraint bits. Add a check 410 * to exclude PMC5/6 from most of the constraints except for 411 * EBB/BHRB. 412 */ 413 if (pmc >= 5) 414 goto ebb_bhrb; 415 } 416 417 if (pmc <= 4) { 418 /* 419 * Add to number of counters in use. Note this includes events with 420 * a PMC of 0 - they still need a PMC, it's just assigned later. 421 * Don't count events on PMC 5 & 6, there is only one valid event 422 * on each of those counters, and they are handled above. 423 */ 424 mask |= CNST_NC_MASK; 425 value |= CNST_NC_VAL; 426 } 427 428 if (unit >= 6 && unit <= 9) { 429 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 430 if (unit == 6) { 431 mask |= CNST_L2L3_GROUP_MASK; 432 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT); 433 } 434 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 435 mask |= CNST_CACHE_GROUP_MASK; 436 value |= CNST_CACHE_GROUP_VAL(event & 0xff); 437 438 mask |= CNST_CACHE_PMC4_MASK; 439 if (pmc == 4) 440 value |= CNST_CACHE_PMC4_VAL; 441 } else if (cache & 0x7) { 442 /* 443 * L2/L3 events contain a cache selector field, which is 444 * supposed to be programmed into MMCRC. However MMCRC is only 445 * HV writable, and there is no API for guest kernels to modify 446 * it. The solution is for the hypervisor to initialise the 447 * field to zeroes, and for us to only ever allow events that 448 * have a cache selector of zero. The bank selector (bit 3) is 449 * irrelevant, as long as the rest of the value is 0. 450 */ 451 return -1; 452 } 453 454 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { 455 mask |= CNST_L1_QUAL_MASK; 456 value |= CNST_L1_QUAL_VAL(cache); 457 } 458 459 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 460 mask |= CNST_RADIX_SCOPE_GROUP_MASK; 461 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT); 462 } 463 464 if (is_event_marked(event)) { 465 mask |= CNST_SAMPLE_MASK; 466 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 467 } 468 469 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 470 if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) { 471 mask |= CNST_THRESH_CTL_SEL_MASK; 472 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT); 473 mask |= p10_CNST_THRESH_CMP_MASK; 474 value |= p10_CNST_THRESH_CMP_VAL(p10_thresh_cmp_val(event_config1)); 475 } 476 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 477 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 478 mask |= CNST_THRESH_MASK; 479 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 480 } 481 } else { 482 /* 483 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 484 * the threshold control bits are used for the match value. 485 */ 486 if (event_is_fab_match(event)) { 487 mask |= CNST_FAB_MATCH_MASK; 488 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 489 } else { 490 if (!is_thresh_cmp_valid(event)) 491 return -1; 492 493 mask |= CNST_THRESH_MASK; 494 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 495 } 496 } 497 498 ebb_bhrb: 499 if (!pmc && ebb) 500 /* EBB events must specify the PMC */ 501 return -1; 502 503 if (event & EVENT_WANTS_BHRB) { 504 if (!ebb) 505 /* Only EBB events can request BHRB */ 506 return -1; 507 508 mask |= CNST_IFM_MASK; 509 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 510 } 511 512 /* 513 * All events must agree on EBB, either all request it or none. 514 * EBB events are pinned & exclusive, so this should never actually 515 * hit, but we leave it as a fallback in case. 516 */ 517 mask |= CNST_EBB_MASK; 518 value |= CNST_EBB_VAL(ebb); 519 520 *maskp = mask; 521 *valp = value; 522 523 return 0; 524 } 525 526 int isa207_compute_mmcr(u64 event[], int n_ev, 527 unsigned int hwc[], struct mmcr_regs *mmcr, 528 struct perf_event *pevents[], u32 flags) 529 { 530 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 531 unsigned long mmcr3; 532 unsigned int pmc, pmc_inuse; 533 int i; 534 535 pmc_inuse = 0; 536 537 /* First pass to count resource use */ 538 for (i = 0; i < n_ev; ++i) { 539 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 540 if (pmc) 541 pmc_inuse |= 1 << pmc; 542 } 543 544 mmcra = mmcr1 = mmcr2 = mmcr3 = 0; 545 546 /* 547 * Disable bhrb unless explicitly requested 548 * by setting MMCRA (BHRBRD) bit. 549 */ 550 if (cpu_has_feature(CPU_FTR_ARCH_31)) 551 mmcra |= MMCRA_BHRB_DISABLE; 552 553 /* Second pass: assign PMCs, set all MMCR1 fields */ 554 for (i = 0; i < n_ev; ++i) { 555 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 556 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 557 combine = combine_from_event(event[i]); 558 psel = event[i] & EVENT_PSEL_MASK; 559 560 if (!pmc) { 561 for (pmc = 1; pmc <= 4; ++pmc) { 562 if (!(pmc_inuse & (1 << pmc))) 563 break; 564 } 565 566 pmc_inuse |= 1 << pmc; 567 } 568 569 if (pmc <= 4) { 570 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 571 mmcr1 |= combine << combine_shift(pmc); 572 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 573 } 574 575 /* In continuous sampling mode, update SDAR on TLB miss */ 576 mmcra_sdar_mode(event[i], &mmcra); 577 578 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 579 cache = dc_ic_rld_quad_l1_sel(event[i]); 580 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 581 } else { 582 if (event[i] & EVENT_IS_L1) { 583 cache = dc_ic_rld_quad_l1_sel(event[i]); 584 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 585 } 586 } 587 588 /* Set RADIX_SCOPE_QUAL bit */ 589 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 590 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) & 591 p10_EVENT_RADIX_SCOPE_QUAL_MASK; 592 mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT; 593 } 594 595 if (is_event_marked(event[i])) { 596 mmcra |= MMCRA_SAMPLE_ENABLE; 597 598 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 599 if (val) { 600 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 601 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 602 } 603 } 604 605 /* 606 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 607 * the threshold bits are used for the match value. 608 */ 609 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 610 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 611 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 612 } else { 613 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 614 mmcra |= val << MMCRA_THR_CTL_SHIFT; 615 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 616 mmcra |= val << MMCRA_THR_SEL_SHIFT; 617 if (!cpu_has_feature(CPU_FTR_ARCH_31)) { 618 val = (event[i] >> EVENT_THR_CMP_SHIFT) & 619 EVENT_THR_CMP_MASK; 620 mmcra |= thresh_cmp_val(val); 621 } else if (flags & PPMU_HAS_ATTR_CONFIG1) { 622 val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) & 623 p10_EVENT_THR_CMP_MASK; 624 mmcra |= thresh_cmp_val(val); 625 } 626 } 627 628 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) { 629 val = (event[i] >> p10_L2L3_EVENT_SHIFT) & 630 p10_EVENT_L2L3_SEL_MASK; 631 mmcr2 |= val << p10_L2L3_SEL_SHIFT; 632 } 633 634 if (event[i] & EVENT_WANTS_BHRB) { 635 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 636 mmcra |= val << MMCRA_IFM_SHIFT; 637 } 638 639 /* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */ 640 if (cpu_has_feature(CPU_FTR_ARCH_31) && 641 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB))) 642 mmcra &= ~MMCRA_BHRB_DISABLE; 643 644 if (pevents[i]->attr.exclude_user) 645 mmcr2 |= MMCR2_FCP(pmc); 646 647 if (pevents[i]->attr.exclude_hv) 648 mmcr2 |= MMCR2_FCH(pmc); 649 650 if (pevents[i]->attr.exclude_kernel) { 651 if (cpu_has_feature(CPU_FTR_HVMODE)) 652 mmcr2 |= MMCR2_FCH(pmc); 653 else 654 mmcr2 |= MMCR2_FCS(pmc); 655 } 656 657 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 658 if (pmc <= 4) { 659 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) & 660 p10_EVENT_MMCR3_MASK; 661 mmcr3 |= val << MMCR3_SHIFT(pmc); 662 } 663 } 664 665 hwc[i] = pmc - 1; 666 } 667 668 /* Return MMCRx values */ 669 mmcr->mmcr0 = 0; 670 671 /* pmc_inuse is 1-based */ 672 if (pmc_inuse & 2) 673 mmcr->mmcr0 = MMCR0_PMC1CE; 674 675 if (pmc_inuse & 0x7c) 676 mmcr->mmcr0 |= MMCR0_PMCjCE; 677 678 /* If we're not using PMC 5 or 6, freeze them */ 679 if (!(pmc_inuse & 0x60)) 680 mmcr->mmcr0 |= MMCR0_FC56; 681 682 /* 683 * Set mmcr0 (PMCCEXT) for p10 which 684 * will restrict access to group B registers 685 * when MMCR0 PMCC=0b00. 686 */ 687 if (cpu_has_feature(CPU_FTR_ARCH_31)) 688 mmcr->mmcr0 |= MMCR0_PMCCEXT; 689 690 mmcr->mmcr1 = mmcr1; 691 mmcr->mmcra = mmcra; 692 mmcr->mmcr2 = mmcr2; 693 mmcr->mmcr3 = mmcr3; 694 695 return 0; 696 } 697 698 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr) 699 { 700 if (pmc <= 3) 701 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 702 } 703 704 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 705 { 706 int i, j; 707 708 for (i = 0; i < size; ++i) { 709 if (event < ev_alt[i][0]) 710 break; 711 712 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 713 if (event == ev_alt[i][j]) 714 return i; 715 } 716 717 return -1; 718 } 719 720 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, 721 const unsigned int ev_alt[][MAX_ALT]) 722 { 723 int i, j, num_alt = 0; 724 u64 alt_event; 725 726 alt[num_alt++] = event; 727 i = find_alternative(event, ev_alt, size); 728 if (i >= 0) { 729 /* Filter out the original event, it's already in alt[0] */ 730 for (j = 0; j < MAX_ALT; ++j) { 731 alt_event = ev_alt[i][j]; 732 if (alt_event && alt_event != event) 733 alt[num_alt++] = alt_event; 734 } 735 } 736 737 if (flags & PPMU_ONLY_COUNT_RUN) { 738 /* 739 * We're only counting in RUN state, so PM_CYC is equivalent to 740 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. 741 */ 742 j = num_alt; 743 for (i = 0; i < num_alt; ++i) { 744 switch (alt[i]) { 745 case 0x1e: /* PMC_CYC */ 746 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 747 break; 748 case 0x600f4: 749 alt[j++] = 0x1e; 750 break; 751 case 0x2: /* PM_INST_CMPL */ 752 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 753 break; 754 case 0x500fa: 755 alt[j++] = 0x2; 756 break; 757 } 758 } 759 num_alt = j; 760 } 761 762 return num_alt; 763 } 764 765 int isa3XX_check_attr_config(struct perf_event *ev) 766 { 767 u64 val, sample_mode; 768 u64 event = ev->attr.config; 769 770 val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 771 sample_mode = val & 0x3; 772 773 /* 774 * MMCRA[61:62] is Random Sampling Mode (SM). 775 * value of 0b11 is reserved. 776 */ 777 if (sample_mode == 0x3) 778 return -EINVAL; 779 780 /* 781 * Check for all reserved value 782 * Source: Performance Monitoring Unit User Guide 783 */ 784 switch (val) { 785 case 0x5: 786 case 0x9: 787 case 0xD: 788 case 0x19: 789 case 0x1D: 790 case 0x1A: 791 case 0x1E: 792 return -EINVAL; 793 } 794 795 /* 796 * MMCRA[48:51]/[52:55]) Threshold Start/Stop 797 * Events Selection. 798 * 0b11110000/0b00001111 is reserved. 799 */ 800 val = (event >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 801 if (((val & 0xF0) == 0xF0) || ((val & 0xF) == 0xF)) 802 return -EINVAL; 803 804 return 0; 805 } 806