1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Common Performance counter support functions for PowerISA v2.07 processors. 4 * 5 * Copyright 2009 Paul Mackerras, IBM Corporation. 6 * Copyright 2013 Michael Ellerman, IBM Corporation. 7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 8 */ 9 #include "isa207-common.h" 10 11 PMU_FORMAT_ATTR(event, "config:0-49"); 12 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 13 PMU_FORMAT_ATTR(mark, "config:8"); 14 PMU_FORMAT_ATTR(combine, "config:11"); 15 PMU_FORMAT_ATTR(unit, "config:12-15"); 16 PMU_FORMAT_ATTR(pmc, "config:16-19"); 17 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 18 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 19 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 20 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 21 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 22 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 23 24 struct attribute *isa207_pmu_format_attr[] = { 25 &format_attr_event.attr, 26 &format_attr_pmcxsel.attr, 27 &format_attr_mark.attr, 28 &format_attr_combine.attr, 29 &format_attr_unit.attr, 30 &format_attr_pmc.attr, 31 &format_attr_cache_sel.attr, 32 &format_attr_sample_mode.attr, 33 &format_attr_thresh_sel.attr, 34 &format_attr_thresh_stop.attr, 35 &format_attr_thresh_start.attr, 36 &format_attr_thresh_cmp.attr, 37 NULL, 38 }; 39 40 struct attribute_group isa207_pmu_format_group = { 41 .name = "format", 42 .attrs = isa207_pmu_format_attr, 43 }; 44 45 static inline bool event_is_fab_match(u64 event) 46 { 47 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 48 event &= 0xff0fe; 49 50 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 51 return (event == 0x30056 || event == 0x4f052); 52 } 53 54 static bool is_event_valid(u64 event) 55 { 56 u64 valid_mask = EVENT_VALID_MASK; 57 58 if (cpu_has_feature(CPU_FTR_ARCH_31)) 59 valid_mask = p10_EVENT_VALID_MASK; 60 else if (cpu_has_feature(CPU_FTR_ARCH_300)) 61 valid_mask = p9_EVENT_VALID_MASK; 62 63 return !(event & ~valid_mask); 64 } 65 66 static inline bool is_event_marked(u64 event) 67 { 68 if (event & EVENT_IS_MARKED) 69 return true; 70 71 return false; 72 } 73 74 static unsigned long sdar_mod_val(u64 event) 75 { 76 if (cpu_has_feature(CPU_FTR_ARCH_31)) 77 return p10_SDAR_MODE(event); 78 79 return p9_SDAR_MODE(event); 80 } 81 82 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) 83 { 84 /* 85 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in 86 * continous sampling mode. 87 * 88 * Incase of Power8: 89 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling 90 * mode and will be un-changed when setting MMCRA[63] (Marked events). 91 * 92 * Incase of Power9/power10: 93 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'), 94 * or if group already have any marked events. 95 * For rest 96 * MMCRA[SDAR_MODE] will be set from event code. 97 * If sdar_mode from event is zero, default to 0b01. Hardware 98 * requires that we set a non-zero value. 99 */ 100 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) 102 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES; 103 else if (sdar_mod_val(event)) 104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT; 105 else 106 *mmcra |= MMCRA_SDAR_MODE_DCACHE; 107 } else 108 *mmcra |= MMCRA_SDAR_MODE_TLB; 109 } 110 111 static u64 p10_thresh_cmp_val(u64 value) 112 { 113 int exp = 0; 114 u64 result = value; 115 116 if (!value) 117 return value; 118 119 /* 120 * Incase of P10, thresh_cmp value is not part of raw event code 121 * and provided via attr.config1 parameter. To program threshold in MMCRA, 122 * take a 18 bit number N and shift right 2 places and increment 123 * the exponent E by 1 until the upper 10 bits of N are zero. 124 * Write E to the threshold exponent and write the lower 8 bits of N 125 * to the threshold mantissa. 126 * The max threshold that can be written is 261120. 127 */ 128 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 129 if (value > 261120) 130 value = 261120; 131 while ((64 - __builtin_clzl(value)) > 8) { 132 exp++; 133 value >>= 2; 134 } 135 136 /* 137 * Note that it is invalid to write a mantissa with the 138 * upper 2 bits of mantissa being zero, unless the 139 * exponent is also zero. 140 */ 141 if (!(value & 0xC0) && exp) 142 result = 0; 143 else 144 result = (exp << 8) | value; 145 } 146 return result; 147 } 148 149 static u64 thresh_cmp_val(u64 value) 150 { 151 if (cpu_has_feature(CPU_FTR_ARCH_31)) 152 value = p10_thresh_cmp_val(value); 153 154 /* 155 * Since location of threshold compare bits in MMCRA 156 * is different for p8, using different shift value. 157 */ 158 if (cpu_has_feature(CPU_FTR_ARCH_300)) 159 return value << p9_MMCRA_THR_CMP_SHIFT; 160 else 161 return value << MMCRA_THR_CMP_SHIFT; 162 } 163 164 static unsigned long combine_from_event(u64 event) 165 { 166 if (cpu_has_feature(CPU_FTR_ARCH_300)) 167 return p9_EVENT_COMBINE(event); 168 169 return EVENT_COMBINE(event); 170 } 171 172 static unsigned long combine_shift(unsigned long pmc) 173 { 174 if (cpu_has_feature(CPU_FTR_ARCH_300)) 175 return p9_MMCR1_COMBINE_SHIFT(pmc); 176 177 return MMCR1_COMBINE_SHIFT(pmc); 178 } 179 180 static inline bool event_is_threshold(u64 event) 181 { 182 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 183 } 184 185 static bool is_thresh_cmp_valid(u64 event) 186 { 187 unsigned int cmp, exp; 188 189 if (cpu_has_feature(CPU_FTR_ARCH_31)) 190 return p10_thresh_cmp_val(event) != 0; 191 192 /* 193 * Check the mantissa upper two bits are not zero, unless the 194 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 195 */ 196 197 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 198 exp = cmp >> 7; 199 200 if (exp && (cmp & 0x60) == 0) 201 return false; 202 203 return true; 204 } 205 206 static unsigned int dc_ic_rld_quad_l1_sel(u64 event) 207 { 208 unsigned int cache; 209 210 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; 211 return cache; 212 } 213 214 static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 215 { 216 u64 ret = PERF_MEM_NA; 217 218 switch(idx) { 219 case 0: 220 /* Nothing to do */ 221 break; 222 case 1: 223 ret = PH(LVL, L1); 224 break; 225 case 2: 226 ret = PH(LVL, L2); 227 break; 228 case 3: 229 ret = PH(LVL, L3); 230 break; 231 case 4: 232 if (sub_idx <= 1) 233 ret = PH(LVL, LOC_RAM); 234 else if (sub_idx > 1 && sub_idx <= 2) 235 ret = PH(LVL, REM_RAM1); 236 else 237 ret = PH(LVL, REM_RAM2); 238 ret |= P(SNOOP, HIT); 239 break; 240 case 5: 241 ret = PH(LVL, REM_CCE1); 242 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4)) 243 ret |= P(SNOOP, HIT); 244 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5)) 245 ret |= P(SNOOP, HITM); 246 break; 247 case 6: 248 ret = PH(LVL, REM_CCE2); 249 if ((sub_idx == 0) || (sub_idx == 2)) 250 ret |= P(SNOOP, HIT); 251 else if ((sub_idx == 1) || (sub_idx == 3)) 252 ret |= P(SNOOP, HITM); 253 break; 254 case 7: 255 ret = PM(LVL, L1); 256 break; 257 } 258 259 return ret; 260 } 261 262 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 263 struct pt_regs *regs) 264 { 265 u64 idx; 266 u32 sub_idx; 267 u64 sier; 268 u64 val; 269 270 /* Skip if no SIER support */ 271 if (!(flags & PPMU_HAS_SIER)) { 272 dsrc->val = 0; 273 return; 274 } 275 276 sier = mfspr(SPRN_SIER); 277 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 278 if (val == 1 || val == 2) { 279 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT; 280 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT; 281 282 dsrc->val = isa207_find_source(idx, sub_idx); 283 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); 284 } 285 } 286 287 void isa207_get_mem_weight(u64 *weight) 288 { 289 u64 mmcra = mfspr(SPRN_MMCRA); 290 u64 exp = MMCRA_THR_CTR_EXP(mmcra); 291 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra); 292 u64 sier = mfspr(SPRN_SIER); 293 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 294 295 if (cpu_has_feature(CPU_FTR_ARCH_31)) 296 mantissa = P10_MMCRA_THR_CTR_MANT(mmcra); 297 298 if (val == 0 || val == 7) 299 *weight = 0; 300 else 301 *weight = mantissa << (2 * exp); 302 } 303 304 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp, u64 event_config1) 305 { 306 unsigned int unit, pmc, cache, ebb; 307 unsigned long mask, value; 308 309 mask = value = 0; 310 311 if (!is_event_valid(event)) 312 return -1; 313 314 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 315 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 316 if (cpu_has_feature(CPU_FTR_ARCH_31)) 317 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 318 p10_EVENT_CACHE_SEL_MASK; 319 else 320 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 321 EVENT_CACHE_SEL_MASK; 322 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 323 324 if (pmc) { 325 u64 base_event; 326 327 if (pmc > 6) 328 return -1; 329 330 /* Ignore Linux defined bits when checking event below */ 331 base_event = event & ~EVENT_LINUX_MASK; 332 333 if (pmc >= 5 && base_event != 0x500fa && 334 base_event != 0x600f4) 335 return -1; 336 337 mask |= CNST_PMC_MASK(pmc); 338 value |= CNST_PMC_VAL(pmc); 339 340 /* 341 * PMC5 and PMC6 are used to count cycles and instructions and 342 * they do not support most of the constraint bits. Add a check 343 * to exclude PMC5/6 from most of the constraints except for 344 * EBB/BHRB. 345 */ 346 if (pmc >= 5) 347 goto ebb_bhrb; 348 } 349 350 if (pmc <= 4) { 351 /* 352 * Add to number of counters in use. Note this includes events with 353 * a PMC of 0 - they still need a PMC, it's just assigned later. 354 * Don't count events on PMC 5 & 6, there is only one valid event 355 * on each of those counters, and they are handled above. 356 */ 357 mask |= CNST_NC_MASK; 358 value |= CNST_NC_VAL; 359 } 360 361 if (unit >= 6 && unit <= 9) { 362 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 363 if (unit == 6) { 364 mask |= CNST_L2L3_GROUP_MASK; 365 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT); 366 } 367 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 368 mask |= CNST_CACHE_GROUP_MASK; 369 value |= CNST_CACHE_GROUP_VAL(event & 0xff); 370 371 mask |= CNST_CACHE_PMC4_MASK; 372 if (pmc == 4) 373 value |= CNST_CACHE_PMC4_VAL; 374 } else if (cache & 0x7) { 375 /* 376 * L2/L3 events contain a cache selector field, which is 377 * supposed to be programmed into MMCRC. However MMCRC is only 378 * HV writable, and there is no API for guest kernels to modify 379 * it. The solution is for the hypervisor to initialise the 380 * field to zeroes, and for us to only ever allow events that 381 * have a cache selector of zero. The bank selector (bit 3) is 382 * irrelevant, as long as the rest of the value is 0. 383 */ 384 return -1; 385 } 386 387 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { 388 mask |= CNST_L1_QUAL_MASK; 389 value |= CNST_L1_QUAL_VAL(cache); 390 } 391 392 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 393 mask |= CNST_RADIX_SCOPE_GROUP_MASK; 394 value |= CNST_RADIX_SCOPE_GROUP_VAL(event >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT); 395 } 396 397 if (is_event_marked(event)) { 398 mask |= CNST_SAMPLE_MASK; 399 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 400 } 401 402 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 403 if (event_is_threshold(event) && is_thresh_cmp_valid(event_config1)) { 404 mask |= CNST_THRESH_CTL_SEL_MASK; 405 value |= CNST_THRESH_CTL_SEL_VAL(event >> EVENT_THRESH_SHIFT); 406 mask |= p10_CNST_THRESH_CMP_MASK; 407 value |= p10_CNST_THRESH_CMP_VAL(p10_thresh_cmp_val(event_config1)); 408 } 409 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 410 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 411 mask |= CNST_THRESH_MASK; 412 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 413 } 414 } else { 415 /* 416 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 417 * the threshold control bits are used for the match value. 418 */ 419 if (event_is_fab_match(event)) { 420 mask |= CNST_FAB_MATCH_MASK; 421 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 422 } else { 423 if (!is_thresh_cmp_valid(event)) 424 return -1; 425 426 mask |= CNST_THRESH_MASK; 427 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 428 } 429 } 430 431 ebb_bhrb: 432 if (!pmc && ebb) 433 /* EBB events must specify the PMC */ 434 return -1; 435 436 if (event & EVENT_WANTS_BHRB) { 437 if (!ebb) 438 /* Only EBB events can request BHRB */ 439 return -1; 440 441 mask |= CNST_IFM_MASK; 442 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 443 } 444 445 /* 446 * All events must agree on EBB, either all request it or none. 447 * EBB events are pinned & exclusive, so this should never actually 448 * hit, but we leave it as a fallback in case. 449 */ 450 mask |= CNST_EBB_VAL(ebb); 451 value |= CNST_EBB_MASK; 452 453 *maskp = mask; 454 *valp = value; 455 456 return 0; 457 } 458 459 int isa207_compute_mmcr(u64 event[], int n_ev, 460 unsigned int hwc[], struct mmcr_regs *mmcr, 461 struct perf_event *pevents[], u32 flags) 462 { 463 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 464 unsigned long mmcr3; 465 unsigned int pmc, pmc_inuse; 466 int i; 467 468 pmc_inuse = 0; 469 470 /* First pass to count resource use */ 471 for (i = 0; i < n_ev; ++i) { 472 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 473 if (pmc) 474 pmc_inuse |= 1 << pmc; 475 } 476 477 mmcra = mmcr1 = mmcr2 = mmcr3 = 0; 478 479 /* 480 * Disable bhrb unless explicitly requested 481 * by setting MMCRA (BHRBRD) bit. 482 */ 483 if (cpu_has_feature(CPU_FTR_ARCH_31)) 484 mmcra |= MMCRA_BHRB_DISABLE; 485 486 /* Second pass: assign PMCs, set all MMCR1 fields */ 487 for (i = 0; i < n_ev; ++i) { 488 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 489 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 490 combine = combine_from_event(event[i]); 491 psel = event[i] & EVENT_PSEL_MASK; 492 493 if (!pmc) { 494 for (pmc = 1; pmc <= 4; ++pmc) { 495 if (!(pmc_inuse & (1 << pmc))) 496 break; 497 } 498 499 pmc_inuse |= 1 << pmc; 500 } 501 502 if (pmc <= 4) { 503 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 504 mmcr1 |= combine << combine_shift(pmc); 505 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 506 } 507 508 /* In continuous sampling mode, update SDAR on TLB miss */ 509 mmcra_sdar_mode(event[i], &mmcra); 510 511 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 512 cache = dc_ic_rld_quad_l1_sel(event[i]); 513 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 514 } else { 515 if (event[i] & EVENT_IS_L1) { 516 cache = dc_ic_rld_quad_l1_sel(event[i]); 517 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 518 } 519 } 520 521 /* Set RADIX_SCOPE_QUAL bit */ 522 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 523 val = (event[i] >> p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) & 524 p10_EVENT_RADIX_SCOPE_QUAL_MASK; 525 mmcr1 |= val << p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT; 526 } 527 528 if (is_event_marked(event[i])) { 529 mmcra |= MMCRA_SAMPLE_ENABLE; 530 531 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 532 if (val) { 533 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 534 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 535 } 536 } 537 538 /* 539 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 540 * the threshold bits are used for the match value. 541 */ 542 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 543 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 544 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 545 } else { 546 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 547 mmcra |= val << MMCRA_THR_CTL_SHIFT; 548 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 549 mmcra |= val << MMCRA_THR_SEL_SHIFT; 550 if (!cpu_has_feature(CPU_FTR_ARCH_31)) { 551 val = (event[i] >> EVENT_THR_CMP_SHIFT) & 552 EVENT_THR_CMP_MASK; 553 mmcra |= thresh_cmp_val(val); 554 } else if (flags & PPMU_HAS_ATTR_CONFIG1) { 555 val = (pevents[i]->attr.config1 >> p10_EVENT_THR_CMP_SHIFT) & 556 p10_EVENT_THR_CMP_MASK; 557 mmcra |= thresh_cmp_val(val); 558 } 559 } 560 561 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) { 562 val = (event[i] >> p10_L2L3_EVENT_SHIFT) & 563 p10_EVENT_L2L3_SEL_MASK; 564 mmcr2 |= val << p10_L2L3_SEL_SHIFT; 565 } 566 567 if (event[i] & EVENT_WANTS_BHRB) { 568 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 569 mmcra |= val << MMCRA_IFM_SHIFT; 570 } 571 572 /* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */ 573 if (cpu_has_feature(CPU_FTR_ARCH_31) && 574 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB))) 575 mmcra &= ~MMCRA_BHRB_DISABLE; 576 577 if (pevents[i]->attr.exclude_user) 578 mmcr2 |= MMCR2_FCP(pmc); 579 580 if (pevents[i]->attr.exclude_hv) 581 mmcr2 |= MMCR2_FCH(pmc); 582 583 if (pevents[i]->attr.exclude_kernel) { 584 if (cpu_has_feature(CPU_FTR_HVMODE)) 585 mmcr2 |= MMCR2_FCH(pmc); 586 else 587 mmcr2 |= MMCR2_FCS(pmc); 588 } 589 590 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 591 if (pmc <= 4) { 592 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) & 593 p10_EVENT_MMCR3_MASK; 594 mmcr3 |= val << MMCR3_SHIFT(pmc); 595 } 596 } 597 598 hwc[i] = pmc - 1; 599 } 600 601 /* Return MMCRx values */ 602 mmcr->mmcr0 = 0; 603 604 /* pmc_inuse is 1-based */ 605 if (pmc_inuse & 2) 606 mmcr->mmcr0 = MMCR0_PMC1CE; 607 608 if (pmc_inuse & 0x7c) 609 mmcr->mmcr0 |= MMCR0_PMCjCE; 610 611 /* If we're not using PMC 5 or 6, freeze them */ 612 if (!(pmc_inuse & 0x60)) 613 mmcr->mmcr0 |= MMCR0_FC56; 614 615 /* 616 * Set mmcr0 (PMCCEXT) for p10 which 617 * will restrict access to group B registers 618 * when MMCR0 PMCC=0b00. 619 */ 620 if (cpu_has_feature(CPU_FTR_ARCH_31)) 621 mmcr->mmcr0 |= MMCR0_PMCCEXT; 622 623 mmcr->mmcr1 = mmcr1; 624 mmcr->mmcra = mmcra; 625 mmcr->mmcr2 = mmcr2; 626 mmcr->mmcr3 = mmcr3; 627 628 return 0; 629 } 630 631 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr) 632 { 633 if (pmc <= 3) 634 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 635 } 636 637 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 638 { 639 int i, j; 640 641 for (i = 0; i < size; ++i) { 642 if (event < ev_alt[i][0]) 643 break; 644 645 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 646 if (event == ev_alt[i][j]) 647 return i; 648 } 649 650 return -1; 651 } 652 653 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, 654 const unsigned int ev_alt[][MAX_ALT]) 655 { 656 int i, j, num_alt = 0; 657 u64 alt_event; 658 659 alt[num_alt++] = event; 660 i = find_alternative(event, ev_alt, size); 661 if (i >= 0) { 662 /* Filter out the original event, it's already in alt[0] */ 663 for (j = 0; j < MAX_ALT; ++j) { 664 alt_event = ev_alt[i][j]; 665 if (alt_event && alt_event != event) 666 alt[num_alt++] = alt_event; 667 } 668 } 669 670 if (flags & PPMU_ONLY_COUNT_RUN) { 671 /* 672 * We're only counting in RUN state, so PM_CYC is equivalent to 673 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. 674 */ 675 j = num_alt; 676 for (i = 0; i < num_alt; ++i) { 677 switch (alt[i]) { 678 case 0x1e: /* PMC_CYC */ 679 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 680 break; 681 case 0x600f4: 682 alt[j++] = 0x1e; 683 break; 684 case 0x2: /* PM_INST_CMPL */ 685 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 686 break; 687 case 0x500fa: 688 alt[j++] = 0x2; 689 break; 690 } 691 } 692 num_alt = j; 693 } 694 695 return num_alt; 696 } 697