1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Common Performance counter support functions for PowerISA v2.07 processors. 4 * 5 * Copyright 2009 Paul Mackerras, IBM Corporation. 6 * Copyright 2013 Michael Ellerman, IBM Corporation. 7 * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 8 */ 9 #include "isa207-common.h" 10 11 PMU_FORMAT_ATTR(event, "config:0-49"); 12 PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 13 PMU_FORMAT_ATTR(mark, "config:8"); 14 PMU_FORMAT_ATTR(combine, "config:11"); 15 PMU_FORMAT_ATTR(unit, "config:12-15"); 16 PMU_FORMAT_ATTR(pmc, "config:16-19"); 17 PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 18 PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 19 PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 20 PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 21 PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 22 PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 23 24 struct attribute *isa207_pmu_format_attr[] = { 25 &format_attr_event.attr, 26 &format_attr_pmcxsel.attr, 27 &format_attr_mark.attr, 28 &format_attr_combine.attr, 29 &format_attr_unit.attr, 30 &format_attr_pmc.attr, 31 &format_attr_cache_sel.attr, 32 &format_attr_sample_mode.attr, 33 &format_attr_thresh_sel.attr, 34 &format_attr_thresh_stop.attr, 35 &format_attr_thresh_start.attr, 36 &format_attr_thresh_cmp.attr, 37 NULL, 38 }; 39 40 struct attribute_group isa207_pmu_format_group = { 41 .name = "format", 42 .attrs = isa207_pmu_format_attr, 43 }; 44 45 static inline bool event_is_fab_match(u64 event) 46 { 47 /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 48 event &= 0xff0fe; 49 50 /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 51 return (event == 0x30056 || event == 0x4f052); 52 } 53 54 static bool is_event_valid(u64 event) 55 { 56 u64 valid_mask = EVENT_VALID_MASK; 57 58 if (cpu_has_feature(CPU_FTR_ARCH_31)) 59 valid_mask = p10_EVENT_VALID_MASK; 60 else if (cpu_has_feature(CPU_FTR_ARCH_300)) 61 valid_mask = p9_EVENT_VALID_MASK; 62 63 return !(event & ~valid_mask); 64 } 65 66 static inline bool is_event_marked(u64 event) 67 { 68 if (event & EVENT_IS_MARKED) 69 return true; 70 71 return false; 72 } 73 74 static unsigned long sdar_mod_val(u64 event) 75 { 76 if (cpu_has_feature(CPU_FTR_ARCH_31)) 77 return p10_SDAR_MODE(event); 78 79 return p9_SDAR_MODE(event); 80 } 81 82 static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) 83 { 84 /* 85 * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in 86 * continous sampling mode. 87 * 88 * Incase of Power8: 89 * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling 90 * mode and will be un-changed when setting MMCRA[63] (Marked events). 91 * 92 * Incase of Power9/power10: 93 * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'), 94 * or if group already have any marked events. 95 * For rest 96 * MMCRA[SDAR_MODE] will be set from event code. 97 * If sdar_mode from event is zero, default to 0b01. Hardware 98 * requires that we set a non-zero value. 99 */ 100 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 101 if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) 102 *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES; 103 else if (sdar_mod_val(event)) 104 *mmcra |= sdar_mod_val(event) << MMCRA_SDAR_MODE_SHIFT; 105 else 106 *mmcra |= MMCRA_SDAR_MODE_DCACHE; 107 } else 108 *mmcra |= MMCRA_SDAR_MODE_TLB; 109 } 110 111 static u64 thresh_cmp_val(u64 value) 112 { 113 if (cpu_has_feature(CPU_FTR_ARCH_300)) 114 return value << p9_MMCRA_THR_CMP_SHIFT; 115 116 return value << MMCRA_THR_CMP_SHIFT; 117 } 118 119 static unsigned long combine_from_event(u64 event) 120 { 121 if (cpu_has_feature(CPU_FTR_ARCH_300)) 122 return p9_EVENT_COMBINE(event); 123 124 return EVENT_COMBINE(event); 125 } 126 127 static unsigned long combine_shift(unsigned long pmc) 128 { 129 if (cpu_has_feature(CPU_FTR_ARCH_300)) 130 return p9_MMCR1_COMBINE_SHIFT(pmc); 131 132 return MMCR1_COMBINE_SHIFT(pmc); 133 } 134 135 static inline bool event_is_threshold(u64 event) 136 { 137 return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 138 } 139 140 static bool is_thresh_cmp_valid(u64 event) 141 { 142 unsigned int cmp, exp; 143 144 /* 145 * Check the mantissa upper two bits are not zero, unless the 146 * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 147 * Power10: thresh_cmp is replaced by l2_l3 event select. 148 */ 149 if (cpu_has_feature(CPU_FTR_ARCH_31)) 150 return false; 151 152 cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 153 exp = cmp >> 7; 154 155 if (exp && (cmp & 0x60) == 0) 156 return false; 157 158 return true; 159 } 160 161 static unsigned int dc_ic_rld_quad_l1_sel(u64 event) 162 { 163 unsigned int cache; 164 165 cache = (event >> EVENT_CACHE_SEL_SHIFT) & MMCR1_DC_IC_QUAL_MASK; 166 return cache; 167 } 168 169 static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 170 { 171 u64 ret = PERF_MEM_NA; 172 173 switch(idx) { 174 case 0: 175 /* Nothing to do */ 176 break; 177 case 1: 178 ret = PH(LVL, L1); 179 break; 180 case 2: 181 ret = PH(LVL, L2); 182 break; 183 case 3: 184 ret = PH(LVL, L3); 185 break; 186 case 4: 187 if (sub_idx <= 1) 188 ret = PH(LVL, LOC_RAM); 189 else if (sub_idx > 1 && sub_idx <= 2) 190 ret = PH(LVL, REM_RAM1); 191 else 192 ret = PH(LVL, REM_RAM2); 193 ret |= P(SNOOP, HIT); 194 break; 195 case 5: 196 ret = PH(LVL, REM_CCE1); 197 if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4)) 198 ret |= P(SNOOP, HIT); 199 else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5)) 200 ret |= P(SNOOP, HITM); 201 break; 202 case 6: 203 ret = PH(LVL, REM_CCE2); 204 if ((sub_idx == 0) || (sub_idx == 2)) 205 ret |= P(SNOOP, HIT); 206 else if ((sub_idx == 1) || (sub_idx == 3)) 207 ret |= P(SNOOP, HITM); 208 break; 209 case 7: 210 ret = PM(LVL, L1); 211 break; 212 } 213 214 return ret; 215 } 216 217 void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 218 struct pt_regs *regs) 219 { 220 u64 idx; 221 u32 sub_idx; 222 u64 sier; 223 u64 val; 224 225 /* Skip if no SIER support */ 226 if (!(flags & PPMU_HAS_SIER)) { 227 dsrc->val = 0; 228 return; 229 } 230 231 sier = mfspr(SPRN_SIER); 232 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 233 if (val == 1 || val == 2) { 234 idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT; 235 sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT; 236 237 dsrc->val = isa207_find_source(idx, sub_idx); 238 dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); 239 } 240 } 241 242 void isa207_get_mem_weight(u64 *weight) 243 { 244 u64 mmcra = mfspr(SPRN_MMCRA); 245 u64 exp = MMCRA_THR_CTR_EXP(mmcra); 246 u64 mantissa = MMCRA_THR_CTR_MANT(mmcra); 247 u64 sier = mfspr(SPRN_SIER); 248 u64 val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 249 250 if (val == 0 || val == 7) 251 *weight = 0; 252 else 253 *weight = mantissa << (2 * exp); 254 } 255 256 int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 257 { 258 unsigned int unit, pmc, cache, ebb; 259 unsigned long mask, value; 260 261 mask = value = 0; 262 263 if (!is_event_valid(event)) 264 return -1; 265 266 pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 267 unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 268 if (cpu_has_feature(CPU_FTR_ARCH_31)) 269 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 270 p10_EVENT_CACHE_SEL_MASK; 271 else 272 cache = (event >> EVENT_CACHE_SEL_SHIFT) & 273 EVENT_CACHE_SEL_MASK; 274 ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 275 276 if (pmc) { 277 u64 base_event; 278 279 if (pmc > 6) 280 return -1; 281 282 /* Ignore Linux defined bits when checking event below */ 283 base_event = event & ~EVENT_LINUX_MASK; 284 285 if (pmc >= 5 && base_event != 0x500fa && 286 base_event != 0x600f4) 287 return -1; 288 289 mask |= CNST_PMC_MASK(pmc); 290 value |= CNST_PMC_VAL(pmc); 291 292 /* 293 * PMC5 and PMC6 are used to count cycles and instructions and 294 * they do not support most of the constraint bits. Add a check 295 * to exclude PMC5/6 from most of the constraints except for 296 * EBB/BHRB. 297 */ 298 if (pmc >= 5) 299 goto ebb_bhrb; 300 } 301 302 if (pmc <= 4) { 303 /* 304 * Add to number of counters in use. Note this includes events with 305 * a PMC of 0 - they still need a PMC, it's just assigned later. 306 * Don't count events on PMC 5 & 6, there is only one valid event 307 * on each of those counters, and they are handled above. 308 */ 309 mask |= CNST_NC_MASK; 310 value |= CNST_NC_VAL; 311 } 312 313 if (unit >= 6 && unit <= 9) { 314 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) { 315 mask |= CNST_L2L3_GROUP_MASK; 316 value |= CNST_L2L3_GROUP_VAL(event >> p10_L2L3_EVENT_SHIFT); 317 } else if (cpu_has_feature(CPU_FTR_ARCH_300)) { 318 mask |= CNST_CACHE_GROUP_MASK; 319 value |= CNST_CACHE_GROUP_VAL(event & 0xff); 320 321 mask |= CNST_CACHE_PMC4_MASK; 322 if (pmc == 4) 323 value |= CNST_CACHE_PMC4_VAL; 324 } else if (cache & 0x7) { 325 /* 326 * L2/L3 events contain a cache selector field, which is 327 * supposed to be programmed into MMCRC. However MMCRC is only 328 * HV writable, and there is no API for guest kernels to modify 329 * it. The solution is for the hypervisor to initialise the 330 * field to zeroes, and for us to only ever allow events that 331 * have a cache selector of zero. The bank selector (bit 3) is 332 * irrelevant, as long as the rest of the value is 0. 333 */ 334 return -1; 335 } 336 337 } else if (cpu_has_feature(CPU_FTR_ARCH_300) || (event & EVENT_IS_L1)) { 338 mask |= CNST_L1_QUAL_MASK; 339 value |= CNST_L1_QUAL_VAL(cache); 340 } 341 342 if (is_event_marked(event)) { 343 mask |= CNST_SAMPLE_MASK; 344 value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 345 } 346 347 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 348 if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 349 mask |= CNST_THRESH_MASK; 350 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 351 } 352 } else { 353 /* 354 * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 355 * the threshold control bits are used for the match value. 356 */ 357 if (event_is_fab_match(event)) { 358 mask |= CNST_FAB_MATCH_MASK; 359 value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 360 } else { 361 if (!is_thresh_cmp_valid(event)) 362 return -1; 363 364 mask |= CNST_THRESH_MASK; 365 value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 366 } 367 } 368 369 ebb_bhrb: 370 if (!pmc && ebb) 371 /* EBB events must specify the PMC */ 372 return -1; 373 374 if (event & EVENT_WANTS_BHRB) { 375 if (!ebb) 376 /* Only EBB events can request BHRB */ 377 return -1; 378 379 mask |= CNST_IFM_MASK; 380 value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 381 } 382 383 /* 384 * All events must agree on EBB, either all request it or none. 385 * EBB events are pinned & exclusive, so this should never actually 386 * hit, but we leave it as a fallback in case. 387 */ 388 mask |= CNST_EBB_VAL(ebb); 389 value |= CNST_EBB_MASK; 390 391 *maskp = mask; 392 *valp = value; 393 394 return 0; 395 } 396 397 int isa207_compute_mmcr(u64 event[], int n_ev, 398 unsigned int hwc[], struct mmcr_regs *mmcr, 399 struct perf_event *pevents[]) 400 { 401 unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 402 unsigned long mmcr3; 403 unsigned int pmc, pmc_inuse; 404 int i; 405 406 pmc_inuse = 0; 407 408 /* First pass to count resource use */ 409 for (i = 0; i < n_ev; ++i) { 410 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 411 if (pmc) 412 pmc_inuse |= 1 << pmc; 413 } 414 415 mmcra = mmcr1 = mmcr2 = mmcr3 = 0; 416 417 /* 418 * Disable bhrb unless explicitly requested 419 * by setting MMCRA (BHRBRD) bit. 420 */ 421 if (cpu_has_feature(CPU_FTR_ARCH_31)) 422 mmcra |= MMCRA_BHRB_DISABLE; 423 424 /* Second pass: assign PMCs, set all MMCR1 fields */ 425 for (i = 0; i < n_ev; ++i) { 426 pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 427 unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 428 combine = combine_from_event(event[i]); 429 psel = event[i] & EVENT_PSEL_MASK; 430 431 if (!pmc) { 432 for (pmc = 1; pmc <= 4; ++pmc) { 433 if (!(pmc_inuse & (1 << pmc))) 434 break; 435 } 436 437 pmc_inuse |= 1 << pmc; 438 } 439 440 if (pmc <= 4) { 441 mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 442 mmcr1 |= combine << combine_shift(pmc); 443 mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 444 } 445 446 /* In continuous sampling mode, update SDAR on TLB miss */ 447 mmcra_sdar_mode(event[i], &mmcra); 448 449 if (cpu_has_feature(CPU_FTR_ARCH_300)) { 450 cache = dc_ic_rld_quad_l1_sel(event[i]); 451 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 452 } else { 453 if (event[i] & EVENT_IS_L1) { 454 cache = dc_ic_rld_quad_l1_sel(event[i]); 455 mmcr1 |= (cache) << MMCR1_DC_IC_QUAL_SHIFT; 456 } 457 } 458 459 if (is_event_marked(event[i])) { 460 mmcra |= MMCRA_SAMPLE_ENABLE; 461 462 val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 463 if (val) { 464 mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 465 mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 466 } 467 } 468 469 /* 470 * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 471 * the threshold bits are used for the match value. 472 */ 473 if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 474 mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 475 EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 476 } else { 477 val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 478 mmcra |= val << MMCRA_THR_CTL_SHIFT; 479 val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 480 mmcra |= val << MMCRA_THR_SEL_SHIFT; 481 if (!cpu_has_feature(CPU_FTR_ARCH_31)) { 482 val = (event[i] >> EVENT_THR_CMP_SHIFT) & 483 EVENT_THR_CMP_MASK; 484 mmcra |= thresh_cmp_val(val); 485 } 486 } 487 488 if (cpu_has_feature(CPU_FTR_ARCH_31) && (unit == 6)) { 489 val = (event[i] >> p10_L2L3_EVENT_SHIFT) & 490 p10_EVENT_L2L3_SEL_MASK; 491 mmcr2 |= val << p10_L2L3_SEL_SHIFT; 492 } 493 494 if (event[i] & EVENT_WANTS_BHRB) { 495 val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 496 mmcra |= val << MMCRA_IFM_SHIFT; 497 } 498 499 /* set MMCRA (BHRBRD) to 0 if there is user request for BHRB */ 500 if (cpu_has_feature(CPU_FTR_ARCH_31) && 501 (has_branch_stack(pevents[i]) || (event[i] & EVENT_WANTS_BHRB))) 502 mmcra &= ~MMCRA_BHRB_DISABLE; 503 504 if (pevents[i]->attr.exclude_user) 505 mmcr2 |= MMCR2_FCP(pmc); 506 507 if (pevents[i]->attr.exclude_hv) 508 mmcr2 |= MMCR2_FCH(pmc); 509 510 if (pevents[i]->attr.exclude_kernel) { 511 if (cpu_has_feature(CPU_FTR_HVMODE)) 512 mmcr2 |= MMCR2_FCH(pmc); 513 else 514 mmcr2 |= MMCR2_FCS(pmc); 515 } 516 517 if (cpu_has_feature(CPU_FTR_ARCH_31)) { 518 if (pmc <= 4) { 519 val = (event[i] >> p10_EVENT_MMCR3_SHIFT) & 520 p10_EVENT_MMCR3_MASK; 521 mmcr3 |= val << MMCR3_SHIFT(pmc); 522 } 523 } 524 525 hwc[i] = pmc - 1; 526 } 527 528 /* Return MMCRx values */ 529 mmcr->mmcr0 = 0; 530 531 /* pmc_inuse is 1-based */ 532 if (pmc_inuse & 2) 533 mmcr->mmcr0 = MMCR0_PMC1CE; 534 535 if (pmc_inuse & 0x7c) 536 mmcr->mmcr0 |= MMCR0_PMCjCE; 537 538 /* If we're not using PMC 5 or 6, freeze them */ 539 if (!(pmc_inuse & 0x60)) 540 mmcr->mmcr0 |= MMCR0_FC56; 541 542 mmcr->mmcr1 = mmcr1; 543 mmcr->mmcra = mmcra; 544 mmcr->mmcr2 = mmcr2; 545 mmcr->mmcr3 = mmcr3; 546 547 return 0; 548 } 549 550 void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr) 551 { 552 if (pmc <= 3) 553 mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 554 } 555 556 static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 557 { 558 int i, j; 559 560 for (i = 0; i < size; ++i) { 561 if (event < ev_alt[i][0]) 562 break; 563 564 for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 565 if (event == ev_alt[i][j]) 566 return i; 567 } 568 569 return -1; 570 } 571 572 int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags, 573 const unsigned int ev_alt[][MAX_ALT]) 574 { 575 int i, j, num_alt = 0; 576 u64 alt_event; 577 578 alt[num_alt++] = event; 579 i = find_alternative(event, ev_alt, size); 580 if (i >= 0) { 581 /* Filter out the original event, it's already in alt[0] */ 582 for (j = 0; j < MAX_ALT; ++j) { 583 alt_event = ev_alt[i][j]; 584 if (alt_event && alt_event != event) 585 alt[num_alt++] = alt_event; 586 } 587 } 588 589 if (flags & PPMU_ONLY_COUNT_RUN) { 590 /* 591 * We're only counting in RUN state, so PM_CYC is equivalent to 592 * PM_RUN_CYC and PM_INST_CMPL === PM_RUN_INST_CMPL. 593 */ 594 j = num_alt; 595 for (i = 0; i < num_alt; ++i) { 596 switch (alt[i]) { 597 case 0x1e: /* PMC_CYC */ 598 alt[j++] = 0x600f4; /* PM_RUN_CYC */ 599 break; 600 case 0x600f4: 601 alt[j++] = 0x1e; 602 break; 603 case 0x2: /* PM_INST_CMPL */ 604 alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */ 605 break; 606 case 0x500fa: 607 alt[j++] = 0x2; 608 break; 609 } 610 } 611 num_alt = j; 612 } 613 614 return num_alt; 615 } 616