17ffd948fSMadhavan Srinivasan /* 27ffd948fSMadhavan Srinivasan * Common Performance counter support functions for PowerISA v2.07 processors. 37ffd948fSMadhavan Srinivasan * 47ffd948fSMadhavan Srinivasan * Copyright 2009 Paul Mackerras, IBM Corporation. 57ffd948fSMadhavan Srinivasan * Copyright 2013 Michael Ellerman, IBM Corporation. 67ffd948fSMadhavan Srinivasan * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 77ffd948fSMadhavan Srinivasan * 87ffd948fSMadhavan Srinivasan * This program is free software; you can redistribute it and/or 97ffd948fSMadhavan Srinivasan * modify it under the terms of the GNU General Public License 107ffd948fSMadhavan Srinivasan * as published by the Free Software Foundation; either version 117ffd948fSMadhavan Srinivasan * 2 of the License, or (at your option) any later version. 127ffd948fSMadhavan Srinivasan */ 137ffd948fSMadhavan Srinivasan #include "isa207-common.h" 147ffd948fSMadhavan Srinivasan 1560b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(event, "config:0-49"); 1660b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 1760b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(mark, "config:8"); 1860b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(combine, "config:11"); 1960b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(unit, "config:12-15"); 2060b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(pmc, "config:16-19"); 2160b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 2260b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 2360b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 2460b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 2560b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 2660b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 2760b00025SMadhavan Srinivasan 2860b00025SMadhavan Srinivasan struct attribute *isa207_pmu_format_attr[] = { 2960b00025SMadhavan Srinivasan &format_attr_event.attr, 3060b00025SMadhavan Srinivasan &format_attr_pmcxsel.attr, 3160b00025SMadhavan Srinivasan &format_attr_mark.attr, 3260b00025SMadhavan Srinivasan &format_attr_combine.attr, 3360b00025SMadhavan Srinivasan &format_attr_unit.attr, 3460b00025SMadhavan Srinivasan &format_attr_pmc.attr, 3560b00025SMadhavan Srinivasan &format_attr_cache_sel.attr, 3660b00025SMadhavan Srinivasan &format_attr_sample_mode.attr, 3760b00025SMadhavan Srinivasan &format_attr_thresh_sel.attr, 3860b00025SMadhavan Srinivasan &format_attr_thresh_stop.attr, 3960b00025SMadhavan Srinivasan &format_attr_thresh_start.attr, 4060b00025SMadhavan Srinivasan &format_attr_thresh_cmp.attr, 4160b00025SMadhavan Srinivasan NULL, 4260b00025SMadhavan Srinivasan }; 4360b00025SMadhavan Srinivasan 4460b00025SMadhavan Srinivasan struct attribute_group isa207_pmu_format_group = { 4560b00025SMadhavan Srinivasan .name = "format", 4660b00025SMadhavan Srinivasan .attrs = isa207_pmu_format_attr, 4760b00025SMadhavan Srinivasan }; 4860b00025SMadhavan Srinivasan 497ffd948fSMadhavan Srinivasan static inline bool event_is_fab_match(u64 event) 507ffd948fSMadhavan Srinivasan { 517ffd948fSMadhavan Srinivasan /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 527ffd948fSMadhavan Srinivasan event &= 0xff0fe; 537ffd948fSMadhavan Srinivasan 547ffd948fSMadhavan Srinivasan /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 557ffd948fSMadhavan Srinivasan return (event == 0x30056 || event == 0x4f052); 567ffd948fSMadhavan Srinivasan } 577ffd948fSMadhavan Srinivasan 58c7c3f568SMadhavan Srinivasan static bool is_event_valid(u64 event) 59c7c3f568SMadhavan Srinivasan { 60c7c3f568SMadhavan Srinivasan u64 valid_mask = EVENT_VALID_MASK; 61c7c3f568SMadhavan Srinivasan 62c7c3f568SMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 63c7c3f568SMadhavan Srinivasan valid_mask = p9_EVENT_VALID_MASK; 64c7c3f568SMadhavan Srinivasan 65c7c3f568SMadhavan Srinivasan return !(event & ~valid_mask); 66c7c3f568SMadhavan Srinivasan } 67c7c3f568SMadhavan Srinivasan 6878b4416aSMadhavan Srinivasan static inline bool is_event_marked(u64 event) 69c7c3f568SMadhavan Srinivasan { 7078b4416aSMadhavan Srinivasan if (event & EVENT_IS_MARKED) 7178b4416aSMadhavan Srinivasan return true; 72c7c3f568SMadhavan Srinivasan 7378b4416aSMadhavan Srinivasan return false; 7478b4416aSMadhavan Srinivasan } 7578b4416aSMadhavan Srinivasan 7678b4416aSMadhavan Srinivasan static void mmcra_sdar_mode(u64 event, unsigned long *mmcra) 7778b4416aSMadhavan Srinivasan { 7878b4416aSMadhavan Srinivasan /* 7978b4416aSMadhavan Srinivasan * MMCRA[SDAR_MODE] specifices how the SDAR should be updated in 8078b4416aSMadhavan Srinivasan * continous sampling mode. 8178b4416aSMadhavan Srinivasan * 8278b4416aSMadhavan Srinivasan * Incase of Power8: 8378b4416aSMadhavan Srinivasan * MMCRA[SDAR_MODE] will be programmed as "0b01" for continous sampling 8478b4416aSMadhavan Srinivasan * mode and will be un-changed when setting MMCRA[63] (Marked events). 8578b4416aSMadhavan Srinivasan * 8678b4416aSMadhavan Srinivasan * Incase of Power9: 8778b4416aSMadhavan Srinivasan * Marked event: MMCRA[SDAR_MODE] will be set to 0b00 ('No Updates'), 8878b4416aSMadhavan Srinivasan * or if group already have any marked events. 8978b4416aSMadhavan Srinivasan * Non-Marked events (for DD1): 9078b4416aSMadhavan Srinivasan * MMCRA[SDAR_MODE] will be set to 0b01 9178b4416aSMadhavan Srinivasan * For rest 9278b4416aSMadhavan Srinivasan * MMCRA[SDAR_MODE] will be set from event code. 9378b4416aSMadhavan Srinivasan */ 9478b4416aSMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_ARCH_300)) { 9578b4416aSMadhavan Srinivasan if (is_event_marked(event) || (*mmcra & MMCRA_SAMPLE_ENABLE)) 9678b4416aSMadhavan Srinivasan *mmcra &= MMCRA_SDAR_MODE_NO_UPDATES; 9778b4416aSMadhavan Srinivasan else if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) 9878b4416aSMadhavan Srinivasan *mmcra |= p9_SDAR_MODE(event) << MMCRA_SDAR_MODE_SHIFT; 9978b4416aSMadhavan Srinivasan else if (cpu_has_feature(CPU_FTR_POWER9_DD1)) 10078b4416aSMadhavan Srinivasan *mmcra |= MMCRA_SDAR_MODE_TLB; 10178b4416aSMadhavan Srinivasan } else 10278b4416aSMadhavan Srinivasan *mmcra |= MMCRA_SDAR_MODE_TLB; 103c7c3f568SMadhavan Srinivasan } 104c7c3f568SMadhavan Srinivasan 105c7c3f568SMadhavan Srinivasan static u64 thresh_cmp_val(u64 value) 106c7c3f568SMadhavan Srinivasan { 107c7c3f568SMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 108c7c3f568SMadhavan Srinivasan return value << p9_MMCRA_THR_CMP_SHIFT; 109c7c3f568SMadhavan Srinivasan 110c7c3f568SMadhavan Srinivasan return value << MMCRA_THR_CMP_SHIFT; 111c7c3f568SMadhavan Srinivasan } 112c7c3f568SMadhavan Srinivasan 113c7c3f568SMadhavan Srinivasan static unsigned long combine_from_event(u64 event) 114c7c3f568SMadhavan Srinivasan { 115c7c3f568SMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 116c7c3f568SMadhavan Srinivasan return p9_EVENT_COMBINE(event); 117c7c3f568SMadhavan Srinivasan 118c7c3f568SMadhavan Srinivasan return EVENT_COMBINE(event); 119c7c3f568SMadhavan Srinivasan } 120c7c3f568SMadhavan Srinivasan 121c7c3f568SMadhavan Srinivasan static unsigned long combine_shift(unsigned long pmc) 122c7c3f568SMadhavan Srinivasan { 123c7c3f568SMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_ARCH_300) && !cpu_has_feature(CPU_FTR_POWER9_DD1)) 124c7c3f568SMadhavan Srinivasan return p9_MMCR1_COMBINE_SHIFT(pmc); 125c7c3f568SMadhavan Srinivasan 126c7c3f568SMadhavan Srinivasan return MMCR1_COMBINE_SHIFT(pmc); 127c7c3f568SMadhavan Srinivasan } 128c7c3f568SMadhavan Srinivasan 12978a16d9fSMadhavan Srinivasan static inline bool event_is_threshold(u64 event) 13078a16d9fSMadhavan Srinivasan { 13178a16d9fSMadhavan Srinivasan return (event >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 13278a16d9fSMadhavan Srinivasan } 13378a16d9fSMadhavan Srinivasan 13478a16d9fSMadhavan Srinivasan static bool is_thresh_cmp_valid(u64 event) 13578a16d9fSMadhavan Srinivasan { 13678a16d9fSMadhavan Srinivasan unsigned int cmp, exp; 13778a16d9fSMadhavan Srinivasan 13878a16d9fSMadhavan Srinivasan /* 13978a16d9fSMadhavan Srinivasan * Check the mantissa upper two bits are not zero, unless the 14078a16d9fSMadhavan Srinivasan * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 14178a16d9fSMadhavan Srinivasan */ 14278a16d9fSMadhavan Srinivasan cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 14378a16d9fSMadhavan Srinivasan exp = cmp >> 7; 14478a16d9fSMadhavan Srinivasan 14578a16d9fSMadhavan Srinivasan if (exp && (cmp & 0x60) == 0) 14678a16d9fSMadhavan Srinivasan return false; 14778a16d9fSMadhavan Srinivasan 14878a16d9fSMadhavan Srinivasan return true; 14978a16d9fSMadhavan Srinivasan } 15078a16d9fSMadhavan Srinivasan 15179e96f8fSMadhavan Srinivasan static inline u64 isa207_find_source(u64 idx, u32 sub_idx) 15279e96f8fSMadhavan Srinivasan { 15379e96f8fSMadhavan Srinivasan u64 ret = PERF_MEM_NA; 15479e96f8fSMadhavan Srinivasan 15579e96f8fSMadhavan Srinivasan switch(idx) { 15679e96f8fSMadhavan Srinivasan case 0: 15779e96f8fSMadhavan Srinivasan /* Nothing to do */ 15879e96f8fSMadhavan Srinivasan break; 15979e96f8fSMadhavan Srinivasan case 1: 16079e96f8fSMadhavan Srinivasan ret = PH(LVL, L1); 16179e96f8fSMadhavan Srinivasan break; 16279e96f8fSMadhavan Srinivasan case 2: 16379e96f8fSMadhavan Srinivasan ret = PH(LVL, L2); 16479e96f8fSMadhavan Srinivasan break; 16579e96f8fSMadhavan Srinivasan case 3: 16679e96f8fSMadhavan Srinivasan ret = PH(LVL, L3); 16779e96f8fSMadhavan Srinivasan break; 16879e96f8fSMadhavan Srinivasan case 4: 16979e96f8fSMadhavan Srinivasan if (sub_idx <= 1) 17079e96f8fSMadhavan Srinivasan ret = PH(LVL, LOC_RAM); 17179e96f8fSMadhavan Srinivasan else if (sub_idx > 1 && sub_idx <= 2) 17279e96f8fSMadhavan Srinivasan ret = PH(LVL, REM_RAM1); 17379e96f8fSMadhavan Srinivasan else 17479e96f8fSMadhavan Srinivasan ret = PH(LVL, REM_RAM2); 17579e96f8fSMadhavan Srinivasan ret |= P(SNOOP, HIT); 17679e96f8fSMadhavan Srinivasan break; 17779e96f8fSMadhavan Srinivasan case 5: 17879e96f8fSMadhavan Srinivasan ret = PH(LVL, REM_CCE1); 17979e96f8fSMadhavan Srinivasan if ((sub_idx == 0) || (sub_idx == 2) || (sub_idx == 4)) 18079e96f8fSMadhavan Srinivasan ret |= P(SNOOP, HIT); 18179e96f8fSMadhavan Srinivasan else if ((sub_idx == 1) || (sub_idx == 3) || (sub_idx == 5)) 18279e96f8fSMadhavan Srinivasan ret |= P(SNOOP, HITM); 18379e96f8fSMadhavan Srinivasan break; 18479e96f8fSMadhavan Srinivasan case 6: 18579e96f8fSMadhavan Srinivasan ret = PH(LVL, REM_CCE2); 18679e96f8fSMadhavan Srinivasan if ((sub_idx == 0) || (sub_idx == 2)) 18779e96f8fSMadhavan Srinivasan ret |= P(SNOOP, HIT); 18879e96f8fSMadhavan Srinivasan else if ((sub_idx == 1) || (sub_idx == 3)) 18979e96f8fSMadhavan Srinivasan ret |= P(SNOOP, HITM); 19079e96f8fSMadhavan Srinivasan break; 19179e96f8fSMadhavan Srinivasan case 7: 19279e96f8fSMadhavan Srinivasan ret = PM(LVL, L1); 19379e96f8fSMadhavan Srinivasan break; 19479e96f8fSMadhavan Srinivasan } 19579e96f8fSMadhavan Srinivasan 19679e96f8fSMadhavan Srinivasan return ret; 19779e96f8fSMadhavan Srinivasan } 19879e96f8fSMadhavan Srinivasan 19979e96f8fSMadhavan Srinivasan void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags, 20079e96f8fSMadhavan Srinivasan struct pt_regs *regs) 20179e96f8fSMadhavan Srinivasan { 20279e96f8fSMadhavan Srinivasan u64 idx; 20379e96f8fSMadhavan Srinivasan u32 sub_idx; 20479e96f8fSMadhavan Srinivasan u64 sier; 20579e96f8fSMadhavan Srinivasan u64 val; 20679e96f8fSMadhavan Srinivasan 20779e96f8fSMadhavan Srinivasan /* Skip if no SIER support */ 20879e96f8fSMadhavan Srinivasan if (!(flags & PPMU_HAS_SIER)) { 20979e96f8fSMadhavan Srinivasan dsrc->val = 0; 21079e96f8fSMadhavan Srinivasan return; 21179e96f8fSMadhavan Srinivasan } 21279e96f8fSMadhavan Srinivasan 21379e96f8fSMadhavan Srinivasan sier = mfspr(SPRN_SIER); 21479e96f8fSMadhavan Srinivasan val = (sier & ISA207_SIER_TYPE_MASK) >> ISA207_SIER_TYPE_SHIFT; 21579e96f8fSMadhavan Srinivasan if (val == 1 || val == 2) { 21679e96f8fSMadhavan Srinivasan idx = (sier & ISA207_SIER_LDST_MASK) >> ISA207_SIER_LDST_SHIFT; 21779e96f8fSMadhavan Srinivasan sub_idx = (sier & ISA207_SIER_DATA_SRC_MASK) >> ISA207_SIER_DATA_SRC_SHIFT; 21879e96f8fSMadhavan Srinivasan 21979e96f8fSMadhavan Srinivasan dsrc->val = isa207_find_source(idx, sub_idx); 22079e96f8fSMadhavan Srinivasan dsrc->val |= (val == 1) ? P(OP, LOAD) : P(OP, STORE); 22179e96f8fSMadhavan Srinivasan } 22279e96f8fSMadhavan Srinivasan } 22379e96f8fSMadhavan Srinivasan 22479e96f8fSMadhavan Srinivasan 2257ffd948fSMadhavan Srinivasan int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 2267ffd948fSMadhavan Srinivasan { 2277ffd948fSMadhavan Srinivasan unsigned int unit, pmc, cache, ebb; 2287ffd948fSMadhavan Srinivasan unsigned long mask, value; 2297ffd948fSMadhavan Srinivasan 2307ffd948fSMadhavan Srinivasan mask = value = 0; 2317ffd948fSMadhavan Srinivasan 232c7c3f568SMadhavan Srinivasan if (!is_event_valid(event)) 2337ffd948fSMadhavan Srinivasan return -1; 2347ffd948fSMadhavan Srinivasan 2357ffd948fSMadhavan Srinivasan pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 2367ffd948fSMadhavan Srinivasan unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 2377ffd948fSMadhavan Srinivasan cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; 2387ffd948fSMadhavan Srinivasan ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 2397ffd948fSMadhavan Srinivasan 2407ffd948fSMadhavan Srinivasan if (pmc) { 2417ffd948fSMadhavan Srinivasan u64 base_event; 2427ffd948fSMadhavan Srinivasan 2437ffd948fSMadhavan Srinivasan if (pmc > 6) 2447ffd948fSMadhavan Srinivasan return -1; 2457ffd948fSMadhavan Srinivasan 2467ffd948fSMadhavan Srinivasan /* Ignore Linux defined bits when checking event below */ 2477ffd948fSMadhavan Srinivasan base_event = event & ~EVENT_LINUX_MASK; 2487ffd948fSMadhavan Srinivasan 2497ffd948fSMadhavan Srinivasan if (pmc >= 5 && base_event != 0x500fa && 2507ffd948fSMadhavan Srinivasan base_event != 0x600f4) 2517ffd948fSMadhavan Srinivasan return -1; 2527ffd948fSMadhavan Srinivasan 2537ffd948fSMadhavan Srinivasan mask |= CNST_PMC_MASK(pmc); 2547ffd948fSMadhavan Srinivasan value |= CNST_PMC_VAL(pmc); 2557ffd948fSMadhavan Srinivasan } 2567ffd948fSMadhavan Srinivasan 2577ffd948fSMadhavan Srinivasan if (pmc <= 4) { 2587ffd948fSMadhavan Srinivasan /* 2597ffd948fSMadhavan Srinivasan * Add to number of counters in use. Note this includes events with 2607ffd948fSMadhavan Srinivasan * a PMC of 0 - they still need a PMC, it's just assigned later. 2617ffd948fSMadhavan Srinivasan * Don't count events on PMC 5 & 6, there is only one valid event 2627ffd948fSMadhavan Srinivasan * on each of those counters, and they are handled above. 2637ffd948fSMadhavan Srinivasan */ 2647ffd948fSMadhavan Srinivasan mask |= CNST_NC_MASK; 2657ffd948fSMadhavan Srinivasan value |= CNST_NC_VAL; 2667ffd948fSMadhavan Srinivasan } 2677ffd948fSMadhavan Srinivasan 2687ffd948fSMadhavan Srinivasan if (unit >= 6 && unit <= 9) { 2697ffd948fSMadhavan Srinivasan /* 2707ffd948fSMadhavan Srinivasan * L2/L3 events contain a cache selector field, which is 2717ffd948fSMadhavan Srinivasan * supposed to be programmed into MMCRC. However MMCRC is only 2727ffd948fSMadhavan Srinivasan * HV writable, and there is no API for guest kernels to modify 2737ffd948fSMadhavan Srinivasan * it. The solution is for the hypervisor to initialise the 2747ffd948fSMadhavan Srinivasan * field to zeroes, and for us to only ever allow events that 2757ffd948fSMadhavan Srinivasan * have a cache selector of zero. The bank selector (bit 3) is 2767ffd948fSMadhavan Srinivasan * irrelevant, as long as the rest of the value is 0. 2777ffd948fSMadhavan Srinivasan */ 2787ffd948fSMadhavan Srinivasan if (cache & 0x7) 2797ffd948fSMadhavan Srinivasan return -1; 2807ffd948fSMadhavan Srinivasan 2817ffd948fSMadhavan Srinivasan } else if (event & EVENT_IS_L1) { 2827ffd948fSMadhavan Srinivasan mask |= CNST_L1_QUAL_MASK; 2837ffd948fSMadhavan Srinivasan value |= CNST_L1_QUAL_VAL(cache); 2847ffd948fSMadhavan Srinivasan } 2857ffd948fSMadhavan Srinivasan 28678b4416aSMadhavan Srinivasan if (is_event_marked(event)) { 2877ffd948fSMadhavan Srinivasan mask |= CNST_SAMPLE_MASK; 2887ffd948fSMadhavan Srinivasan value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 2897ffd948fSMadhavan Srinivasan } 2907ffd948fSMadhavan Srinivasan 29178a16d9fSMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_ARCH_300)) { 29278a16d9fSMadhavan Srinivasan if (event_is_threshold(event) && is_thresh_cmp_valid(event)) { 29378a16d9fSMadhavan Srinivasan mask |= CNST_THRESH_MASK; 29478a16d9fSMadhavan Srinivasan value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 29578a16d9fSMadhavan Srinivasan } 29678a16d9fSMadhavan Srinivasan } else { 2977ffd948fSMadhavan Srinivasan /* 2987ffd948fSMadhavan Srinivasan * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 2997ffd948fSMadhavan Srinivasan * the threshold control bits are used for the match value. 3007ffd948fSMadhavan Srinivasan */ 3017ffd948fSMadhavan Srinivasan if (event_is_fab_match(event)) { 3027ffd948fSMadhavan Srinivasan mask |= CNST_FAB_MATCH_MASK; 3037ffd948fSMadhavan Srinivasan value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 3047ffd948fSMadhavan Srinivasan } else { 30578a16d9fSMadhavan Srinivasan if (!is_thresh_cmp_valid(event)) 3067ffd948fSMadhavan Srinivasan return -1; 3077ffd948fSMadhavan Srinivasan 3087ffd948fSMadhavan Srinivasan mask |= CNST_THRESH_MASK; 3097ffd948fSMadhavan Srinivasan value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 3107ffd948fSMadhavan Srinivasan } 31178a16d9fSMadhavan Srinivasan } 3127ffd948fSMadhavan Srinivasan 3137ffd948fSMadhavan Srinivasan if (!pmc && ebb) 3147ffd948fSMadhavan Srinivasan /* EBB events must specify the PMC */ 3157ffd948fSMadhavan Srinivasan return -1; 3167ffd948fSMadhavan Srinivasan 3177ffd948fSMadhavan Srinivasan if (event & EVENT_WANTS_BHRB) { 3187ffd948fSMadhavan Srinivasan if (!ebb) 3197ffd948fSMadhavan Srinivasan /* Only EBB events can request BHRB */ 3207ffd948fSMadhavan Srinivasan return -1; 3217ffd948fSMadhavan Srinivasan 3227ffd948fSMadhavan Srinivasan mask |= CNST_IFM_MASK; 3237ffd948fSMadhavan Srinivasan value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 3247ffd948fSMadhavan Srinivasan } 3257ffd948fSMadhavan Srinivasan 3267ffd948fSMadhavan Srinivasan /* 3277ffd948fSMadhavan Srinivasan * All events must agree on EBB, either all request it or none. 3287ffd948fSMadhavan Srinivasan * EBB events are pinned & exclusive, so this should never actually 3297ffd948fSMadhavan Srinivasan * hit, but we leave it as a fallback in case. 3307ffd948fSMadhavan Srinivasan */ 3317ffd948fSMadhavan Srinivasan mask |= CNST_EBB_VAL(ebb); 3327ffd948fSMadhavan Srinivasan value |= CNST_EBB_MASK; 3337ffd948fSMadhavan Srinivasan 3347ffd948fSMadhavan Srinivasan *maskp = mask; 3357ffd948fSMadhavan Srinivasan *valp = value; 3367ffd948fSMadhavan Srinivasan 3377ffd948fSMadhavan Srinivasan return 0; 3387ffd948fSMadhavan Srinivasan } 3397ffd948fSMadhavan Srinivasan 3407ffd948fSMadhavan Srinivasan int isa207_compute_mmcr(u64 event[], int n_ev, 3417ffd948fSMadhavan Srinivasan unsigned int hwc[], unsigned long mmcr[], 3427ffd948fSMadhavan Srinivasan struct perf_event *pevents[]) 3437ffd948fSMadhavan Srinivasan { 3447ffd948fSMadhavan Srinivasan unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 3457ffd948fSMadhavan Srinivasan unsigned int pmc, pmc_inuse; 3467ffd948fSMadhavan Srinivasan int i; 3477ffd948fSMadhavan Srinivasan 3487ffd948fSMadhavan Srinivasan pmc_inuse = 0; 3497ffd948fSMadhavan Srinivasan 3507ffd948fSMadhavan Srinivasan /* First pass to count resource use */ 3517ffd948fSMadhavan Srinivasan for (i = 0; i < n_ev; ++i) { 3527ffd948fSMadhavan Srinivasan pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 3537ffd948fSMadhavan Srinivasan if (pmc) 3547ffd948fSMadhavan Srinivasan pmc_inuse |= 1 << pmc; 3557ffd948fSMadhavan Srinivasan } 3567ffd948fSMadhavan Srinivasan 357c7c3f568SMadhavan Srinivasan mmcra = mmcr1 = mmcr2 = 0; 3587ffd948fSMadhavan Srinivasan 3597ffd948fSMadhavan Srinivasan /* Second pass: assign PMCs, set all MMCR1 fields */ 3607ffd948fSMadhavan Srinivasan for (i = 0; i < n_ev; ++i) { 3617ffd948fSMadhavan Srinivasan pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 3627ffd948fSMadhavan Srinivasan unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 363c7c3f568SMadhavan Srinivasan combine = combine_from_event(event[i]); 3647ffd948fSMadhavan Srinivasan psel = event[i] & EVENT_PSEL_MASK; 3657ffd948fSMadhavan Srinivasan 3667ffd948fSMadhavan Srinivasan if (!pmc) { 3677ffd948fSMadhavan Srinivasan for (pmc = 1; pmc <= 4; ++pmc) { 3687ffd948fSMadhavan Srinivasan if (!(pmc_inuse & (1 << pmc))) 3697ffd948fSMadhavan Srinivasan break; 3707ffd948fSMadhavan Srinivasan } 3717ffd948fSMadhavan Srinivasan 3727ffd948fSMadhavan Srinivasan pmc_inuse |= 1 << pmc; 3737ffd948fSMadhavan Srinivasan } 3747ffd948fSMadhavan Srinivasan 3757ffd948fSMadhavan Srinivasan if (pmc <= 4) { 3767ffd948fSMadhavan Srinivasan mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 377c7c3f568SMadhavan Srinivasan mmcr1 |= combine << combine_shift(pmc); 3787ffd948fSMadhavan Srinivasan mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 3797ffd948fSMadhavan Srinivasan } 3807ffd948fSMadhavan Srinivasan 381c7c3f568SMadhavan Srinivasan /* In continuous sampling mode, update SDAR on TLB miss */ 38278b4416aSMadhavan Srinivasan mmcra_sdar_mode(event[i], &mmcra); 383c7c3f568SMadhavan Srinivasan 3847ffd948fSMadhavan Srinivasan if (event[i] & EVENT_IS_L1) { 3857ffd948fSMadhavan Srinivasan cache = event[i] >> EVENT_CACHE_SEL_SHIFT; 3867ffd948fSMadhavan Srinivasan mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; 3877ffd948fSMadhavan Srinivasan cache >>= 1; 3887ffd948fSMadhavan Srinivasan mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; 3897ffd948fSMadhavan Srinivasan } 3907ffd948fSMadhavan Srinivasan 39178b4416aSMadhavan Srinivasan if (is_event_marked(event[i])) { 3927ffd948fSMadhavan Srinivasan mmcra |= MMCRA_SAMPLE_ENABLE; 3937ffd948fSMadhavan Srinivasan 3947ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 3957ffd948fSMadhavan Srinivasan if (val) { 3967ffd948fSMadhavan Srinivasan mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 3977ffd948fSMadhavan Srinivasan mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 3987ffd948fSMadhavan Srinivasan } 3997ffd948fSMadhavan Srinivasan } 4007ffd948fSMadhavan Srinivasan 4017ffd948fSMadhavan Srinivasan /* 4027ffd948fSMadhavan Srinivasan * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 4037ffd948fSMadhavan Srinivasan * the threshold bits are used for the match value. 4047ffd948fSMadhavan Srinivasan */ 40578a16d9fSMadhavan Srinivasan if (!cpu_has_feature(CPU_FTR_ARCH_300) && event_is_fab_match(event[i])) { 4067ffd948fSMadhavan Srinivasan mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 4077ffd948fSMadhavan Srinivasan EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 4087ffd948fSMadhavan Srinivasan } else { 4097ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 4107ffd948fSMadhavan Srinivasan mmcra |= val << MMCRA_THR_CTL_SHIFT; 4117ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 4127ffd948fSMadhavan Srinivasan mmcra |= val << MMCRA_THR_SEL_SHIFT; 4137ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 414c7c3f568SMadhavan Srinivasan mmcra |= thresh_cmp_val(val); 4157ffd948fSMadhavan Srinivasan } 4167ffd948fSMadhavan Srinivasan 4177ffd948fSMadhavan Srinivasan if (event[i] & EVENT_WANTS_BHRB) { 4187ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 4197ffd948fSMadhavan Srinivasan mmcra |= val << MMCRA_IFM_SHIFT; 4207ffd948fSMadhavan Srinivasan } 4217ffd948fSMadhavan Srinivasan 4227ffd948fSMadhavan Srinivasan if (pevents[i]->attr.exclude_user) 4237ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCP(pmc); 4247ffd948fSMadhavan Srinivasan 4257ffd948fSMadhavan Srinivasan if (pevents[i]->attr.exclude_hv) 4267ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCH(pmc); 4277ffd948fSMadhavan Srinivasan 4287ffd948fSMadhavan Srinivasan if (pevents[i]->attr.exclude_kernel) { 4297ffd948fSMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_HVMODE)) 4307ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCH(pmc); 4317ffd948fSMadhavan Srinivasan else 4327ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCS(pmc); 4337ffd948fSMadhavan Srinivasan } 4347ffd948fSMadhavan Srinivasan 4357ffd948fSMadhavan Srinivasan hwc[i] = pmc - 1; 4367ffd948fSMadhavan Srinivasan } 4377ffd948fSMadhavan Srinivasan 4387ffd948fSMadhavan Srinivasan /* Return MMCRx values */ 4397ffd948fSMadhavan Srinivasan mmcr[0] = 0; 4407ffd948fSMadhavan Srinivasan 4417ffd948fSMadhavan Srinivasan /* pmc_inuse is 1-based */ 4427ffd948fSMadhavan Srinivasan if (pmc_inuse & 2) 4437ffd948fSMadhavan Srinivasan mmcr[0] = MMCR0_PMC1CE; 4447ffd948fSMadhavan Srinivasan 4457ffd948fSMadhavan Srinivasan if (pmc_inuse & 0x7c) 4467ffd948fSMadhavan Srinivasan mmcr[0] |= MMCR0_PMCjCE; 4477ffd948fSMadhavan Srinivasan 4487ffd948fSMadhavan Srinivasan /* If we're not using PMC 5 or 6, freeze them */ 4497ffd948fSMadhavan Srinivasan if (!(pmc_inuse & 0x60)) 4507ffd948fSMadhavan Srinivasan mmcr[0] |= MMCR0_FC56; 4517ffd948fSMadhavan Srinivasan 4527ffd948fSMadhavan Srinivasan mmcr[1] = mmcr1; 4537ffd948fSMadhavan Srinivasan mmcr[2] = mmcra; 4547ffd948fSMadhavan Srinivasan mmcr[3] = mmcr2; 4557ffd948fSMadhavan Srinivasan 4567ffd948fSMadhavan Srinivasan return 0; 4577ffd948fSMadhavan Srinivasan } 4587ffd948fSMadhavan Srinivasan 4597ffd948fSMadhavan Srinivasan void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 4607ffd948fSMadhavan Srinivasan { 4617ffd948fSMadhavan Srinivasan if (pmc <= 3) 4627ffd948fSMadhavan Srinivasan mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 4637ffd948fSMadhavan Srinivasan } 464efe881afSMadhavan Srinivasan 465efe881afSMadhavan Srinivasan static int find_alternative(u64 event, const unsigned int ev_alt[][MAX_ALT], int size) 466efe881afSMadhavan Srinivasan { 467efe881afSMadhavan Srinivasan int i, j; 468efe881afSMadhavan Srinivasan 469efe881afSMadhavan Srinivasan for (i = 0; i < size; ++i) { 470efe881afSMadhavan Srinivasan if (event < ev_alt[i][0]) 471efe881afSMadhavan Srinivasan break; 472efe881afSMadhavan Srinivasan 473efe881afSMadhavan Srinivasan for (j = 0; j < MAX_ALT && ev_alt[i][j]; ++j) 474efe881afSMadhavan Srinivasan if (event == ev_alt[i][j]) 475efe881afSMadhavan Srinivasan return i; 476efe881afSMadhavan Srinivasan } 477efe881afSMadhavan Srinivasan 478efe881afSMadhavan Srinivasan return -1; 479efe881afSMadhavan Srinivasan } 480efe881afSMadhavan Srinivasan 481efe881afSMadhavan Srinivasan int isa207_get_alternatives(u64 event, u64 alt[], 482efe881afSMadhavan Srinivasan const unsigned int ev_alt[][MAX_ALT], int size) 483efe881afSMadhavan Srinivasan { 484efe881afSMadhavan Srinivasan int i, j, num_alt = 0; 485efe881afSMadhavan Srinivasan u64 alt_event; 486efe881afSMadhavan Srinivasan 487efe881afSMadhavan Srinivasan alt[num_alt++] = event; 488efe881afSMadhavan Srinivasan i = find_alternative(event, ev_alt, size); 489efe881afSMadhavan Srinivasan if (i >= 0) { 490efe881afSMadhavan Srinivasan /* Filter out the original event, it's already in alt[0] */ 491efe881afSMadhavan Srinivasan for (j = 0; j < MAX_ALT; ++j) { 492efe881afSMadhavan Srinivasan alt_event = ev_alt[i][j]; 493efe881afSMadhavan Srinivasan if (alt_event && alt_event != event) 494efe881afSMadhavan Srinivasan alt[num_alt++] = alt_event; 495efe881afSMadhavan Srinivasan } 496efe881afSMadhavan Srinivasan } 497efe881afSMadhavan Srinivasan 498efe881afSMadhavan Srinivasan return num_alt; 499efe881afSMadhavan Srinivasan } 500