17ffd948fSMadhavan Srinivasan /* 27ffd948fSMadhavan Srinivasan * Common Performance counter support functions for PowerISA v2.07 processors. 37ffd948fSMadhavan Srinivasan * 47ffd948fSMadhavan Srinivasan * Copyright 2009 Paul Mackerras, IBM Corporation. 57ffd948fSMadhavan Srinivasan * Copyright 2013 Michael Ellerman, IBM Corporation. 67ffd948fSMadhavan Srinivasan * Copyright 2016 Madhavan Srinivasan, IBM Corporation. 77ffd948fSMadhavan Srinivasan * 87ffd948fSMadhavan Srinivasan * This program is free software; you can redistribute it and/or 97ffd948fSMadhavan Srinivasan * modify it under the terms of the GNU General Public License 107ffd948fSMadhavan Srinivasan * as published by the Free Software Foundation; either version 117ffd948fSMadhavan Srinivasan * 2 of the License, or (at your option) any later version. 127ffd948fSMadhavan Srinivasan */ 137ffd948fSMadhavan Srinivasan #include "isa207-common.h" 147ffd948fSMadhavan Srinivasan 1560b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(event, "config:0-49"); 1660b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 1760b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(mark, "config:8"); 1860b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(combine, "config:11"); 1960b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(unit, "config:12-15"); 2060b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(pmc, "config:16-19"); 2160b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(cache_sel, "config:20-23"); 2260b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(sample_mode, "config:24-28"); 2360b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_sel, "config:29-31"); 2460b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_stop, "config:32-35"); 2560b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_start, "config:36-39"); 2660b00025SMadhavan Srinivasan PMU_FORMAT_ATTR(thresh_cmp, "config:40-49"); 2760b00025SMadhavan Srinivasan 2860b00025SMadhavan Srinivasan struct attribute *isa207_pmu_format_attr[] = { 2960b00025SMadhavan Srinivasan &format_attr_event.attr, 3060b00025SMadhavan Srinivasan &format_attr_pmcxsel.attr, 3160b00025SMadhavan Srinivasan &format_attr_mark.attr, 3260b00025SMadhavan Srinivasan &format_attr_combine.attr, 3360b00025SMadhavan Srinivasan &format_attr_unit.attr, 3460b00025SMadhavan Srinivasan &format_attr_pmc.attr, 3560b00025SMadhavan Srinivasan &format_attr_cache_sel.attr, 3660b00025SMadhavan Srinivasan &format_attr_sample_mode.attr, 3760b00025SMadhavan Srinivasan &format_attr_thresh_sel.attr, 3860b00025SMadhavan Srinivasan &format_attr_thresh_stop.attr, 3960b00025SMadhavan Srinivasan &format_attr_thresh_start.attr, 4060b00025SMadhavan Srinivasan &format_attr_thresh_cmp.attr, 4160b00025SMadhavan Srinivasan NULL, 4260b00025SMadhavan Srinivasan }; 4360b00025SMadhavan Srinivasan 4460b00025SMadhavan Srinivasan struct attribute_group isa207_pmu_format_group = { 4560b00025SMadhavan Srinivasan .name = "format", 4660b00025SMadhavan Srinivasan .attrs = isa207_pmu_format_attr, 4760b00025SMadhavan Srinivasan }; 4860b00025SMadhavan Srinivasan 497ffd948fSMadhavan Srinivasan static inline bool event_is_fab_match(u64 event) 507ffd948fSMadhavan Srinivasan { 517ffd948fSMadhavan Srinivasan /* Only check pmc, unit and pmcxsel, ignore the edge bit (0) */ 527ffd948fSMadhavan Srinivasan event &= 0xff0fe; 537ffd948fSMadhavan Srinivasan 547ffd948fSMadhavan Srinivasan /* PM_MRK_FAB_RSP_MATCH & PM_MRK_FAB_RSP_MATCH_CYC */ 557ffd948fSMadhavan Srinivasan return (event == 0x30056 || event == 0x4f052); 567ffd948fSMadhavan Srinivasan } 577ffd948fSMadhavan Srinivasan 587ffd948fSMadhavan Srinivasan int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp) 597ffd948fSMadhavan Srinivasan { 607ffd948fSMadhavan Srinivasan unsigned int unit, pmc, cache, ebb; 617ffd948fSMadhavan Srinivasan unsigned long mask, value; 627ffd948fSMadhavan Srinivasan 637ffd948fSMadhavan Srinivasan mask = value = 0; 647ffd948fSMadhavan Srinivasan 657ffd948fSMadhavan Srinivasan if (event & ~EVENT_VALID_MASK) 667ffd948fSMadhavan Srinivasan return -1; 677ffd948fSMadhavan Srinivasan 687ffd948fSMadhavan Srinivasan pmc = (event >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 697ffd948fSMadhavan Srinivasan unit = (event >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 707ffd948fSMadhavan Srinivasan cache = (event >> EVENT_CACHE_SEL_SHIFT) & EVENT_CACHE_SEL_MASK; 717ffd948fSMadhavan Srinivasan ebb = (event >> EVENT_EBB_SHIFT) & EVENT_EBB_MASK; 727ffd948fSMadhavan Srinivasan 737ffd948fSMadhavan Srinivasan if (pmc) { 747ffd948fSMadhavan Srinivasan u64 base_event; 757ffd948fSMadhavan Srinivasan 767ffd948fSMadhavan Srinivasan if (pmc > 6) 777ffd948fSMadhavan Srinivasan return -1; 787ffd948fSMadhavan Srinivasan 797ffd948fSMadhavan Srinivasan /* Ignore Linux defined bits when checking event below */ 807ffd948fSMadhavan Srinivasan base_event = event & ~EVENT_LINUX_MASK; 817ffd948fSMadhavan Srinivasan 827ffd948fSMadhavan Srinivasan if (pmc >= 5 && base_event != 0x500fa && 837ffd948fSMadhavan Srinivasan base_event != 0x600f4) 847ffd948fSMadhavan Srinivasan return -1; 857ffd948fSMadhavan Srinivasan 867ffd948fSMadhavan Srinivasan mask |= CNST_PMC_MASK(pmc); 877ffd948fSMadhavan Srinivasan value |= CNST_PMC_VAL(pmc); 887ffd948fSMadhavan Srinivasan } 897ffd948fSMadhavan Srinivasan 907ffd948fSMadhavan Srinivasan if (pmc <= 4) { 917ffd948fSMadhavan Srinivasan /* 927ffd948fSMadhavan Srinivasan * Add to number of counters in use. Note this includes events with 937ffd948fSMadhavan Srinivasan * a PMC of 0 - they still need a PMC, it's just assigned later. 947ffd948fSMadhavan Srinivasan * Don't count events on PMC 5 & 6, there is only one valid event 957ffd948fSMadhavan Srinivasan * on each of those counters, and they are handled above. 967ffd948fSMadhavan Srinivasan */ 977ffd948fSMadhavan Srinivasan mask |= CNST_NC_MASK; 987ffd948fSMadhavan Srinivasan value |= CNST_NC_VAL; 997ffd948fSMadhavan Srinivasan } 1007ffd948fSMadhavan Srinivasan 1017ffd948fSMadhavan Srinivasan if (unit >= 6 && unit <= 9) { 1027ffd948fSMadhavan Srinivasan /* 1037ffd948fSMadhavan Srinivasan * L2/L3 events contain a cache selector field, which is 1047ffd948fSMadhavan Srinivasan * supposed to be programmed into MMCRC. However MMCRC is only 1057ffd948fSMadhavan Srinivasan * HV writable, and there is no API for guest kernels to modify 1067ffd948fSMadhavan Srinivasan * it. The solution is for the hypervisor to initialise the 1077ffd948fSMadhavan Srinivasan * field to zeroes, and for us to only ever allow events that 1087ffd948fSMadhavan Srinivasan * have a cache selector of zero. The bank selector (bit 3) is 1097ffd948fSMadhavan Srinivasan * irrelevant, as long as the rest of the value is 0. 1107ffd948fSMadhavan Srinivasan */ 1117ffd948fSMadhavan Srinivasan if (cache & 0x7) 1127ffd948fSMadhavan Srinivasan return -1; 1137ffd948fSMadhavan Srinivasan 1147ffd948fSMadhavan Srinivasan } else if (event & EVENT_IS_L1) { 1157ffd948fSMadhavan Srinivasan mask |= CNST_L1_QUAL_MASK; 1167ffd948fSMadhavan Srinivasan value |= CNST_L1_QUAL_VAL(cache); 1177ffd948fSMadhavan Srinivasan } 1187ffd948fSMadhavan Srinivasan 1197ffd948fSMadhavan Srinivasan if (event & EVENT_IS_MARKED) { 1207ffd948fSMadhavan Srinivasan mask |= CNST_SAMPLE_MASK; 1217ffd948fSMadhavan Srinivasan value |= CNST_SAMPLE_VAL(event >> EVENT_SAMPLE_SHIFT); 1227ffd948fSMadhavan Srinivasan } 1237ffd948fSMadhavan Srinivasan 1247ffd948fSMadhavan Srinivasan /* 1257ffd948fSMadhavan Srinivasan * Special case for PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 1267ffd948fSMadhavan Srinivasan * the threshold control bits are used for the match value. 1277ffd948fSMadhavan Srinivasan */ 1287ffd948fSMadhavan Srinivasan if (event_is_fab_match(event)) { 1297ffd948fSMadhavan Srinivasan mask |= CNST_FAB_MATCH_MASK; 1307ffd948fSMadhavan Srinivasan value |= CNST_FAB_MATCH_VAL(event >> EVENT_THR_CTL_SHIFT); 1317ffd948fSMadhavan Srinivasan } else { 1327ffd948fSMadhavan Srinivasan /* 1337ffd948fSMadhavan Srinivasan * Check the mantissa upper two bits are not zero, unless the 1347ffd948fSMadhavan Srinivasan * exponent is also zero. See the THRESH_CMP_MANTISSA doc. 1357ffd948fSMadhavan Srinivasan */ 1367ffd948fSMadhavan Srinivasan unsigned int cmp, exp; 1377ffd948fSMadhavan Srinivasan 1387ffd948fSMadhavan Srinivasan cmp = (event >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 1397ffd948fSMadhavan Srinivasan exp = cmp >> 7; 1407ffd948fSMadhavan Srinivasan 1417ffd948fSMadhavan Srinivasan if (exp && (cmp & 0x60) == 0) 1427ffd948fSMadhavan Srinivasan return -1; 1437ffd948fSMadhavan Srinivasan 1447ffd948fSMadhavan Srinivasan mask |= CNST_THRESH_MASK; 1457ffd948fSMadhavan Srinivasan value |= CNST_THRESH_VAL(event >> EVENT_THRESH_SHIFT); 1467ffd948fSMadhavan Srinivasan } 1477ffd948fSMadhavan Srinivasan 1487ffd948fSMadhavan Srinivasan if (!pmc && ebb) 1497ffd948fSMadhavan Srinivasan /* EBB events must specify the PMC */ 1507ffd948fSMadhavan Srinivasan return -1; 1517ffd948fSMadhavan Srinivasan 1527ffd948fSMadhavan Srinivasan if (event & EVENT_WANTS_BHRB) { 1537ffd948fSMadhavan Srinivasan if (!ebb) 1547ffd948fSMadhavan Srinivasan /* Only EBB events can request BHRB */ 1557ffd948fSMadhavan Srinivasan return -1; 1567ffd948fSMadhavan Srinivasan 1577ffd948fSMadhavan Srinivasan mask |= CNST_IFM_MASK; 1587ffd948fSMadhavan Srinivasan value |= CNST_IFM_VAL(event >> EVENT_IFM_SHIFT); 1597ffd948fSMadhavan Srinivasan } 1607ffd948fSMadhavan Srinivasan 1617ffd948fSMadhavan Srinivasan /* 1627ffd948fSMadhavan Srinivasan * All events must agree on EBB, either all request it or none. 1637ffd948fSMadhavan Srinivasan * EBB events are pinned & exclusive, so this should never actually 1647ffd948fSMadhavan Srinivasan * hit, but we leave it as a fallback in case. 1657ffd948fSMadhavan Srinivasan */ 1667ffd948fSMadhavan Srinivasan mask |= CNST_EBB_VAL(ebb); 1677ffd948fSMadhavan Srinivasan value |= CNST_EBB_MASK; 1687ffd948fSMadhavan Srinivasan 1697ffd948fSMadhavan Srinivasan *maskp = mask; 1707ffd948fSMadhavan Srinivasan *valp = value; 1717ffd948fSMadhavan Srinivasan 1727ffd948fSMadhavan Srinivasan return 0; 1737ffd948fSMadhavan Srinivasan } 1747ffd948fSMadhavan Srinivasan 1757ffd948fSMadhavan Srinivasan int isa207_compute_mmcr(u64 event[], int n_ev, 1767ffd948fSMadhavan Srinivasan unsigned int hwc[], unsigned long mmcr[], 1777ffd948fSMadhavan Srinivasan struct perf_event *pevents[]) 1787ffd948fSMadhavan Srinivasan { 1797ffd948fSMadhavan Srinivasan unsigned long mmcra, mmcr1, mmcr2, unit, combine, psel, cache, val; 1807ffd948fSMadhavan Srinivasan unsigned int pmc, pmc_inuse; 1817ffd948fSMadhavan Srinivasan int i; 1827ffd948fSMadhavan Srinivasan 1837ffd948fSMadhavan Srinivasan pmc_inuse = 0; 1847ffd948fSMadhavan Srinivasan 1857ffd948fSMadhavan Srinivasan /* First pass to count resource use */ 1867ffd948fSMadhavan Srinivasan for (i = 0; i < n_ev; ++i) { 1877ffd948fSMadhavan Srinivasan pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 1887ffd948fSMadhavan Srinivasan if (pmc) 1897ffd948fSMadhavan Srinivasan pmc_inuse |= 1 << pmc; 1907ffd948fSMadhavan Srinivasan } 1917ffd948fSMadhavan Srinivasan 1927ffd948fSMadhavan Srinivasan /* In continuous sampling mode, update SDAR on TLB miss */ 1937ffd948fSMadhavan Srinivasan mmcra = MMCRA_SDAR_MODE_TLB; 1947ffd948fSMadhavan Srinivasan mmcr1 = mmcr2 = 0; 1957ffd948fSMadhavan Srinivasan 1967ffd948fSMadhavan Srinivasan /* Second pass: assign PMCs, set all MMCR1 fields */ 1977ffd948fSMadhavan Srinivasan for (i = 0; i < n_ev; ++i) { 1987ffd948fSMadhavan Srinivasan pmc = (event[i] >> EVENT_PMC_SHIFT) & EVENT_PMC_MASK; 1997ffd948fSMadhavan Srinivasan unit = (event[i] >> EVENT_UNIT_SHIFT) & EVENT_UNIT_MASK; 2007ffd948fSMadhavan Srinivasan combine = (event[i] >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK; 2017ffd948fSMadhavan Srinivasan psel = event[i] & EVENT_PSEL_MASK; 2027ffd948fSMadhavan Srinivasan 2037ffd948fSMadhavan Srinivasan if (!pmc) { 2047ffd948fSMadhavan Srinivasan for (pmc = 1; pmc <= 4; ++pmc) { 2057ffd948fSMadhavan Srinivasan if (!(pmc_inuse & (1 << pmc))) 2067ffd948fSMadhavan Srinivasan break; 2077ffd948fSMadhavan Srinivasan } 2087ffd948fSMadhavan Srinivasan 2097ffd948fSMadhavan Srinivasan pmc_inuse |= 1 << pmc; 2107ffd948fSMadhavan Srinivasan } 2117ffd948fSMadhavan Srinivasan 2127ffd948fSMadhavan Srinivasan if (pmc <= 4) { 2137ffd948fSMadhavan Srinivasan mmcr1 |= unit << MMCR1_UNIT_SHIFT(pmc); 2147ffd948fSMadhavan Srinivasan mmcr1 |= combine << MMCR1_COMBINE_SHIFT(pmc); 2157ffd948fSMadhavan Srinivasan mmcr1 |= psel << MMCR1_PMCSEL_SHIFT(pmc); 2167ffd948fSMadhavan Srinivasan } 2177ffd948fSMadhavan Srinivasan 2187ffd948fSMadhavan Srinivasan if (event[i] & EVENT_IS_L1) { 2197ffd948fSMadhavan Srinivasan cache = event[i] >> EVENT_CACHE_SEL_SHIFT; 2207ffd948fSMadhavan Srinivasan mmcr1 |= (cache & 1) << MMCR1_IC_QUAL_SHIFT; 2217ffd948fSMadhavan Srinivasan cache >>= 1; 2227ffd948fSMadhavan Srinivasan mmcr1 |= (cache & 1) << MMCR1_DC_QUAL_SHIFT; 2237ffd948fSMadhavan Srinivasan } 2247ffd948fSMadhavan Srinivasan 2257ffd948fSMadhavan Srinivasan if (event[i] & EVENT_IS_MARKED) { 2267ffd948fSMadhavan Srinivasan mmcra |= MMCRA_SAMPLE_ENABLE; 2277ffd948fSMadhavan Srinivasan 2287ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK; 2297ffd948fSMadhavan Srinivasan if (val) { 2307ffd948fSMadhavan Srinivasan mmcra |= (val & 3) << MMCRA_SAMP_MODE_SHIFT; 2317ffd948fSMadhavan Srinivasan mmcra |= (val >> 2) << MMCRA_SAMP_ELIG_SHIFT; 2327ffd948fSMadhavan Srinivasan } 2337ffd948fSMadhavan Srinivasan } 2347ffd948fSMadhavan Srinivasan 2357ffd948fSMadhavan Srinivasan /* 2367ffd948fSMadhavan Srinivasan * PM_MRK_FAB_RSP_MATCH and PM_MRK_FAB_RSP_MATCH_CYC, 2377ffd948fSMadhavan Srinivasan * the threshold bits are used for the match value. 2387ffd948fSMadhavan Srinivasan */ 2397ffd948fSMadhavan Srinivasan if (event_is_fab_match(event[i])) { 2407ffd948fSMadhavan Srinivasan mmcr1 |= ((event[i] >> EVENT_THR_CTL_SHIFT) & 2417ffd948fSMadhavan Srinivasan EVENT_THR_CTL_MASK) << MMCR1_FAB_SHIFT; 2427ffd948fSMadhavan Srinivasan } else { 2437ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_THR_CTL_SHIFT) & EVENT_THR_CTL_MASK; 2447ffd948fSMadhavan Srinivasan mmcra |= val << MMCRA_THR_CTL_SHIFT; 2457ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_THR_SEL_SHIFT) & EVENT_THR_SEL_MASK; 2467ffd948fSMadhavan Srinivasan mmcra |= val << MMCRA_THR_SEL_SHIFT; 2477ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_THR_CMP_SHIFT) & EVENT_THR_CMP_MASK; 2487ffd948fSMadhavan Srinivasan mmcra |= val << MMCRA_THR_CMP_SHIFT; 2497ffd948fSMadhavan Srinivasan } 2507ffd948fSMadhavan Srinivasan 2517ffd948fSMadhavan Srinivasan if (event[i] & EVENT_WANTS_BHRB) { 2527ffd948fSMadhavan Srinivasan val = (event[i] >> EVENT_IFM_SHIFT) & EVENT_IFM_MASK; 2537ffd948fSMadhavan Srinivasan mmcra |= val << MMCRA_IFM_SHIFT; 2547ffd948fSMadhavan Srinivasan } 2557ffd948fSMadhavan Srinivasan 2567ffd948fSMadhavan Srinivasan if (pevents[i]->attr.exclude_user) 2577ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCP(pmc); 2587ffd948fSMadhavan Srinivasan 2597ffd948fSMadhavan Srinivasan if (pevents[i]->attr.exclude_hv) 2607ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCH(pmc); 2617ffd948fSMadhavan Srinivasan 2627ffd948fSMadhavan Srinivasan if (pevents[i]->attr.exclude_kernel) { 2637ffd948fSMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_HVMODE)) 2647ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCH(pmc); 2657ffd948fSMadhavan Srinivasan else 2667ffd948fSMadhavan Srinivasan mmcr2 |= MMCR2_FCS(pmc); 2677ffd948fSMadhavan Srinivasan } 2687ffd948fSMadhavan Srinivasan 2697ffd948fSMadhavan Srinivasan hwc[i] = pmc - 1; 2707ffd948fSMadhavan Srinivasan } 2717ffd948fSMadhavan Srinivasan 2727ffd948fSMadhavan Srinivasan /* Return MMCRx values */ 2737ffd948fSMadhavan Srinivasan mmcr[0] = 0; 2747ffd948fSMadhavan Srinivasan 2757ffd948fSMadhavan Srinivasan /* pmc_inuse is 1-based */ 2767ffd948fSMadhavan Srinivasan if (pmc_inuse & 2) 2777ffd948fSMadhavan Srinivasan mmcr[0] = MMCR0_PMC1CE; 2787ffd948fSMadhavan Srinivasan 2797ffd948fSMadhavan Srinivasan if (pmc_inuse & 0x7c) 2807ffd948fSMadhavan Srinivasan mmcr[0] |= MMCR0_PMCjCE; 2817ffd948fSMadhavan Srinivasan 2827ffd948fSMadhavan Srinivasan /* If we're not using PMC 5 or 6, freeze them */ 2837ffd948fSMadhavan Srinivasan if (!(pmc_inuse & 0x60)) 2847ffd948fSMadhavan Srinivasan mmcr[0] |= MMCR0_FC56; 2857ffd948fSMadhavan Srinivasan 2867ffd948fSMadhavan Srinivasan mmcr[1] = mmcr1; 2877ffd948fSMadhavan Srinivasan mmcr[2] = mmcra; 2887ffd948fSMadhavan Srinivasan mmcr[3] = mmcr2; 2897ffd948fSMadhavan Srinivasan 2907ffd948fSMadhavan Srinivasan return 0; 2917ffd948fSMadhavan Srinivasan } 2927ffd948fSMadhavan Srinivasan 2937ffd948fSMadhavan Srinivasan void isa207_disable_pmc(unsigned int pmc, unsigned long mmcr[]) 2947ffd948fSMadhavan Srinivasan { 2957ffd948fSMadhavan Srinivasan if (pmc <= 3) 2967ffd948fSMadhavan Srinivasan mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SHIFT(pmc + 1)); 2977ffd948fSMadhavan Srinivasan } 298