xref: /openbmc/linux/arch/powerpc/perf/imc-pmu.c (revision ae40e94f)
1 /*
2  * In-Memory Collection (IMC) Performance Monitor counter support.
3  *
4  * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
5  *           (C) 2017 Anju T Sudhakar, IBM Corporation.
6  *           (C) 2017 Hemant K Shaw, IBM Corporation.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License
10  * as published by the Free Software Foundation; either version
11  * 2 of the License, or later version.
12  */
13 #include <linux/perf_event.h>
14 #include <linux/slab.h>
15 #include <asm/opal.h>
16 #include <asm/imc-pmu.h>
17 #include <asm/cputhreads.h>
18 #include <asm/smp.h>
19 #include <linux/string.h>
20 
21 /* Nest IMC data structures and variables */
22 
23 /*
24  * Used to avoid races in counting the nest-pmu units during hotplug
25  * register and unregister
26  */
27 static DEFINE_MUTEX(nest_init_lock);
28 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
29 static struct imc_pmu **per_nest_pmu_arr;
30 static cpumask_t nest_imc_cpumask;
31 static struct imc_pmu_ref *nest_imc_refc;
32 static int nest_pmus;
33 
34 /* Core IMC data structures and variables */
35 
36 static cpumask_t core_imc_cpumask;
37 static struct imc_pmu_ref *core_imc_refc;
38 static struct imc_pmu *core_imc_pmu;
39 
40 /* Thread IMC data structures and variables */
41 
42 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
43 static struct imc_pmu *thread_imc_pmu;
44 static int thread_imc_mem_size;
45 
46 static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
47 {
48 	return container_of(event->pmu, struct imc_pmu, pmu);
49 }
50 
51 PMU_FORMAT_ATTR(event, "config:0-40");
52 PMU_FORMAT_ATTR(offset, "config:0-31");
53 PMU_FORMAT_ATTR(rvalue, "config:32");
54 PMU_FORMAT_ATTR(mode, "config:33-40");
55 static struct attribute *imc_format_attrs[] = {
56 	&format_attr_event.attr,
57 	&format_attr_offset.attr,
58 	&format_attr_rvalue.attr,
59 	&format_attr_mode.attr,
60 	NULL,
61 };
62 
63 static struct attribute_group imc_format_group = {
64 	.name = "format",
65 	.attrs = imc_format_attrs,
66 };
67 
68 /* Get the cpumask printed to a buffer "buf" */
69 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
70 					struct device_attribute *attr,
71 					char *buf)
72 {
73 	struct pmu *pmu = dev_get_drvdata(dev);
74 	struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
75 	cpumask_t *active_mask;
76 
77 	switch(imc_pmu->domain){
78 	case IMC_DOMAIN_NEST:
79 		active_mask = &nest_imc_cpumask;
80 		break;
81 	case IMC_DOMAIN_CORE:
82 		active_mask = &core_imc_cpumask;
83 		break;
84 	default:
85 		return 0;
86 	}
87 
88 	return cpumap_print_to_pagebuf(true, buf, active_mask);
89 }
90 
91 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
92 
93 static struct attribute *imc_pmu_cpumask_attrs[] = {
94 	&dev_attr_cpumask.attr,
95 	NULL,
96 };
97 
98 static struct attribute_group imc_pmu_cpumask_attr_group = {
99 	.attrs = imc_pmu_cpumask_attrs,
100 };
101 
102 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
103 static struct attribute *device_str_attr_create(const char *name, const char *str)
104 {
105 	struct perf_pmu_events_attr *attr;
106 
107 	attr = kzalloc(sizeof(*attr), GFP_KERNEL);
108 	if (!attr)
109 		return NULL;
110 	sysfs_attr_init(&attr->attr.attr);
111 
112 	attr->event_str = str;
113 	attr->attr.attr.name = name;
114 	attr->attr.attr.mode = 0444;
115 	attr->attr.show = perf_event_sysfs_show;
116 
117 	return &attr->attr.attr;
118 }
119 
120 static int imc_parse_event(struct device_node *np, const char *scale,
121 				  const char *unit, const char *prefix,
122 				  u32 base, struct imc_events *event)
123 {
124 	const char *s;
125 	u32 reg;
126 
127 	if (of_property_read_u32(np, "reg", &reg))
128 		goto error;
129 	/* Add the base_reg value to the "reg" */
130 	event->value = base + reg;
131 
132 	if (of_property_read_string(np, "event-name", &s))
133 		goto error;
134 
135 	event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
136 	if (!event->name)
137 		goto error;
138 
139 	if (of_property_read_string(np, "scale", &s))
140 		s = scale;
141 
142 	if (s) {
143 		event->scale = kstrdup(s, GFP_KERNEL);
144 		if (!event->scale)
145 			goto error;
146 	}
147 
148 	if (of_property_read_string(np, "unit", &s))
149 		s = unit;
150 
151 	if (s) {
152 		event->unit = kstrdup(s, GFP_KERNEL);
153 		if (!event->unit)
154 			goto error;
155 	}
156 
157 	return 0;
158 error:
159 	kfree(event->unit);
160 	kfree(event->scale);
161 	kfree(event->name);
162 	return -EINVAL;
163 }
164 
165 /*
166  * imc_free_events: Function to cleanup the events list, having
167  * 		    "nr_entries".
168  */
169 static void imc_free_events(struct imc_events *events, int nr_entries)
170 {
171 	int i;
172 
173 	/* Nothing to clean, return */
174 	if (!events)
175 		return;
176 	for (i = 0; i < nr_entries; i++) {
177 		kfree(events[i].unit);
178 		kfree(events[i].scale);
179 		kfree(events[i].name);
180 	}
181 
182 	kfree(events);
183 }
184 
185 /*
186  * update_events_in_group: Update the "events" information in an attr_group
187  *                         and assign the attr_group to the pmu "pmu".
188  */
189 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
190 {
191 	struct attribute_group *attr_group;
192 	struct attribute **attrs, *dev_str;
193 	struct device_node *np, *pmu_events;
194 	u32 handle, base_reg;
195 	int i = 0, j = 0, ct, ret;
196 	const char *prefix, *g_scale, *g_unit;
197 	const char *ev_val_str, *ev_scale_str, *ev_unit_str;
198 
199 	if (!of_property_read_u32(node, "events", &handle))
200 		pmu_events = of_find_node_by_phandle(handle);
201 	else
202 		return 0;
203 
204 	/* Did not find any node with a given phandle */
205 	if (!pmu_events)
206 		return 0;
207 
208 	/* Get a count of number of child nodes */
209 	ct = of_get_child_count(pmu_events);
210 
211 	/* Get the event prefix */
212 	if (of_property_read_string(node, "events-prefix", &prefix))
213 		return 0;
214 
215 	/* Get a global unit and scale data if available */
216 	if (of_property_read_string(node, "scale", &g_scale))
217 		g_scale = NULL;
218 
219 	if (of_property_read_string(node, "unit", &g_unit))
220 		g_unit = NULL;
221 
222 	/* "reg" property gives out the base offset of the counters data */
223 	of_property_read_u32(node, "reg", &base_reg);
224 
225 	/* Allocate memory for the events */
226 	pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
227 	if (!pmu->events)
228 		return -ENOMEM;
229 
230 	ct = 0;
231 	/* Parse the events and update the struct */
232 	for_each_child_of_node(pmu_events, np) {
233 		ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
234 		if (!ret)
235 			ct++;
236 	}
237 
238 	/* Allocate memory for attribute group */
239 	attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
240 	if (!attr_group) {
241 		imc_free_events(pmu->events, ct);
242 		return -ENOMEM;
243 	}
244 
245 	/*
246 	 * Allocate memory for attributes.
247 	 * Since we have count of events for this pmu, we also allocate
248 	 * memory for the scale and unit attribute for now.
249 	 * "ct" has the total event structs added from the events-parent node.
250 	 * So allocate three times the "ct" (this includes event, event_scale and
251 	 * event_unit).
252 	 */
253 	attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
254 	if (!attrs) {
255 		kfree(attr_group);
256 		imc_free_events(pmu->events, ct);
257 		return -ENOMEM;
258 	}
259 
260 	attr_group->name = "events";
261 	attr_group->attrs = attrs;
262 	do {
263 		ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
264 		dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
265 		if (!dev_str)
266 			continue;
267 
268 		attrs[j++] = dev_str;
269 		if (pmu->events[i].scale) {
270 			ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
271 			dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
272 			if (!dev_str)
273 				continue;
274 
275 			attrs[j++] = dev_str;
276 		}
277 
278 		if (pmu->events[i].unit) {
279 			ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
280 			dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
281 			if (!dev_str)
282 				continue;
283 
284 			attrs[j++] = dev_str;
285 		}
286 	} while (++i < ct);
287 
288 	/* Save the event attribute */
289 	pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
290 
291 	return 0;
292 }
293 
294 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
295 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
296 {
297 	return per_cpu(local_nest_imc_refc, cpu);
298 }
299 
300 static void nest_change_cpu_context(int old_cpu, int new_cpu)
301 {
302 	struct imc_pmu **pn = per_nest_pmu_arr;
303 
304 	if (old_cpu < 0 || new_cpu < 0)
305 		return;
306 
307 	while (*pn) {
308 		perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
309 		pn++;
310 	}
311 }
312 
313 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
314 {
315 	int nid, target = -1;
316 	const struct cpumask *l_cpumask;
317 	struct imc_pmu_ref *ref;
318 
319 	/*
320 	 * Check in the designated list for this cpu. Dont bother
321 	 * if not one of them.
322 	 */
323 	if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
324 		return 0;
325 
326 	/*
327 	 * Check whether nest_imc is registered. We could end up here if the
328 	 * cpuhotplug callback registration fails. i.e, callback invokes the
329 	 * offline path for all successfully registered nodes. At this stage,
330 	 * nest_imc pmu will not be registered and we should return here.
331 	 *
332 	 * We return with a zero since this is not an offline failure. And
333 	 * cpuhp_setup_state() returns the actual failure reason to the caller,
334 	 * which in turn will call the cleanup routine.
335 	 */
336 	if (!nest_pmus)
337 		return 0;
338 
339 	/*
340 	 * Now that this cpu is one of the designated,
341 	 * find a next cpu a) which is online and b) in same chip.
342 	 */
343 	nid = cpu_to_node(cpu);
344 	l_cpumask = cpumask_of_node(nid);
345 	target = cpumask_any_but(l_cpumask, cpu);
346 
347 	/*
348 	 * Update the cpumask with the target cpu and
349 	 * migrate the context if needed
350 	 */
351 	if (target >= 0 && target < nr_cpu_ids) {
352 		cpumask_set_cpu(target, &nest_imc_cpumask);
353 		nest_change_cpu_context(cpu, target);
354 	} else {
355 		opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
356 				       get_hard_smp_processor_id(cpu));
357 		/*
358 		 * If this is the last cpu in this chip then, skip the reference
359 		 * count mutex lock and make the reference count on this chip zero.
360 		 */
361 		ref = get_nest_pmu_ref(cpu);
362 		if (!ref)
363 			return -EINVAL;
364 
365 		ref->refc = 0;
366 	}
367 	return 0;
368 }
369 
370 static int ppc_nest_imc_cpu_online(unsigned int cpu)
371 {
372 	const struct cpumask *l_cpumask;
373 	static struct cpumask tmp_mask;
374 	int res;
375 
376 	/* Get the cpumask of this node */
377 	l_cpumask = cpumask_of_node(cpu_to_node(cpu));
378 
379 	/*
380 	 * If this is not the first online CPU on this node, then
381 	 * just return.
382 	 */
383 	if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
384 		return 0;
385 
386 	/*
387 	 * If this is the first online cpu on this node
388 	 * disable the nest counters by making an OPAL call.
389 	 */
390 	res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
391 				     get_hard_smp_processor_id(cpu));
392 	if (res)
393 		return res;
394 
395 	/* Make this CPU the designated target for counter collection */
396 	cpumask_set_cpu(cpu, &nest_imc_cpumask);
397 	return 0;
398 }
399 
400 static int nest_pmu_cpumask_init(void)
401 {
402 	return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
403 				 "perf/powerpc/imc:online",
404 				 ppc_nest_imc_cpu_online,
405 				 ppc_nest_imc_cpu_offline);
406 }
407 
408 static void nest_imc_counters_release(struct perf_event *event)
409 {
410 	int rc, node_id;
411 	struct imc_pmu_ref *ref;
412 
413 	if (event->cpu < 0)
414 		return;
415 
416 	node_id = cpu_to_node(event->cpu);
417 
418 	/*
419 	 * See if we need to disable the nest PMU.
420 	 * If no events are currently in use, then we have to take a
421 	 * mutex to ensure that we don't race with another task doing
422 	 * enable or disable the nest counters.
423 	 */
424 	ref = get_nest_pmu_ref(event->cpu);
425 	if (!ref)
426 		return;
427 
428 	/* Take the mutex lock for this node and then decrement the reference count */
429 	mutex_lock(&ref->lock);
430 	if (ref->refc == 0) {
431 		/*
432 		 * The scenario where this is true is, when perf session is
433 		 * started, followed by offlining of all cpus in a given node.
434 		 *
435 		 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
436 		 * function set the ref->count to zero, if the cpu which is
437 		 * about to offline is the last cpu in a given node and make
438 		 * an OPAL call to disable the engine in that node.
439 		 *
440 		 */
441 		mutex_unlock(&ref->lock);
442 		return;
443 	}
444 	ref->refc--;
445 	if (ref->refc == 0) {
446 		rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
447 					    get_hard_smp_processor_id(event->cpu));
448 		if (rc) {
449 			mutex_unlock(&ref->lock);
450 			pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
451 			return;
452 		}
453 	} else if (ref->refc < 0) {
454 		WARN(1, "nest-imc: Invalid event reference count\n");
455 		ref->refc = 0;
456 	}
457 	mutex_unlock(&ref->lock);
458 }
459 
460 static int nest_imc_event_init(struct perf_event *event)
461 {
462 	int chip_id, rc, node_id;
463 	u32 l_config, config = event->attr.config;
464 	struct imc_mem_info *pcni;
465 	struct imc_pmu *pmu;
466 	struct imc_pmu_ref *ref;
467 	bool flag = false;
468 
469 	if (event->attr.type != event->pmu->type)
470 		return -ENOENT;
471 
472 	/* Sampling not supported */
473 	if (event->hw.sample_period)
474 		return -EINVAL;
475 
476 	if (event->cpu < 0)
477 		return -EINVAL;
478 
479 	pmu = imc_event_to_pmu(event);
480 
481 	/* Sanity check for config (event offset) */
482 	if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
483 		return -EINVAL;
484 
485 	/*
486 	 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
487 	 * Get the base memory addresss for this cpu.
488 	 */
489 	chip_id = cpu_to_chip_id(event->cpu);
490 	pcni = pmu->mem_info;
491 	do {
492 		if (pcni->id == chip_id) {
493 			flag = true;
494 			break;
495 		}
496 		pcni++;
497 	} while (pcni);
498 
499 	if (!flag)
500 		return -ENODEV;
501 
502 	/*
503 	 * Add the event offset to the base address.
504 	 */
505 	l_config = config & IMC_EVENT_OFFSET_MASK;
506 	event->hw.event_base = (u64)pcni->vbase + l_config;
507 	node_id = cpu_to_node(event->cpu);
508 
509 	/*
510 	 * Get the imc_pmu_ref struct for this node.
511 	 * Take the mutex lock and then increment the count of nest pmu events
512 	 * inited.
513 	 */
514 	ref = get_nest_pmu_ref(event->cpu);
515 	if (!ref)
516 		return -EINVAL;
517 
518 	mutex_lock(&ref->lock);
519 	if (ref->refc == 0) {
520 		rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
521 					     get_hard_smp_processor_id(event->cpu));
522 		if (rc) {
523 			mutex_unlock(&ref->lock);
524 			pr_err("nest-imc: Unable to start the counters for node %d\n",
525 									node_id);
526 			return rc;
527 		}
528 	}
529 	++ref->refc;
530 	mutex_unlock(&ref->lock);
531 
532 	event->destroy = nest_imc_counters_release;
533 	return 0;
534 }
535 
536 /*
537  * core_imc_mem_init : Initializes memory for the current core.
538  *
539  * Uses alloc_pages_node() and uses the returned address as an argument to
540  * an opal call to configure the pdbar. The address sent as an argument is
541  * converted to physical address before the opal call is made. This is the
542  * base address at which the core imc counters are populated.
543  */
544 static int core_imc_mem_init(int cpu, int size)
545 {
546 	int nid, rc = 0, core_id = (cpu / threads_per_core);
547 	struct imc_mem_info *mem_info;
548 
549 	/*
550 	 * alloc_pages_node() will allocate memory for core in the
551 	 * local node only.
552 	 */
553 	nid = cpu_to_node(cpu);
554 	mem_info = &core_imc_pmu->mem_info[core_id];
555 	mem_info->id = core_id;
556 
557 	/* We need only vbase for core counters */
558 	mem_info->vbase = page_address(alloc_pages_node(nid,
559 					  GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
560 					  __GFP_NOWARN, get_order(size)));
561 	if (!mem_info->vbase)
562 		return -ENOMEM;
563 
564 	/* Init the mutex */
565 	core_imc_refc[core_id].id = core_id;
566 	mutex_init(&core_imc_refc[core_id].lock);
567 
568 	rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
569 				__pa((void *)mem_info->vbase),
570 				get_hard_smp_processor_id(cpu));
571 	if (rc) {
572 		free_pages((u64)mem_info->vbase, get_order(size));
573 		mem_info->vbase = NULL;
574 	}
575 
576 	return rc;
577 }
578 
579 static bool is_core_imc_mem_inited(int cpu)
580 {
581 	struct imc_mem_info *mem_info;
582 	int core_id = (cpu / threads_per_core);
583 
584 	mem_info = &core_imc_pmu->mem_info[core_id];
585 	if (!mem_info->vbase)
586 		return false;
587 
588 	return true;
589 }
590 
591 static int ppc_core_imc_cpu_online(unsigned int cpu)
592 {
593 	const struct cpumask *l_cpumask;
594 	static struct cpumask tmp_mask;
595 	int ret = 0;
596 
597 	/* Get the cpumask for this core */
598 	l_cpumask = cpu_sibling_mask(cpu);
599 
600 	/* If a cpu for this core is already set, then, don't do anything */
601 	if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
602 		return 0;
603 
604 	if (!is_core_imc_mem_inited(cpu)) {
605 		ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
606 		if (ret) {
607 			pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
608 			return ret;
609 		}
610 	}
611 
612 	/* set the cpu in the mask */
613 	cpumask_set_cpu(cpu, &core_imc_cpumask);
614 	return 0;
615 }
616 
617 static int ppc_core_imc_cpu_offline(unsigned int cpu)
618 {
619 	unsigned int core_id;
620 	int ncpu;
621 	struct imc_pmu_ref *ref;
622 
623 	/*
624 	 * clear this cpu out of the mask, if not present in the mask,
625 	 * don't bother doing anything.
626 	 */
627 	if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
628 		return 0;
629 
630 	/*
631 	 * Check whether core_imc is registered. We could end up here
632 	 * if the cpuhotplug callback registration fails. i.e, callback
633 	 * invokes the offline path for all sucessfully registered cpus.
634 	 * At this stage, core_imc pmu will not be registered and we
635 	 * should return here.
636 	 *
637 	 * We return with a zero since this is not an offline failure.
638 	 * And cpuhp_setup_state() returns the actual failure reason
639 	 * to the caller, which inturn will call the cleanup routine.
640 	 */
641 	if (!core_imc_pmu->pmu.event_init)
642 		return 0;
643 
644 	/* Find any online cpu in that core except the current "cpu" */
645 	ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
646 
647 	if (ncpu >= 0 && ncpu < nr_cpu_ids) {
648 		cpumask_set_cpu(ncpu, &core_imc_cpumask);
649 		perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
650 	} else {
651 		/*
652 		 * If this is the last cpu in this core then, skip taking refernce
653 		 * count mutex lock for this core and directly zero "refc" for
654 		 * this core.
655 		 */
656 		opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
657 				       get_hard_smp_processor_id(cpu));
658 		core_id = cpu / threads_per_core;
659 		ref = &core_imc_refc[core_id];
660 		if (!ref)
661 			return -EINVAL;
662 
663 		ref->refc = 0;
664 	}
665 	return 0;
666 }
667 
668 static int core_imc_pmu_cpumask_init(void)
669 {
670 	return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
671 				 "perf/powerpc/imc_core:online",
672 				 ppc_core_imc_cpu_online,
673 				 ppc_core_imc_cpu_offline);
674 }
675 
676 static void core_imc_counters_release(struct perf_event *event)
677 {
678 	int rc, core_id;
679 	struct imc_pmu_ref *ref;
680 
681 	if (event->cpu < 0)
682 		return;
683 	/*
684 	 * See if we need to disable the IMC PMU.
685 	 * If no events are currently in use, then we have to take a
686 	 * mutex to ensure that we don't race with another task doing
687 	 * enable or disable the core counters.
688 	 */
689 	core_id = event->cpu / threads_per_core;
690 
691 	/* Take the mutex lock and decrement the refernce count for this core */
692 	ref = &core_imc_refc[core_id];
693 	if (!ref)
694 		return;
695 
696 	mutex_lock(&ref->lock);
697 	if (ref->refc == 0) {
698 		/*
699 		 * The scenario where this is true is, when perf session is
700 		 * started, followed by offlining of all cpus in a given core.
701 		 *
702 		 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
703 		 * function set the ref->count to zero, if the cpu which is
704 		 * about to offline is the last cpu in a given core and make
705 		 * an OPAL call to disable the engine in that core.
706 		 *
707 		 */
708 		mutex_unlock(&ref->lock);
709 		return;
710 	}
711 	ref->refc--;
712 	if (ref->refc == 0) {
713 		rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
714 					    get_hard_smp_processor_id(event->cpu));
715 		if (rc) {
716 			mutex_unlock(&ref->lock);
717 			pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
718 			return;
719 		}
720 	} else if (ref->refc < 0) {
721 		WARN(1, "core-imc: Invalid event reference count\n");
722 		ref->refc = 0;
723 	}
724 	mutex_unlock(&ref->lock);
725 }
726 
727 static int core_imc_event_init(struct perf_event *event)
728 {
729 	int core_id, rc;
730 	u64 config = event->attr.config;
731 	struct imc_mem_info *pcmi;
732 	struct imc_pmu *pmu;
733 	struct imc_pmu_ref *ref;
734 
735 	if (event->attr.type != event->pmu->type)
736 		return -ENOENT;
737 
738 	/* Sampling not supported */
739 	if (event->hw.sample_period)
740 		return -EINVAL;
741 
742 	if (event->cpu < 0)
743 		return -EINVAL;
744 
745 	event->hw.idx = -1;
746 	pmu = imc_event_to_pmu(event);
747 
748 	/* Sanity check for config (event offset) */
749 	if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
750 		return -EINVAL;
751 
752 	if (!is_core_imc_mem_inited(event->cpu))
753 		return -ENODEV;
754 
755 	core_id = event->cpu / threads_per_core;
756 	pcmi = &core_imc_pmu->mem_info[core_id];
757 	if ((!pcmi->vbase))
758 		return -ENODEV;
759 
760 	/* Get the core_imc mutex for this core */
761 	ref = &core_imc_refc[core_id];
762 	if (!ref)
763 		return -EINVAL;
764 
765 	/*
766 	 * Core pmu units are enabled only when it is used.
767 	 * See if this is triggered for the first time.
768 	 * If yes, take the mutex lock and enable the core counters.
769 	 * If not, just increment the count in core_imc_refc struct.
770 	 */
771 	mutex_lock(&ref->lock);
772 	if (ref->refc == 0) {
773 		rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
774 					     get_hard_smp_processor_id(event->cpu));
775 		if (rc) {
776 			mutex_unlock(&ref->lock);
777 			pr_err("core-imc: Unable to start the counters for core %d\n",
778 									core_id);
779 			return rc;
780 		}
781 	}
782 	++ref->refc;
783 	mutex_unlock(&ref->lock);
784 
785 	event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
786 	event->destroy = core_imc_counters_release;
787 	return 0;
788 }
789 
790 /*
791  * Allocates a page of memory for each of the online cpus, and write the
792  * physical base address of that page to the LDBAR for that cpu.
793  *
794  * LDBAR Register Layout:
795  *
796  *  0          4         8         12        16        20        24        28
797  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
798  *   | |       [   ]    [                   Counter Address [8:50]
799  *   | * Mode    |
800  *   |           * PB Scope
801  *   * Enable/Disable
802  *
803  *  32        36        40        44        48        52        56        60
804  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
805  *           Counter Address [8:50]              ]
806  *
807  */
808 static int thread_imc_mem_alloc(int cpu_id, int size)
809 {
810 	u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, cpu_id);
811 	int nid = cpu_to_node(cpu_id);
812 
813 	if (!local_mem) {
814 		/*
815 		 * This case could happen only once at start, since we dont
816 		 * free the memory in cpu offline path.
817 		 */
818 		local_mem = page_address(alloc_pages_node(nid,
819 				  GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
820 				  __GFP_NOWARN, get_order(size)));
821 		if (!local_mem)
822 			return -ENOMEM;
823 
824 		per_cpu(thread_imc_mem, cpu_id) = local_mem;
825 	}
826 
827 	ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
828 
829 	mtspr(SPRN_LDBAR, ldbar_value);
830 	return 0;
831 }
832 
833 static int ppc_thread_imc_cpu_online(unsigned int cpu)
834 {
835 	return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
836 }
837 
838 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
839 {
840 	mtspr(SPRN_LDBAR, 0);
841 	return 0;
842 }
843 
844 static int thread_imc_cpu_init(void)
845 {
846 	return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
847 			  "perf/powerpc/imc_thread:online",
848 			  ppc_thread_imc_cpu_online,
849 			  ppc_thread_imc_cpu_offline);
850 }
851 
852 static int thread_imc_event_init(struct perf_event *event)
853 {
854 	u32 config = event->attr.config;
855 	struct task_struct *target;
856 	struct imc_pmu *pmu;
857 
858 	if (event->attr.type != event->pmu->type)
859 		return -ENOENT;
860 
861 	/* Sampling not supported */
862 	if (event->hw.sample_period)
863 		return -EINVAL;
864 
865 	event->hw.idx = -1;
866 	pmu = imc_event_to_pmu(event);
867 
868 	/* Sanity check for config offset */
869 	if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
870 		return -EINVAL;
871 
872 	target = event->hw.target;
873 	if (!target)
874 		return -EINVAL;
875 
876 	event->pmu->task_ctx_nr = perf_sw_context;
877 	return 0;
878 }
879 
880 static bool is_thread_imc_pmu(struct perf_event *event)
881 {
882 	if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
883 		return true;
884 
885 	return false;
886 }
887 
888 static u64 * get_event_base_addr(struct perf_event *event)
889 {
890 	u64 addr;
891 
892 	if (is_thread_imc_pmu(event)) {
893 		addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
894 		return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
895 	}
896 
897 	return (u64 *)event->hw.event_base;
898 }
899 
900 static void thread_imc_pmu_start_txn(struct pmu *pmu,
901 				     unsigned int txn_flags)
902 {
903 	if (txn_flags & ~PERF_PMU_TXN_ADD)
904 		return;
905 	perf_pmu_disable(pmu);
906 }
907 
908 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
909 {
910 	perf_pmu_enable(pmu);
911 }
912 
913 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
914 {
915 	perf_pmu_enable(pmu);
916 	return 0;
917 }
918 
919 static u64 imc_read_counter(struct perf_event *event)
920 {
921 	u64 *addr, data;
922 
923 	/*
924 	 * In-Memory Collection (IMC) counters are free flowing counters.
925 	 * So we take a snapshot of the counter value on enable and save it
926 	 * to calculate the delta at later stage to present the event counter
927 	 * value.
928 	 */
929 	addr = get_event_base_addr(event);
930 	data = be64_to_cpu(READ_ONCE(*addr));
931 	local64_set(&event->hw.prev_count, data);
932 
933 	return data;
934 }
935 
936 static void imc_event_update(struct perf_event *event)
937 {
938 	u64 counter_prev, counter_new, final_count;
939 
940 	counter_prev = local64_read(&event->hw.prev_count);
941 	counter_new = imc_read_counter(event);
942 	final_count = counter_new - counter_prev;
943 
944 	/* Update the delta to the event count */
945 	local64_add(final_count, &event->count);
946 }
947 
948 static void imc_event_start(struct perf_event *event, int flags)
949 {
950 	/*
951 	 * In Memory Counters are free flowing counters. HW or the microcode
952 	 * keeps adding to the counter offset in memory. To get event
953 	 * counter value, we snapshot the value here and we calculate
954 	 * delta at later point.
955 	 */
956 	imc_read_counter(event);
957 }
958 
959 static void imc_event_stop(struct perf_event *event, int flags)
960 {
961 	/*
962 	 * Take a snapshot and calculate the delta and update
963 	 * the event counter values.
964 	 */
965 	imc_event_update(event);
966 }
967 
968 static int imc_event_add(struct perf_event *event, int flags)
969 {
970 	if (flags & PERF_EF_START)
971 		imc_event_start(event, flags);
972 
973 	return 0;
974 }
975 
976 static int thread_imc_event_add(struct perf_event *event, int flags)
977 {
978 	int core_id;
979 	struct imc_pmu_ref *ref;
980 
981 	if (flags & PERF_EF_START)
982 		imc_event_start(event, flags);
983 
984 	if (!is_core_imc_mem_inited(smp_processor_id()))
985 		return -EINVAL;
986 
987 	core_id = smp_processor_id() / threads_per_core;
988 	/*
989 	 * imc pmus are enabled only when it is used.
990 	 * See if this is triggered for the first time.
991 	 * If yes, take the mutex lock and enable the counters.
992 	 * If not, just increment the count in ref count struct.
993 	 */
994 	ref = &core_imc_refc[core_id];
995 	if (!ref)
996 		return -EINVAL;
997 
998 	mutex_lock(&ref->lock);
999 	if (ref->refc == 0) {
1000 		if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1001 		    get_hard_smp_processor_id(smp_processor_id()))) {
1002 			mutex_unlock(&ref->lock);
1003 			pr_err("thread-imc: Unable to start the counter\
1004 				for core %d\n", core_id);
1005 			return -EINVAL;
1006 		}
1007 	}
1008 	++ref->refc;
1009 	mutex_unlock(&ref->lock);
1010 	return 0;
1011 }
1012 
1013 static void thread_imc_event_del(struct perf_event *event, int flags)
1014 {
1015 
1016 	int core_id;
1017 	struct imc_pmu_ref *ref;
1018 
1019 	/*
1020 	 * Take a snapshot and calculate the delta and update
1021 	 * the event counter values.
1022 	 */
1023 	imc_event_update(event);
1024 
1025 	core_id = smp_processor_id() / threads_per_core;
1026 	ref = &core_imc_refc[core_id];
1027 
1028 	mutex_lock(&ref->lock);
1029 	ref->refc--;
1030 	if (ref->refc == 0) {
1031 		if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1032 		    get_hard_smp_processor_id(smp_processor_id()))) {
1033 			mutex_unlock(&ref->lock);
1034 			pr_err("thread-imc: Unable to stop the counters\
1035 				for core %d\n", core_id);
1036 			return;
1037 		}
1038 	} else if (ref->refc < 0) {
1039 		ref->refc = 0;
1040 	}
1041 	mutex_unlock(&ref->lock);
1042 }
1043 
1044 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1045 static int update_pmu_ops(struct imc_pmu *pmu)
1046 {
1047 	pmu->pmu.task_ctx_nr = perf_invalid_context;
1048 	pmu->pmu.add = imc_event_add;
1049 	pmu->pmu.del = imc_event_stop;
1050 	pmu->pmu.start = imc_event_start;
1051 	pmu->pmu.stop = imc_event_stop;
1052 	pmu->pmu.read = imc_event_update;
1053 	pmu->pmu.attr_groups = pmu->attr_groups;
1054 	pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1055 	pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1056 
1057 	switch (pmu->domain) {
1058 	case IMC_DOMAIN_NEST:
1059 		pmu->pmu.event_init = nest_imc_event_init;
1060 		pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1061 		break;
1062 	case IMC_DOMAIN_CORE:
1063 		pmu->pmu.event_init = core_imc_event_init;
1064 		pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1065 		break;
1066 	case IMC_DOMAIN_THREAD:
1067 		pmu->pmu.event_init = thread_imc_event_init;
1068 		pmu->pmu.add = thread_imc_event_add;
1069 		pmu->pmu.del = thread_imc_event_del;
1070 		pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1071 		pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1072 		pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1073 		break;
1074 	default:
1075 		break;
1076 	}
1077 
1078 	return 0;
1079 }
1080 
1081 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1082 static int init_nest_pmu_ref(void)
1083 {
1084 	int nid, i, cpu;
1085 
1086 	nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1087 								GFP_KERNEL);
1088 
1089 	if (!nest_imc_refc)
1090 		return -ENOMEM;
1091 
1092 	i = 0;
1093 	for_each_node(nid) {
1094 		/*
1095 		 * Mutex lock to avoid races while tracking the number of
1096 		 * sessions using the chip's nest pmu units.
1097 		 */
1098 		mutex_init(&nest_imc_refc[i].lock);
1099 
1100 		/*
1101 		 * Loop to init the "id" with the node_id. Variable "i" initialized to
1102 		 * 0 and will be used as index to the array. "i" will not go off the
1103 		 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1104 		 * nodes only.
1105 		 */
1106 		nest_imc_refc[i++].id = nid;
1107 	}
1108 
1109 	/*
1110 	 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1111 	 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1112 	 */
1113 	for_each_possible_cpu(cpu) {
1114 		nid = cpu_to_node(cpu);
1115 		for (i = 0; i < num_possible_nodes(); i++) {
1116 			if (nest_imc_refc[i].id == nid) {
1117 				per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1118 				break;
1119 			}
1120 		}
1121 	}
1122 	return 0;
1123 }
1124 
1125 static void cleanup_all_core_imc_memory(void)
1126 {
1127 	int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1128 	struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1129 	int size = core_imc_pmu->counter_mem_size;
1130 
1131 	/* mem_info will never be NULL */
1132 	for (i = 0; i < nr_cores; i++) {
1133 		if (ptr[i].vbase)
1134 			free_pages((u64)ptr[i].vbase, get_order(size));
1135 	}
1136 
1137 	kfree(ptr);
1138 	kfree(core_imc_refc);
1139 }
1140 
1141 static void thread_imc_ldbar_disable(void *dummy)
1142 {
1143 	/*
1144 	 * By Zeroing LDBAR, we disable thread-imc
1145 	 * updates.
1146 	 */
1147 	mtspr(SPRN_LDBAR, 0);
1148 }
1149 
1150 void thread_imc_disable(void)
1151 {
1152 	on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1153 }
1154 
1155 static void cleanup_all_thread_imc_memory(void)
1156 {
1157 	int i, order = get_order(thread_imc_mem_size);
1158 
1159 	for_each_online_cpu(i) {
1160 		if (per_cpu(thread_imc_mem, i))
1161 			free_pages((u64)per_cpu(thread_imc_mem, i), order);
1162 
1163 	}
1164 }
1165 
1166 /* Function to free the attr_groups which are dynamically allocated */
1167 static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1168 {
1169 	if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1170 		kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1171 	kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1172 }
1173 
1174 /*
1175  * Common function to unregister cpu hotplug callback and
1176  * free the memory.
1177  * TODO: Need to handle pmu unregistering, which will be
1178  * done in followup series.
1179  */
1180 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1181 {
1182 	if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1183 		mutex_lock(&nest_init_lock);
1184 		if (nest_pmus == 1) {
1185 			cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1186 			kfree(nest_imc_refc);
1187 			kfree(per_nest_pmu_arr);
1188 			per_nest_pmu_arr = NULL;
1189 		}
1190 
1191 		if (nest_pmus > 0)
1192 			nest_pmus--;
1193 		mutex_unlock(&nest_init_lock);
1194 	}
1195 
1196 	/* Free core_imc memory */
1197 	if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1198 		cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1199 		cleanup_all_core_imc_memory();
1200 	}
1201 
1202 	/* Free thread_imc memory */
1203 	if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1204 		cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1205 		cleanup_all_thread_imc_memory();
1206 	}
1207 }
1208 
1209 /*
1210  * Function to unregister thread-imc if core-imc
1211  * is not registered.
1212  */
1213 void unregister_thread_imc(void)
1214 {
1215 	imc_common_cpuhp_mem_free(thread_imc_pmu);
1216 	imc_common_mem_free(thread_imc_pmu);
1217 	perf_pmu_unregister(&thread_imc_pmu->pmu);
1218 }
1219 
1220 /*
1221  * imc_mem_init : Function to support memory allocation for core imc.
1222  */
1223 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1224 								int pmu_index)
1225 {
1226 	const char *s;
1227 	int nr_cores, cpu, res = -ENOMEM;
1228 
1229 	if (of_property_read_string(parent, "name", &s))
1230 		return -ENODEV;
1231 
1232 	switch (pmu_ptr->domain) {
1233 	case IMC_DOMAIN_NEST:
1234 		/* Update the pmu name */
1235 		pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1236 		if (!pmu_ptr->pmu.name)
1237 			goto err;
1238 
1239 		/* Needed for hotplug/migration */
1240 		if (!per_nest_pmu_arr) {
1241 			per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1242 						sizeof(struct imc_pmu *),
1243 						GFP_KERNEL);
1244 			if (!per_nest_pmu_arr)
1245 				goto err;
1246 		}
1247 		per_nest_pmu_arr[pmu_index] = pmu_ptr;
1248 		break;
1249 	case IMC_DOMAIN_CORE:
1250 		/* Update the pmu name */
1251 		pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1252 		if (!pmu_ptr->pmu.name)
1253 			goto err;
1254 
1255 		nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1256 		pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1257 								GFP_KERNEL);
1258 
1259 		if (!pmu_ptr->mem_info)
1260 			goto err;
1261 
1262 		core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1263 								GFP_KERNEL);
1264 
1265 		if (!core_imc_refc) {
1266 			kfree(pmu_ptr->mem_info);
1267 			goto err;
1268 		}
1269 
1270 		core_imc_pmu = pmu_ptr;
1271 		break;
1272 	case IMC_DOMAIN_THREAD:
1273 		/* Update the pmu name */
1274 		pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1275 		if (!pmu_ptr->pmu.name)
1276 			goto err;
1277 
1278 		thread_imc_mem_size = pmu_ptr->counter_mem_size;
1279 		for_each_online_cpu(cpu) {
1280 			res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1281 			if (res) {
1282 				cleanup_all_thread_imc_memory();
1283 				goto err;
1284 			}
1285 		}
1286 
1287 		thread_imc_pmu = pmu_ptr;
1288 		break;
1289 	default:
1290 		return -EINVAL;
1291 	}
1292 
1293 	return 0;
1294 err:
1295 	return res;
1296 }
1297 
1298 /*
1299  * init_imc_pmu : Setup and register the IMC pmu device.
1300  *
1301  * @parent:	Device tree unit node
1302  * @pmu_ptr:	memory allocated for this pmu
1303  * @pmu_idx:	Count of nest pmc registered
1304  *
1305  * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1306  * Handles failure cases and accordingly frees memory.
1307  */
1308 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1309 {
1310 	int ret;
1311 
1312 	ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1313 	if (ret)
1314 		goto err_free_mem;
1315 
1316 	switch (pmu_ptr->domain) {
1317 	case IMC_DOMAIN_NEST:
1318 		/*
1319 		* Nest imc pmu need only one cpu per chip, we initialize the
1320 		* cpumask for the first nest imc pmu and use the same for the
1321 		* rest. To handle the cpuhotplug callback unregister, we track
1322 		* the number of nest pmus in "nest_pmus".
1323 		*/
1324 		mutex_lock(&nest_init_lock);
1325 		if (nest_pmus == 0) {
1326 			ret = init_nest_pmu_ref();
1327 			if (ret) {
1328 				mutex_unlock(&nest_init_lock);
1329 				kfree(per_nest_pmu_arr);
1330 				per_nest_pmu_arr = NULL;
1331 				goto err_free_mem;
1332 			}
1333 			/* Register for cpu hotplug notification. */
1334 			ret = nest_pmu_cpumask_init();
1335 			if (ret) {
1336 				mutex_unlock(&nest_init_lock);
1337 				kfree(nest_imc_refc);
1338 				kfree(per_nest_pmu_arr);
1339 				per_nest_pmu_arr = NULL;
1340 				goto err_free_mem;
1341 			}
1342 		}
1343 		nest_pmus++;
1344 		mutex_unlock(&nest_init_lock);
1345 		break;
1346 	case IMC_DOMAIN_CORE:
1347 		ret = core_imc_pmu_cpumask_init();
1348 		if (ret) {
1349 			cleanup_all_core_imc_memory();
1350 			goto err_free_mem;
1351 		}
1352 
1353 		break;
1354 	case IMC_DOMAIN_THREAD:
1355 		ret = thread_imc_cpu_init();
1356 		if (ret) {
1357 			cleanup_all_thread_imc_memory();
1358 			goto err_free_mem;
1359 		}
1360 
1361 		break;
1362 	default:
1363 		return  -EINVAL;	/* Unknown domain */
1364 	}
1365 
1366 	ret = update_events_in_group(parent, pmu_ptr);
1367 	if (ret)
1368 		goto err_free_cpuhp_mem;
1369 
1370 	ret = update_pmu_ops(pmu_ptr);
1371 	if (ret)
1372 		goto err_free_cpuhp_mem;
1373 
1374 	ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1375 	if (ret)
1376 		goto err_free_cpuhp_mem;
1377 
1378 	pr_debug("%s performance monitor hardware support registered\n",
1379 							pmu_ptr->pmu.name);
1380 
1381 	return 0;
1382 
1383 err_free_cpuhp_mem:
1384 	imc_common_cpuhp_mem_free(pmu_ptr);
1385 err_free_mem:
1386 	imc_common_mem_free(pmu_ptr);
1387 	return ret;
1388 }
1389