xref: /openbmc/linux/arch/powerpc/perf/core-book3s.c (revision d7a3d85e)
1 /*
2  * Performance event support - powerpc architecture code
3  *
4  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License
8  * as published by the Free Software Foundation; either version
9  * 2 of the License, or (at your option) any later version.
10  */
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
17 #include <asm/reg.h>
18 #include <asm/pmc.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
23 
24 #define BHRB_MAX_ENTRIES	32
25 #define BHRB_TARGET		0x0000000000000002
26 #define BHRB_PREDICTION		0x0000000000000001
27 #define BHRB_EA			0xFFFFFFFFFFFFFFFCUL
28 
29 struct cpu_hw_events {
30 	int n_events;
31 	int n_percpu;
32 	int disabled;
33 	int n_added;
34 	int n_limited;
35 	u8  pmcs_enabled;
36 	struct perf_event *event[MAX_HWEVENTS];
37 	u64 events[MAX_HWEVENTS];
38 	unsigned int flags[MAX_HWEVENTS];
39 	/*
40 	 * The order of the MMCR array is:
41 	 *  - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
42 	 *  - 32-bit, MMCR0, MMCR1, MMCR2
43 	 */
44 	unsigned long mmcr[4];
45 	struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
46 	u8  limited_hwidx[MAX_LIMITED_HWCOUNTERS];
47 	u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
48 	unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 	unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
50 
51 	unsigned int group_flag;
52 	int n_txn_start;
53 
54 	/* BHRB bits */
55 	u64				bhrb_filter;	/* BHRB HW branch filter */
56 	int				bhrb_users;
57 	void				*bhrb_context;
58 	struct	perf_branch_stack	bhrb_stack;
59 	struct	perf_branch_entry	bhrb_entries[BHRB_MAX_ENTRIES];
60 };
61 
62 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
63 
64 static struct power_pmu *ppmu;
65 
66 /*
67  * Normally, to ignore kernel events we set the FCS (freeze counters
68  * in supervisor mode) bit in MMCR0, but if the kernel runs with the
69  * hypervisor bit set in the MSR, or if we are running on a processor
70  * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
71  * then we need to use the FCHV bit to ignore kernel events.
72  */
73 static unsigned int freeze_events_kernel = MMCR0_FCS;
74 
75 /*
76  * 32-bit doesn't have MMCRA but does have an MMCR2,
77  * and a few other names are different.
78  */
79 #ifdef CONFIG_PPC32
80 
81 #define MMCR0_FCHV		0
82 #define MMCR0_PMCjCE		MMCR0_PMCnCE
83 #define MMCR0_FC56		0
84 #define MMCR0_PMAO		0
85 #define MMCR0_EBE		0
86 #define MMCR0_BHRBA		0
87 #define MMCR0_PMCC		0
88 #define MMCR0_PMCC_U6		0
89 
90 #define SPRN_MMCRA		SPRN_MMCR2
91 #define MMCRA_SAMPLE_ENABLE	0
92 
93 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
94 {
95 	return 0;
96 }
97 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
98 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
99 {
100 	return 0;
101 }
102 static inline void perf_read_regs(struct pt_regs *regs)
103 {
104 	regs->result = 0;
105 }
106 static inline int perf_intr_is_nmi(struct pt_regs *regs)
107 {
108 	return 0;
109 }
110 
111 static inline int siar_valid(struct pt_regs *regs)
112 {
113 	return 1;
114 }
115 
116 static bool is_ebb_event(struct perf_event *event) { return false; }
117 static int ebb_event_check(struct perf_event *event) { return 0; }
118 static void ebb_event_add(struct perf_event *event) { }
119 static void ebb_switch_out(unsigned long mmcr0) { }
120 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
121 {
122 	return cpuhw->mmcr[0];
123 }
124 
125 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
126 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
127 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
128 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
129 static void pmao_restore_workaround(bool ebb) { }
130 #endif /* CONFIG_PPC32 */
131 
132 static bool regs_use_siar(struct pt_regs *regs)
133 {
134 	return !!regs->result;
135 }
136 
137 /*
138  * Things that are specific to 64-bit implementations.
139  */
140 #ifdef CONFIG_PPC64
141 
142 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
143 {
144 	unsigned long mmcra = regs->dsisr;
145 
146 	if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
147 		unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
148 		if (slot > 1)
149 			return 4 * (slot - 1);
150 	}
151 
152 	return 0;
153 }
154 
155 /*
156  * The user wants a data address recorded.
157  * If we're not doing instruction sampling, give them the SDAR
158  * (sampled data address).  If we are doing instruction sampling, then
159  * only give them the SDAR if it corresponds to the instruction
160  * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
161  * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
162  */
163 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
164 {
165 	unsigned long mmcra = regs->dsisr;
166 	bool sdar_valid;
167 
168 	if (ppmu->flags & PPMU_HAS_SIER)
169 		sdar_valid = regs->dar & SIER_SDAR_VALID;
170 	else {
171 		unsigned long sdsync;
172 
173 		if (ppmu->flags & PPMU_SIAR_VALID)
174 			sdsync = POWER7P_MMCRA_SDAR_VALID;
175 		else if (ppmu->flags & PPMU_ALT_SIPR)
176 			sdsync = POWER6_MMCRA_SDSYNC;
177 		else
178 			sdsync = MMCRA_SDSYNC;
179 
180 		sdar_valid = mmcra & sdsync;
181 	}
182 
183 	if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
184 		*addrp = mfspr(SPRN_SDAR);
185 }
186 
187 static bool regs_sihv(struct pt_regs *regs)
188 {
189 	unsigned long sihv = MMCRA_SIHV;
190 
191 	if (ppmu->flags & PPMU_HAS_SIER)
192 		return !!(regs->dar & SIER_SIHV);
193 
194 	if (ppmu->flags & PPMU_ALT_SIPR)
195 		sihv = POWER6_MMCRA_SIHV;
196 
197 	return !!(regs->dsisr & sihv);
198 }
199 
200 static bool regs_sipr(struct pt_regs *regs)
201 {
202 	unsigned long sipr = MMCRA_SIPR;
203 
204 	if (ppmu->flags & PPMU_HAS_SIER)
205 		return !!(regs->dar & SIER_SIPR);
206 
207 	if (ppmu->flags & PPMU_ALT_SIPR)
208 		sipr = POWER6_MMCRA_SIPR;
209 
210 	return !!(regs->dsisr & sipr);
211 }
212 
213 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
214 {
215 	if (regs->msr & MSR_PR)
216 		return PERF_RECORD_MISC_USER;
217 	if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
218 		return PERF_RECORD_MISC_HYPERVISOR;
219 	return PERF_RECORD_MISC_KERNEL;
220 }
221 
222 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
223 {
224 	bool use_siar = regs_use_siar(regs);
225 
226 	if (!use_siar)
227 		return perf_flags_from_msr(regs);
228 
229 	/*
230 	 * If we don't have flags in MMCRA, rather than using
231 	 * the MSR, we intuit the flags from the address in
232 	 * SIAR which should give slightly more reliable
233 	 * results
234 	 */
235 	if (ppmu->flags & PPMU_NO_SIPR) {
236 		unsigned long siar = mfspr(SPRN_SIAR);
237 		if (siar >= PAGE_OFFSET)
238 			return PERF_RECORD_MISC_KERNEL;
239 		return PERF_RECORD_MISC_USER;
240 	}
241 
242 	/* PR has priority over HV, so order below is important */
243 	if (regs_sipr(regs))
244 		return PERF_RECORD_MISC_USER;
245 
246 	if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
247 		return PERF_RECORD_MISC_HYPERVISOR;
248 
249 	return PERF_RECORD_MISC_KERNEL;
250 }
251 
252 /*
253  * Overload regs->dsisr to store MMCRA so we only need to read it once
254  * on each interrupt.
255  * Overload regs->dar to store SIER if we have it.
256  * Overload regs->result to specify whether we should use the MSR (result
257  * is zero) or the SIAR (result is non zero).
258  */
259 static inline void perf_read_regs(struct pt_regs *regs)
260 {
261 	unsigned long mmcra = mfspr(SPRN_MMCRA);
262 	int marked = mmcra & MMCRA_SAMPLE_ENABLE;
263 	int use_siar;
264 
265 	regs->dsisr = mmcra;
266 
267 	if (ppmu->flags & PPMU_HAS_SIER)
268 		regs->dar = mfspr(SPRN_SIER);
269 
270 	/*
271 	 * If this isn't a PMU exception (eg a software event) the SIAR is
272 	 * not valid. Use pt_regs.
273 	 *
274 	 * If it is a marked event use the SIAR.
275 	 *
276 	 * If the PMU doesn't update the SIAR for non marked events use
277 	 * pt_regs.
278 	 *
279 	 * If the PMU has HV/PR flags then check to see if they
280 	 * place the exception in userspace. If so, use pt_regs. In
281 	 * continuous sampling mode the SIAR and the PMU exception are
282 	 * not synchronised, so they may be many instructions apart.
283 	 * This can result in confusing backtraces. We still want
284 	 * hypervisor samples as well as samples in the kernel with
285 	 * interrupts off hence the userspace check.
286 	 */
287 	if (TRAP(regs) != 0xf00)
288 		use_siar = 0;
289 	else if (marked)
290 		use_siar = 1;
291 	else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
292 		use_siar = 0;
293 	else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
294 		use_siar = 0;
295 	else
296 		use_siar = 1;
297 
298 	regs->result = use_siar;
299 }
300 
301 /*
302  * If interrupts were soft-disabled when a PMU interrupt occurs, treat
303  * it as an NMI.
304  */
305 static inline int perf_intr_is_nmi(struct pt_regs *regs)
306 {
307 	return !regs->softe;
308 }
309 
310 /*
311  * On processors like P7+ that have the SIAR-Valid bit, marked instructions
312  * must be sampled only if the SIAR-valid bit is set.
313  *
314  * For unmarked instructions and for processors that don't have the SIAR-Valid
315  * bit, assume that SIAR is valid.
316  */
317 static inline int siar_valid(struct pt_regs *regs)
318 {
319 	unsigned long mmcra = regs->dsisr;
320 	int marked = mmcra & MMCRA_SAMPLE_ENABLE;
321 
322 	if (marked) {
323 		if (ppmu->flags & PPMU_HAS_SIER)
324 			return regs->dar & SIER_SIAR_VALID;
325 
326 		if (ppmu->flags & PPMU_SIAR_VALID)
327 			return mmcra & POWER7P_MMCRA_SIAR_VALID;
328 	}
329 
330 	return 1;
331 }
332 
333 
334 /* Reset all possible BHRB entries */
335 static void power_pmu_bhrb_reset(void)
336 {
337 	asm volatile(PPC_CLRBHRB);
338 }
339 
340 static void power_pmu_bhrb_enable(struct perf_event *event)
341 {
342 	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
343 
344 	if (!ppmu->bhrb_nr)
345 		return;
346 
347 	/* Clear BHRB if we changed task context to avoid data leaks */
348 	if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
349 		power_pmu_bhrb_reset();
350 		cpuhw->bhrb_context = event->ctx;
351 	}
352 	cpuhw->bhrb_users++;
353 	perf_sched_cb_inc(event->ctx->pmu);
354 }
355 
356 static void power_pmu_bhrb_disable(struct perf_event *event)
357 {
358 	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
359 
360 	if (!ppmu->bhrb_nr)
361 		return;
362 
363 	cpuhw->bhrb_users--;
364 	WARN_ON_ONCE(cpuhw->bhrb_users < 0);
365 	perf_sched_cb_dec(event->ctx->pmu);
366 
367 	if (!cpuhw->disabled && !cpuhw->bhrb_users) {
368 		/* BHRB cannot be turned off when other
369 		 * events are active on the PMU.
370 		 */
371 
372 		/* avoid stale pointer */
373 		cpuhw->bhrb_context = NULL;
374 	}
375 }
376 
377 /* Called from ctxsw to prevent one process's branch entries to
378  * mingle with the other process's entries during context switch.
379  */
380 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
381 {
382 	if (!ppmu->bhrb_nr)
383 		return;
384 
385 	if (sched_in)
386 		power_pmu_bhrb_reset();
387 }
388 /* Calculate the to address for a branch */
389 static __u64 power_pmu_bhrb_to(u64 addr)
390 {
391 	unsigned int instr;
392 	int ret;
393 	__u64 target;
394 
395 	if (is_kernel_addr(addr))
396 		return branch_target((unsigned int *)addr);
397 
398 	/* Userspace: need copy instruction here then translate it */
399 	pagefault_disable();
400 	ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
401 	if (ret) {
402 		pagefault_enable();
403 		return 0;
404 	}
405 	pagefault_enable();
406 
407 	target = branch_target(&instr);
408 	if ((!target) || (instr & BRANCH_ABSOLUTE))
409 		return target;
410 
411 	/* Translate relative branch target from kernel to user address */
412 	return target - (unsigned long)&instr + addr;
413 }
414 
415 /* Processing BHRB entries */
416 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
417 {
418 	u64 val;
419 	u64 addr;
420 	int r_index, u_index, pred;
421 
422 	r_index = 0;
423 	u_index = 0;
424 	while (r_index < ppmu->bhrb_nr) {
425 		/* Assembly read function */
426 		val = read_bhrb(r_index++);
427 		if (!val)
428 			/* Terminal marker: End of valid BHRB entries */
429 			break;
430 		else {
431 			addr = val & BHRB_EA;
432 			pred = val & BHRB_PREDICTION;
433 
434 			if (!addr)
435 				/* invalid entry */
436 				continue;
437 
438 			/* Branches are read most recent first (ie. mfbhrb 0 is
439 			 * the most recent branch).
440 			 * There are two types of valid entries:
441 			 * 1) a target entry which is the to address of a
442 			 *    computed goto like a blr,bctr,btar.  The next
443 			 *    entry read from the bhrb will be branch
444 			 *    corresponding to this target (ie. the actual
445 			 *    blr/bctr/btar instruction).
446 			 * 2) a from address which is an actual branch.  If a
447 			 *    target entry proceeds this, then this is the
448 			 *    matching branch for that target.  If this is not
449 			 *    following a target entry, then this is a branch
450 			 *    where the target is given as an immediate field
451 			 *    in the instruction (ie. an i or b form branch).
452 			 *    In this case we need to read the instruction from
453 			 *    memory to determine the target/to address.
454 			 */
455 
456 			if (val & BHRB_TARGET) {
457 				/* Target branches use two entries
458 				 * (ie. computed gotos/XL form)
459 				 */
460 				cpuhw->bhrb_entries[u_index].to = addr;
461 				cpuhw->bhrb_entries[u_index].mispred = pred;
462 				cpuhw->bhrb_entries[u_index].predicted = ~pred;
463 
464 				/* Get from address in next entry */
465 				val = read_bhrb(r_index++);
466 				addr = val & BHRB_EA;
467 				if (val & BHRB_TARGET) {
468 					/* Shouldn't have two targets in a
469 					   row.. Reset index and try again */
470 					r_index--;
471 					addr = 0;
472 				}
473 				cpuhw->bhrb_entries[u_index].from = addr;
474 			} else {
475 				/* Branches to immediate field
476 				   (ie I or B form) */
477 				cpuhw->bhrb_entries[u_index].from = addr;
478 				cpuhw->bhrb_entries[u_index].to =
479 					power_pmu_bhrb_to(addr);
480 				cpuhw->bhrb_entries[u_index].mispred = pred;
481 				cpuhw->bhrb_entries[u_index].predicted = ~pred;
482 			}
483 			u_index++;
484 
485 		}
486 	}
487 	cpuhw->bhrb_stack.nr = u_index;
488 	return;
489 }
490 
491 static bool is_ebb_event(struct perf_event *event)
492 {
493 	/*
494 	 * This could be a per-PMU callback, but we'd rather avoid the cost. We
495 	 * check that the PMU supports EBB, meaning those that don't can still
496 	 * use bit 63 of the event code for something else if they wish.
497 	 */
498 	return (ppmu->flags & PPMU_ARCH_207S) &&
499 	       ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
500 }
501 
502 static int ebb_event_check(struct perf_event *event)
503 {
504 	struct perf_event *leader = event->group_leader;
505 
506 	/* Event and group leader must agree on EBB */
507 	if (is_ebb_event(leader) != is_ebb_event(event))
508 		return -EINVAL;
509 
510 	if (is_ebb_event(event)) {
511 		if (!(event->attach_state & PERF_ATTACH_TASK))
512 			return -EINVAL;
513 
514 		if (!leader->attr.pinned || !leader->attr.exclusive)
515 			return -EINVAL;
516 
517 		if (event->attr.freq ||
518 		    event->attr.inherit ||
519 		    event->attr.sample_type ||
520 		    event->attr.sample_period ||
521 		    event->attr.enable_on_exec)
522 			return -EINVAL;
523 	}
524 
525 	return 0;
526 }
527 
528 static void ebb_event_add(struct perf_event *event)
529 {
530 	if (!is_ebb_event(event) || current->thread.used_ebb)
531 		return;
532 
533 	/*
534 	 * IFF this is the first time we've added an EBB event, set
535 	 * PMXE in the user MMCR0 so we can detect when it's cleared by
536 	 * userspace. We need this so that we can context switch while
537 	 * userspace is in the EBB handler (where PMXE is 0).
538 	 */
539 	current->thread.used_ebb = 1;
540 	current->thread.mmcr0 |= MMCR0_PMXE;
541 }
542 
543 static void ebb_switch_out(unsigned long mmcr0)
544 {
545 	if (!(mmcr0 & MMCR0_EBE))
546 		return;
547 
548 	current->thread.siar  = mfspr(SPRN_SIAR);
549 	current->thread.sier  = mfspr(SPRN_SIER);
550 	current->thread.sdar  = mfspr(SPRN_SDAR);
551 	current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
552 	current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
553 }
554 
555 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
556 {
557 	unsigned long mmcr0 = cpuhw->mmcr[0];
558 
559 	if (!ebb)
560 		goto out;
561 
562 	/* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
563 	mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
564 
565 	/*
566 	 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
567 	 * with pmao_restore_workaround() because we may add PMAO but we never
568 	 * clear it here.
569 	 */
570 	mmcr0 |= current->thread.mmcr0;
571 
572 	/*
573 	 * Be careful not to set PMXE if userspace had it cleared. This is also
574 	 * compatible with pmao_restore_workaround() because it has already
575 	 * cleared PMXE and we leave PMAO alone.
576 	 */
577 	if (!(current->thread.mmcr0 & MMCR0_PMXE))
578 		mmcr0 &= ~MMCR0_PMXE;
579 
580 	mtspr(SPRN_SIAR, current->thread.siar);
581 	mtspr(SPRN_SIER, current->thread.sier);
582 	mtspr(SPRN_SDAR, current->thread.sdar);
583 
584 	/*
585 	 * Merge the kernel & user values of MMCR2. The semantics we implement
586 	 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
587 	 * but not clear bits. If a task wants to be able to clear bits, ie.
588 	 * unfreeze counters, it should not set exclude_xxx in its events and
589 	 * instead manage the MMCR2 entirely by itself.
590 	 */
591 	mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
592 out:
593 	return mmcr0;
594 }
595 
596 static void pmao_restore_workaround(bool ebb)
597 {
598 	unsigned pmcs[6];
599 
600 	if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
601 		return;
602 
603 	/*
604 	 * On POWER8E there is a hardware defect which affects the PMU context
605 	 * switch logic, ie. power_pmu_disable/enable().
606 	 *
607 	 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
608 	 * by the hardware. Sometime later the actual PMU exception is
609 	 * delivered.
610 	 *
611 	 * If we context switch, or simply disable/enable, the PMU prior to the
612 	 * exception arriving, the exception will be lost when we clear PMAO.
613 	 *
614 	 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
615 	 * set, and this _should_ generate an exception. However because of the
616 	 * defect no exception is generated when we write PMAO, and we get
617 	 * stuck with no counters counting but no exception delivered.
618 	 *
619 	 * The workaround is to detect this case and tweak the hardware to
620 	 * create another pending PMU exception.
621 	 *
622 	 * We do that by setting up PMC6 (cycles) for an imminent overflow and
623 	 * enabling the PMU. That causes a new exception to be generated in the
624 	 * chip, but we don't take it yet because we have interrupts hard
625 	 * disabled. We then write back the PMU state as we want it to be seen
626 	 * by the exception handler. When we reenable interrupts the exception
627 	 * handler will be called and see the correct state.
628 	 *
629 	 * The logic is the same for EBB, except that the exception is gated by
630 	 * us having interrupts hard disabled as well as the fact that we are
631 	 * not in userspace. The exception is finally delivered when we return
632 	 * to userspace.
633 	 */
634 
635 	/* Only if PMAO is set and PMAO_SYNC is clear */
636 	if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
637 		return;
638 
639 	/* If we're doing EBB, only if BESCR[GE] is set */
640 	if (ebb && !(current->thread.bescr & BESCR_GE))
641 		return;
642 
643 	/*
644 	 * We are already soft-disabled in power_pmu_enable(). We need to hard
645 	 * enable to actually prevent the PMU exception from firing.
646 	 */
647 	hard_irq_disable();
648 
649 	/*
650 	 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
651 	 * Using read/write_pmc() in a for loop adds 12 function calls and
652 	 * almost doubles our code size.
653 	 */
654 	pmcs[0] = mfspr(SPRN_PMC1);
655 	pmcs[1] = mfspr(SPRN_PMC2);
656 	pmcs[2] = mfspr(SPRN_PMC3);
657 	pmcs[3] = mfspr(SPRN_PMC4);
658 	pmcs[4] = mfspr(SPRN_PMC5);
659 	pmcs[5] = mfspr(SPRN_PMC6);
660 
661 	/* Ensure all freeze bits are unset */
662 	mtspr(SPRN_MMCR2, 0);
663 
664 	/* Set up PMC6 to overflow in one cycle */
665 	mtspr(SPRN_PMC6, 0x7FFFFFFE);
666 
667 	/* Enable exceptions and unfreeze PMC6 */
668 	mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
669 
670 	/* Now we need to refreeze and restore the PMCs */
671 	mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
672 
673 	mtspr(SPRN_PMC1, pmcs[0]);
674 	mtspr(SPRN_PMC2, pmcs[1]);
675 	mtspr(SPRN_PMC3, pmcs[2]);
676 	mtspr(SPRN_PMC4, pmcs[3]);
677 	mtspr(SPRN_PMC5, pmcs[4]);
678 	mtspr(SPRN_PMC6, pmcs[5]);
679 }
680 #endif /* CONFIG_PPC64 */
681 
682 static void perf_event_interrupt(struct pt_regs *regs);
683 
684 /*
685  * Read one performance monitor counter (PMC).
686  */
687 static unsigned long read_pmc(int idx)
688 {
689 	unsigned long val;
690 
691 	switch (idx) {
692 	case 1:
693 		val = mfspr(SPRN_PMC1);
694 		break;
695 	case 2:
696 		val = mfspr(SPRN_PMC2);
697 		break;
698 	case 3:
699 		val = mfspr(SPRN_PMC3);
700 		break;
701 	case 4:
702 		val = mfspr(SPRN_PMC4);
703 		break;
704 	case 5:
705 		val = mfspr(SPRN_PMC5);
706 		break;
707 	case 6:
708 		val = mfspr(SPRN_PMC6);
709 		break;
710 #ifdef CONFIG_PPC64
711 	case 7:
712 		val = mfspr(SPRN_PMC7);
713 		break;
714 	case 8:
715 		val = mfspr(SPRN_PMC8);
716 		break;
717 #endif /* CONFIG_PPC64 */
718 	default:
719 		printk(KERN_ERR "oops trying to read PMC%d\n", idx);
720 		val = 0;
721 	}
722 	return val;
723 }
724 
725 /*
726  * Write one PMC.
727  */
728 static void write_pmc(int idx, unsigned long val)
729 {
730 	switch (idx) {
731 	case 1:
732 		mtspr(SPRN_PMC1, val);
733 		break;
734 	case 2:
735 		mtspr(SPRN_PMC2, val);
736 		break;
737 	case 3:
738 		mtspr(SPRN_PMC3, val);
739 		break;
740 	case 4:
741 		mtspr(SPRN_PMC4, val);
742 		break;
743 	case 5:
744 		mtspr(SPRN_PMC5, val);
745 		break;
746 	case 6:
747 		mtspr(SPRN_PMC6, val);
748 		break;
749 #ifdef CONFIG_PPC64
750 	case 7:
751 		mtspr(SPRN_PMC7, val);
752 		break;
753 	case 8:
754 		mtspr(SPRN_PMC8, val);
755 		break;
756 #endif /* CONFIG_PPC64 */
757 	default:
758 		printk(KERN_ERR "oops trying to write PMC%d\n", idx);
759 	}
760 }
761 
762 /* Called from sysrq_handle_showregs() */
763 void perf_event_print_debug(void)
764 {
765 	unsigned long sdar, sier, flags;
766 	u32 pmcs[MAX_HWEVENTS];
767 	int i;
768 
769 	if (!ppmu->n_counter)
770 		return;
771 
772 	local_irq_save(flags);
773 
774 	pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
775 		 smp_processor_id(), ppmu->name, ppmu->n_counter);
776 
777 	for (i = 0; i < ppmu->n_counter; i++)
778 		pmcs[i] = read_pmc(i + 1);
779 
780 	for (; i < MAX_HWEVENTS; i++)
781 		pmcs[i] = 0xdeadbeef;
782 
783 	pr_info("PMC1:  %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
784 		 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
785 
786 	if (ppmu->n_counter > 4)
787 		pr_info("PMC5:  %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
788 			 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
789 
790 	pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
791 		mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
792 
793 	sdar = sier = 0;
794 #ifdef CONFIG_PPC64
795 	sdar = mfspr(SPRN_SDAR);
796 
797 	if (ppmu->flags & PPMU_HAS_SIER)
798 		sier = mfspr(SPRN_SIER);
799 
800 	if (ppmu->flags & PPMU_ARCH_207S) {
801 		pr_info("MMCR2: %016lx EBBHR: %016lx\n",
802 			mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
803 		pr_info("EBBRR: %016lx BESCR: %016lx\n",
804 			mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
805 	}
806 #endif
807 	pr_info("SIAR:  %016lx SDAR:  %016lx SIER:  %016lx\n",
808 		mfspr(SPRN_SIAR), sdar, sier);
809 
810 	local_irq_restore(flags);
811 }
812 
813 /*
814  * Check if a set of events can all go on the PMU at once.
815  * If they can't, this will look at alternative codes for the events
816  * and see if any combination of alternative codes is feasible.
817  * The feasible set is returned in event_id[].
818  */
819 static int power_check_constraints(struct cpu_hw_events *cpuhw,
820 				   u64 event_id[], unsigned int cflags[],
821 				   int n_ev)
822 {
823 	unsigned long mask, value, nv;
824 	unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
825 	int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
826 	int i, j;
827 	unsigned long addf = ppmu->add_fields;
828 	unsigned long tadd = ppmu->test_adder;
829 
830 	if (n_ev > ppmu->n_counter)
831 		return -1;
832 
833 	/* First see if the events will go on as-is */
834 	for (i = 0; i < n_ev; ++i) {
835 		if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
836 		    && !ppmu->limited_pmc_event(event_id[i])) {
837 			ppmu->get_alternatives(event_id[i], cflags[i],
838 					       cpuhw->alternatives[i]);
839 			event_id[i] = cpuhw->alternatives[i][0];
840 		}
841 		if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
842 					 &cpuhw->avalues[i][0]))
843 			return -1;
844 	}
845 	value = mask = 0;
846 	for (i = 0; i < n_ev; ++i) {
847 		nv = (value | cpuhw->avalues[i][0]) +
848 			(value & cpuhw->avalues[i][0] & addf);
849 		if ((((nv + tadd) ^ value) & mask) != 0 ||
850 		    (((nv + tadd) ^ cpuhw->avalues[i][0]) &
851 		     cpuhw->amasks[i][0]) != 0)
852 			break;
853 		value = nv;
854 		mask |= cpuhw->amasks[i][0];
855 	}
856 	if (i == n_ev)
857 		return 0;	/* all OK */
858 
859 	/* doesn't work, gather alternatives... */
860 	if (!ppmu->get_alternatives)
861 		return -1;
862 	for (i = 0; i < n_ev; ++i) {
863 		choice[i] = 0;
864 		n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
865 						  cpuhw->alternatives[i]);
866 		for (j = 1; j < n_alt[i]; ++j)
867 			ppmu->get_constraint(cpuhw->alternatives[i][j],
868 					     &cpuhw->amasks[i][j],
869 					     &cpuhw->avalues[i][j]);
870 	}
871 
872 	/* enumerate all possibilities and see if any will work */
873 	i = 0;
874 	j = -1;
875 	value = mask = nv = 0;
876 	while (i < n_ev) {
877 		if (j >= 0) {
878 			/* we're backtracking, restore context */
879 			value = svalues[i];
880 			mask = smasks[i];
881 			j = choice[i];
882 		}
883 		/*
884 		 * See if any alternative k for event_id i,
885 		 * where k > j, will satisfy the constraints.
886 		 */
887 		while (++j < n_alt[i]) {
888 			nv = (value | cpuhw->avalues[i][j]) +
889 				(value & cpuhw->avalues[i][j] & addf);
890 			if ((((nv + tadd) ^ value) & mask) == 0 &&
891 			    (((nv + tadd) ^ cpuhw->avalues[i][j])
892 			     & cpuhw->amasks[i][j]) == 0)
893 				break;
894 		}
895 		if (j >= n_alt[i]) {
896 			/*
897 			 * No feasible alternative, backtrack
898 			 * to event_id i-1 and continue enumerating its
899 			 * alternatives from where we got up to.
900 			 */
901 			if (--i < 0)
902 				return -1;
903 		} else {
904 			/*
905 			 * Found a feasible alternative for event_id i,
906 			 * remember where we got up to with this event_id,
907 			 * go on to the next event_id, and start with
908 			 * the first alternative for it.
909 			 */
910 			choice[i] = j;
911 			svalues[i] = value;
912 			smasks[i] = mask;
913 			value = nv;
914 			mask |= cpuhw->amasks[i][j];
915 			++i;
916 			j = -1;
917 		}
918 	}
919 
920 	/* OK, we have a feasible combination, tell the caller the solution */
921 	for (i = 0; i < n_ev; ++i)
922 		event_id[i] = cpuhw->alternatives[i][choice[i]];
923 	return 0;
924 }
925 
926 /*
927  * Check if newly-added events have consistent settings for
928  * exclude_{user,kernel,hv} with each other and any previously
929  * added events.
930  */
931 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
932 			  int n_prev, int n_new)
933 {
934 	int eu = 0, ek = 0, eh = 0;
935 	int i, n, first;
936 	struct perf_event *event;
937 
938 	/*
939 	 * If the PMU we're on supports per event exclude settings then we
940 	 * don't need to do any of this logic. NB. This assumes no PMU has both
941 	 * per event exclude and limited PMCs.
942 	 */
943 	if (ppmu->flags & PPMU_ARCH_207S)
944 		return 0;
945 
946 	n = n_prev + n_new;
947 	if (n <= 1)
948 		return 0;
949 
950 	first = 1;
951 	for (i = 0; i < n; ++i) {
952 		if (cflags[i] & PPMU_LIMITED_PMC_OK) {
953 			cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
954 			continue;
955 		}
956 		event = ctrs[i];
957 		if (first) {
958 			eu = event->attr.exclude_user;
959 			ek = event->attr.exclude_kernel;
960 			eh = event->attr.exclude_hv;
961 			first = 0;
962 		} else if (event->attr.exclude_user != eu ||
963 			   event->attr.exclude_kernel != ek ||
964 			   event->attr.exclude_hv != eh) {
965 			return -EAGAIN;
966 		}
967 	}
968 
969 	if (eu || ek || eh)
970 		for (i = 0; i < n; ++i)
971 			if (cflags[i] & PPMU_LIMITED_PMC_OK)
972 				cflags[i] |= PPMU_LIMITED_PMC_REQD;
973 
974 	return 0;
975 }
976 
977 static u64 check_and_compute_delta(u64 prev, u64 val)
978 {
979 	u64 delta = (val - prev) & 0xfffffffful;
980 
981 	/*
982 	 * POWER7 can roll back counter values, if the new value is smaller
983 	 * than the previous value it will cause the delta and the counter to
984 	 * have bogus values unless we rolled a counter over.  If a coutner is
985 	 * rolled back, it will be smaller, but within 256, which is the maximum
986 	 * number of events to rollback at once.  If we dectect a rollback
987 	 * return 0.  This can lead to a small lack of precision in the
988 	 * counters.
989 	 */
990 	if (prev > val && (prev - val) < 256)
991 		delta = 0;
992 
993 	return delta;
994 }
995 
996 static void power_pmu_read(struct perf_event *event)
997 {
998 	s64 val, delta, prev;
999 
1000 	if (event->hw.state & PERF_HES_STOPPED)
1001 		return;
1002 
1003 	if (!event->hw.idx)
1004 		return;
1005 
1006 	if (is_ebb_event(event)) {
1007 		val = read_pmc(event->hw.idx);
1008 		local64_set(&event->hw.prev_count, val);
1009 		return;
1010 	}
1011 
1012 	/*
1013 	 * Performance monitor interrupts come even when interrupts
1014 	 * are soft-disabled, as long as interrupts are hard-enabled.
1015 	 * Therefore we treat them like NMIs.
1016 	 */
1017 	do {
1018 		prev = local64_read(&event->hw.prev_count);
1019 		barrier();
1020 		val = read_pmc(event->hw.idx);
1021 		delta = check_and_compute_delta(prev, val);
1022 		if (!delta)
1023 			return;
1024 	} while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1025 
1026 	local64_add(delta, &event->count);
1027 
1028 	/*
1029 	 * A number of places program the PMC with (0x80000000 - period_left).
1030 	 * We never want period_left to be less than 1 because we will program
1031 	 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1032 	 * roll around to 0 before taking an exception. We have seen this
1033 	 * on POWER8.
1034 	 *
1035 	 * To fix this, clamp the minimum value of period_left to 1.
1036 	 */
1037 	do {
1038 		prev = local64_read(&event->hw.period_left);
1039 		val = prev - delta;
1040 		if (val < 1)
1041 			val = 1;
1042 	} while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1043 }
1044 
1045 /*
1046  * On some machines, PMC5 and PMC6 can't be written, don't respect
1047  * the freeze conditions, and don't generate interrupts.  This tells
1048  * us if `event' is using such a PMC.
1049  */
1050 static int is_limited_pmc(int pmcnum)
1051 {
1052 	return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1053 		&& (pmcnum == 5 || pmcnum == 6);
1054 }
1055 
1056 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1057 				    unsigned long pmc5, unsigned long pmc6)
1058 {
1059 	struct perf_event *event;
1060 	u64 val, prev, delta;
1061 	int i;
1062 
1063 	for (i = 0; i < cpuhw->n_limited; ++i) {
1064 		event = cpuhw->limited_counter[i];
1065 		if (!event->hw.idx)
1066 			continue;
1067 		val = (event->hw.idx == 5) ? pmc5 : pmc6;
1068 		prev = local64_read(&event->hw.prev_count);
1069 		event->hw.idx = 0;
1070 		delta = check_and_compute_delta(prev, val);
1071 		if (delta)
1072 			local64_add(delta, &event->count);
1073 	}
1074 }
1075 
1076 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1077 				  unsigned long pmc5, unsigned long pmc6)
1078 {
1079 	struct perf_event *event;
1080 	u64 val, prev;
1081 	int i;
1082 
1083 	for (i = 0; i < cpuhw->n_limited; ++i) {
1084 		event = cpuhw->limited_counter[i];
1085 		event->hw.idx = cpuhw->limited_hwidx[i];
1086 		val = (event->hw.idx == 5) ? pmc5 : pmc6;
1087 		prev = local64_read(&event->hw.prev_count);
1088 		if (check_and_compute_delta(prev, val))
1089 			local64_set(&event->hw.prev_count, val);
1090 		perf_event_update_userpage(event);
1091 	}
1092 }
1093 
1094 /*
1095  * Since limited events don't respect the freeze conditions, we
1096  * have to read them immediately after freezing or unfreezing the
1097  * other events.  We try to keep the values from the limited
1098  * events as consistent as possible by keeping the delay (in
1099  * cycles and instructions) between freezing/unfreezing and reading
1100  * the limited events as small and consistent as possible.
1101  * Therefore, if any limited events are in use, we read them
1102  * both, and always in the same order, to minimize variability,
1103  * and do it inside the same asm that writes MMCR0.
1104  */
1105 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1106 {
1107 	unsigned long pmc5, pmc6;
1108 
1109 	if (!cpuhw->n_limited) {
1110 		mtspr(SPRN_MMCR0, mmcr0);
1111 		return;
1112 	}
1113 
1114 	/*
1115 	 * Write MMCR0, then read PMC5 and PMC6 immediately.
1116 	 * To ensure we don't get a performance monitor interrupt
1117 	 * between writing MMCR0 and freezing/thawing the limited
1118 	 * events, we first write MMCR0 with the event overflow
1119 	 * interrupt enable bits turned off.
1120 	 */
1121 	asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1122 		     : "=&r" (pmc5), "=&r" (pmc6)
1123 		     : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1124 		       "i" (SPRN_MMCR0),
1125 		       "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1126 
1127 	if (mmcr0 & MMCR0_FC)
1128 		freeze_limited_counters(cpuhw, pmc5, pmc6);
1129 	else
1130 		thaw_limited_counters(cpuhw, pmc5, pmc6);
1131 
1132 	/*
1133 	 * Write the full MMCR0 including the event overflow interrupt
1134 	 * enable bits, if necessary.
1135 	 */
1136 	if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1137 		mtspr(SPRN_MMCR0, mmcr0);
1138 }
1139 
1140 /*
1141  * Disable all events to prevent PMU interrupts and to allow
1142  * events to be added or removed.
1143  */
1144 static void power_pmu_disable(struct pmu *pmu)
1145 {
1146 	struct cpu_hw_events *cpuhw;
1147 	unsigned long flags, mmcr0, val;
1148 
1149 	if (!ppmu)
1150 		return;
1151 	local_irq_save(flags);
1152 	cpuhw = this_cpu_ptr(&cpu_hw_events);
1153 
1154 	if (!cpuhw->disabled) {
1155 		/*
1156 		 * Check if we ever enabled the PMU on this cpu.
1157 		 */
1158 		if (!cpuhw->pmcs_enabled) {
1159 			ppc_enable_pmcs();
1160 			cpuhw->pmcs_enabled = 1;
1161 		}
1162 
1163 		/*
1164 		 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1165 		 */
1166 		val  = mmcr0 = mfspr(SPRN_MMCR0);
1167 		val |= MMCR0_FC;
1168 		val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1169 			 MMCR0_FC56);
1170 
1171 		/*
1172 		 * The barrier is to make sure the mtspr has been
1173 		 * executed and the PMU has frozen the events etc.
1174 		 * before we return.
1175 		 */
1176 		write_mmcr0(cpuhw, val);
1177 		mb();
1178 
1179 		/*
1180 		 * Disable instruction sampling if it was enabled
1181 		 */
1182 		if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1183 			mtspr(SPRN_MMCRA,
1184 			      cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1185 			mb();
1186 		}
1187 
1188 		cpuhw->disabled = 1;
1189 		cpuhw->n_added = 0;
1190 
1191 		ebb_switch_out(mmcr0);
1192 	}
1193 
1194 	local_irq_restore(flags);
1195 }
1196 
1197 /*
1198  * Re-enable all events if disable == 0.
1199  * If we were previously disabled and events were added, then
1200  * put the new config on the PMU.
1201  */
1202 static void power_pmu_enable(struct pmu *pmu)
1203 {
1204 	struct perf_event *event;
1205 	struct cpu_hw_events *cpuhw;
1206 	unsigned long flags;
1207 	long i;
1208 	unsigned long val, mmcr0;
1209 	s64 left;
1210 	unsigned int hwc_index[MAX_HWEVENTS];
1211 	int n_lim;
1212 	int idx;
1213 	bool ebb;
1214 
1215 	if (!ppmu)
1216 		return;
1217 	local_irq_save(flags);
1218 
1219 	cpuhw = this_cpu_ptr(&cpu_hw_events);
1220 	if (!cpuhw->disabled)
1221 		goto out;
1222 
1223 	if (cpuhw->n_events == 0) {
1224 		ppc_set_pmu_inuse(0);
1225 		goto out;
1226 	}
1227 
1228 	cpuhw->disabled = 0;
1229 
1230 	/*
1231 	 * EBB requires an exclusive group and all events must have the EBB
1232 	 * flag set, or not set, so we can just check a single event. Also we
1233 	 * know we have at least one event.
1234 	 */
1235 	ebb = is_ebb_event(cpuhw->event[0]);
1236 
1237 	/*
1238 	 * If we didn't change anything, or only removed events,
1239 	 * no need to recalculate MMCR* settings and reset the PMCs.
1240 	 * Just reenable the PMU with the current MMCR* settings
1241 	 * (possibly updated for removal of events).
1242 	 */
1243 	if (!cpuhw->n_added) {
1244 		mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1245 		mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1246 		goto out_enable;
1247 	}
1248 
1249 	/*
1250 	 * Clear all MMCR settings and recompute them for the new set of events.
1251 	 */
1252 	memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1253 
1254 	if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1255 			       cpuhw->mmcr, cpuhw->event)) {
1256 		/* shouldn't ever get here */
1257 		printk(KERN_ERR "oops compute_mmcr failed\n");
1258 		goto out;
1259 	}
1260 
1261 	if (!(ppmu->flags & PPMU_ARCH_207S)) {
1262 		/*
1263 		 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1264 		 * bits for the first event. We have already checked that all
1265 		 * events have the same value for these bits as the first event.
1266 		 */
1267 		event = cpuhw->event[0];
1268 		if (event->attr.exclude_user)
1269 			cpuhw->mmcr[0] |= MMCR0_FCP;
1270 		if (event->attr.exclude_kernel)
1271 			cpuhw->mmcr[0] |= freeze_events_kernel;
1272 		if (event->attr.exclude_hv)
1273 			cpuhw->mmcr[0] |= MMCR0_FCHV;
1274 	}
1275 
1276 	/*
1277 	 * Write the new configuration to MMCR* with the freeze
1278 	 * bit set and set the hardware events to their initial values.
1279 	 * Then unfreeze the events.
1280 	 */
1281 	ppc_set_pmu_inuse(1);
1282 	mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1283 	mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1284 	mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1285 				| MMCR0_FC);
1286 	if (ppmu->flags & PPMU_ARCH_207S)
1287 		mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1288 
1289 	/*
1290 	 * Read off any pre-existing events that need to move
1291 	 * to another PMC.
1292 	 */
1293 	for (i = 0; i < cpuhw->n_events; ++i) {
1294 		event = cpuhw->event[i];
1295 		if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1296 			power_pmu_read(event);
1297 			write_pmc(event->hw.idx, 0);
1298 			event->hw.idx = 0;
1299 		}
1300 	}
1301 
1302 	/*
1303 	 * Initialize the PMCs for all the new and moved events.
1304 	 */
1305 	cpuhw->n_limited = n_lim = 0;
1306 	for (i = 0; i < cpuhw->n_events; ++i) {
1307 		event = cpuhw->event[i];
1308 		if (event->hw.idx)
1309 			continue;
1310 		idx = hwc_index[i] + 1;
1311 		if (is_limited_pmc(idx)) {
1312 			cpuhw->limited_counter[n_lim] = event;
1313 			cpuhw->limited_hwidx[n_lim] = idx;
1314 			++n_lim;
1315 			continue;
1316 		}
1317 
1318 		if (ebb)
1319 			val = local64_read(&event->hw.prev_count);
1320 		else {
1321 			val = 0;
1322 			if (event->hw.sample_period) {
1323 				left = local64_read(&event->hw.period_left);
1324 				if (left < 0x80000000L)
1325 					val = 0x80000000L - left;
1326 			}
1327 			local64_set(&event->hw.prev_count, val);
1328 		}
1329 
1330 		event->hw.idx = idx;
1331 		if (event->hw.state & PERF_HES_STOPPED)
1332 			val = 0;
1333 		write_pmc(idx, val);
1334 
1335 		perf_event_update_userpage(event);
1336 	}
1337 	cpuhw->n_limited = n_lim;
1338 	cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1339 
1340  out_enable:
1341 	pmao_restore_workaround(ebb);
1342 
1343 	mmcr0 = ebb_switch_in(ebb, cpuhw);
1344 
1345 	mb();
1346 	if (cpuhw->bhrb_users)
1347 		ppmu->config_bhrb(cpuhw->bhrb_filter);
1348 
1349 	write_mmcr0(cpuhw, mmcr0);
1350 
1351 	/*
1352 	 * Enable instruction sampling if necessary
1353 	 */
1354 	if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1355 		mb();
1356 		mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1357 	}
1358 
1359  out:
1360 
1361 	local_irq_restore(flags);
1362 }
1363 
1364 static int collect_events(struct perf_event *group, int max_count,
1365 			  struct perf_event *ctrs[], u64 *events,
1366 			  unsigned int *flags)
1367 {
1368 	int n = 0;
1369 	struct perf_event *event;
1370 
1371 	if (!is_software_event(group)) {
1372 		if (n >= max_count)
1373 			return -1;
1374 		ctrs[n] = group;
1375 		flags[n] = group->hw.event_base;
1376 		events[n++] = group->hw.config;
1377 	}
1378 	list_for_each_entry(event, &group->sibling_list, group_entry) {
1379 		if (!is_software_event(event) &&
1380 		    event->state != PERF_EVENT_STATE_OFF) {
1381 			if (n >= max_count)
1382 				return -1;
1383 			ctrs[n] = event;
1384 			flags[n] = event->hw.event_base;
1385 			events[n++] = event->hw.config;
1386 		}
1387 	}
1388 	return n;
1389 }
1390 
1391 /*
1392  * Add a event to the PMU.
1393  * If all events are not already frozen, then we disable and
1394  * re-enable the PMU in order to get hw_perf_enable to do the
1395  * actual work of reconfiguring the PMU.
1396  */
1397 static int power_pmu_add(struct perf_event *event, int ef_flags)
1398 {
1399 	struct cpu_hw_events *cpuhw;
1400 	unsigned long flags;
1401 	int n0;
1402 	int ret = -EAGAIN;
1403 
1404 	local_irq_save(flags);
1405 	perf_pmu_disable(event->pmu);
1406 
1407 	/*
1408 	 * Add the event to the list (if there is room)
1409 	 * and check whether the total set is still feasible.
1410 	 */
1411 	cpuhw = this_cpu_ptr(&cpu_hw_events);
1412 	n0 = cpuhw->n_events;
1413 	if (n0 >= ppmu->n_counter)
1414 		goto out;
1415 	cpuhw->event[n0] = event;
1416 	cpuhw->events[n0] = event->hw.config;
1417 	cpuhw->flags[n0] = event->hw.event_base;
1418 
1419 	/*
1420 	 * This event may have been disabled/stopped in record_and_restart()
1421 	 * because we exceeded the ->event_limit. If re-starting the event,
1422 	 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1423 	 * notification is re-enabled.
1424 	 */
1425 	if (!(ef_flags & PERF_EF_START))
1426 		event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1427 	else
1428 		event->hw.state = 0;
1429 
1430 	/*
1431 	 * If group events scheduling transaction was started,
1432 	 * skip the schedulability test here, it will be performed
1433 	 * at commit time(->commit_txn) as a whole
1434 	 */
1435 	if (cpuhw->group_flag & PERF_EVENT_TXN)
1436 		goto nocheck;
1437 
1438 	if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1439 		goto out;
1440 	if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1441 		goto out;
1442 	event->hw.config = cpuhw->events[n0];
1443 
1444 nocheck:
1445 	ebb_event_add(event);
1446 
1447 	++cpuhw->n_events;
1448 	++cpuhw->n_added;
1449 
1450 	ret = 0;
1451  out:
1452 	if (has_branch_stack(event)) {
1453 		power_pmu_bhrb_enable(event);
1454 		cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1455 					event->attr.branch_sample_type);
1456 	}
1457 
1458 	perf_pmu_enable(event->pmu);
1459 	local_irq_restore(flags);
1460 	return ret;
1461 }
1462 
1463 /*
1464  * Remove a event from the PMU.
1465  */
1466 static void power_pmu_del(struct perf_event *event, int ef_flags)
1467 {
1468 	struct cpu_hw_events *cpuhw;
1469 	long i;
1470 	unsigned long flags;
1471 
1472 	local_irq_save(flags);
1473 	perf_pmu_disable(event->pmu);
1474 
1475 	power_pmu_read(event);
1476 
1477 	cpuhw = this_cpu_ptr(&cpu_hw_events);
1478 	for (i = 0; i < cpuhw->n_events; ++i) {
1479 		if (event == cpuhw->event[i]) {
1480 			while (++i < cpuhw->n_events) {
1481 				cpuhw->event[i-1] = cpuhw->event[i];
1482 				cpuhw->events[i-1] = cpuhw->events[i];
1483 				cpuhw->flags[i-1] = cpuhw->flags[i];
1484 			}
1485 			--cpuhw->n_events;
1486 			ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1487 			if (event->hw.idx) {
1488 				write_pmc(event->hw.idx, 0);
1489 				event->hw.idx = 0;
1490 			}
1491 			perf_event_update_userpage(event);
1492 			break;
1493 		}
1494 	}
1495 	for (i = 0; i < cpuhw->n_limited; ++i)
1496 		if (event == cpuhw->limited_counter[i])
1497 			break;
1498 	if (i < cpuhw->n_limited) {
1499 		while (++i < cpuhw->n_limited) {
1500 			cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1501 			cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1502 		}
1503 		--cpuhw->n_limited;
1504 	}
1505 	if (cpuhw->n_events == 0) {
1506 		/* disable exceptions if no events are running */
1507 		cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1508 	}
1509 
1510 	if (has_branch_stack(event))
1511 		power_pmu_bhrb_disable(event);
1512 
1513 	perf_pmu_enable(event->pmu);
1514 	local_irq_restore(flags);
1515 }
1516 
1517 /*
1518  * POWER-PMU does not support disabling individual counters, hence
1519  * program their cycle counter to their max value and ignore the interrupts.
1520  */
1521 
1522 static void power_pmu_start(struct perf_event *event, int ef_flags)
1523 {
1524 	unsigned long flags;
1525 	s64 left;
1526 	unsigned long val;
1527 
1528 	if (!event->hw.idx || !event->hw.sample_period)
1529 		return;
1530 
1531 	if (!(event->hw.state & PERF_HES_STOPPED))
1532 		return;
1533 
1534 	if (ef_flags & PERF_EF_RELOAD)
1535 		WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1536 
1537 	local_irq_save(flags);
1538 	perf_pmu_disable(event->pmu);
1539 
1540 	event->hw.state = 0;
1541 	left = local64_read(&event->hw.period_left);
1542 
1543 	val = 0;
1544 	if (left < 0x80000000L)
1545 		val = 0x80000000L - left;
1546 
1547 	write_pmc(event->hw.idx, val);
1548 
1549 	perf_event_update_userpage(event);
1550 	perf_pmu_enable(event->pmu);
1551 	local_irq_restore(flags);
1552 }
1553 
1554 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1555 {
1556 	unsigned long flags;
1557 
1558 	if (!event->hw.idx || !event->hw.sample_period)
1559 		return;
1560 
1561 	if (event->hw.state & PERF_HES_STOPPED)
1562 		return;
1563 
1564 	local_irq_save(flags);
1565 	perf_pmu_disable(event->pmu);
1566 
1567 	power_pmu_read(event);
1568 	event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1569 	write_pmc(event->hw.idx, 0);
1570 
1571 	perf_event_update_userpage(event);
1572 	perf_pmu_enable(event->pmu);
1573 	local_irq_restore(flags);
1574 }
1575 
1576 /*
1577  * Start group events scheduling transaction
1578  * Set the flag to make pmu::enable() not perform the
1579  * schedulability test, it will be performed at commit time
1580  */
1581 static void power_pmu_start_txn(struct pmu *pmu)
1582 {
1583 	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1584 
1585 	perf_pmu_disable(pmu);
1586 	cpuhw->group_flag |= PERF_EVENT_TXN;
1587 	cpuhw->n_txn_start = cpuhw->n_events;
1588 }
1589 
1590 /*
1591  * Stop group events scheduling transaction
1592  * Clear the flag and pmu::enable() will perform the
1593  * schedulability test.
1594  */
1595 static void power_pmu_cancel_txn(struct pmu *pmu)
1596 {
1597 	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1598 
1599 	cpuhw->group_flag &= ~PERF_EVENT_TXN;
1600 	perf_pmu_enable(pmu);
1601 }
1602 
1603 /*
1604  * Commit group events scheduling transaction
1605  * Perform the group schedulability test as a whole
1606  * Return 0 if success
1607  */
1608 static int power_pmu_commit_txn(struct pmu *pmu)
1609 {
1610 	struct cpu_hw_events *cpuhw;
1611 	long i, n;
1612 
1613 	if (!ppmu)
1614 		return -EAGAIN;
1615 	cpuhw = this_cpu_ptr(&cpu_hw_events);
1616 	n = cpuhw->n_events;
1617 	if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1618 		return -EAGAIN;
1619 	i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1620 	if (i < 0)
1621 		return -EAGAIN;
1622 
1623 	for (i = cpuhw->n_txn_start; i < n; ++i)
1624 		cpuhw->event[i]->hw.config = cpuhw->events[i];
1625 
1626 	cpuhw->group_flag &= ~PERF_EVENT_TXN;
1627 	perf_pmu_enable(pmu);
1628 	return 0;
1629 }
1630 
1631 /*
1632  * Return 1 if we might be able to put event on a limited PMC,
1633  * or 0 if not.
1634  * A event can only go on a limited PMC if it counts something
1635  * that a limited PMC can count, doesn't require interrupts, and
1636  * doesn't exclude any processor mode.
1637  */
1638 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1639 				 unsigned int flags)
1640 {
1641 	int n;
1642 	u64 alt[MAX_EVENT_ALTERNATIVES];
1643 
1644 	if (event->attr.exclude_user
1645 	    || event->attr.exclude_kernel
1646 	    || event->attr.exclude_hv
1647 	    || event->attr.sample_period)
1648 		return 0;
1649 
1650 	if (ppmu->limited_pmc_event(ev))
1651 		return 1;
1652 
1653 	/*
1654 	 * The requested event_id isn't on a limited PMC already;
1655 	 * see if any alternative code goes on a limited PMC.
1656 	 */
1657 	if (!ppmu->get_alternatives)
1658 		return 0;
1659 
1660 	flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1661 	n = ppmu->get_alternatives(ev, flags, alt);
1662 
1663 	return n > 0;
1664 }
1665 
1666 /*
1667  * Find an alternative event_id that goes on a normal PMC, if possible,
1668  * and return the event_id code, or 0 if there is no such alternative.
1669  * (Note: event_id code 0 is "don't count" on all machines.)
1670  */
1671 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1672 {
1673 	u64 alt[MAX_EVENT_ALTERNATIVES];
1674 	int n;
1675 
1676 	flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1677 	n = ppmu->get_alternatives(ev, flags, alt);
1678 	if (!n)
1679 		return 0;
1680 	return alt[0];
1681 }
1682 
1683 /* Number of perf_events counting hardware events */
1684 static atomic_t num_events;
1685 /* Used to avoid races in calling reserve/release_pmc_hardware */
1686 static DEFINE_MUTEX(pmc_reserve_mutex);
1687 
1688 /*
1689  * Release the PMU if this is the last perf_event.
1690  */
1691 static void hw_perf_event_destroy(struct perf_event *event)
1692 {
1693 	if (!atomic_add_unless(&num_events, -1, 1)) {
1694 		mutex_lock(&pmc_reserve_mutex);
1695 		if (atomic_dec_return(&num_events) == 0)
1696 			release_pmc_hardware();
1697 		mutex_unlock(&pmc_reserve_mutex);
1698 	}
1699 }
1700 
1701 /*
1702  * Translate a generic cache event_id config to a raw event_id code.
1703  */
1704 static int hw_perf_cache_event(u64 config, u64 *eventp)
1705 {
1706 	unsigned long type, op, result;
1707 	int ev;
1708 
1709 	if (!ppmu->cache_events)
1710 		return -EINVAL;
1711 
1712 	/* unpack config */
1713 	type = config & 0xff;
1714 	op = (config >> 8) & 0xff;
1715 	result = (config >> 16) & 0xff;
1716 
1717 	if (type >= PERF_COUNT_HW_CACHE_MAX ||
1718 	    op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1719 	    result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1720 		return -EINVAL;
1721 
1722 	ev = (*ppmu->cache_events)[type][op][result];
1723 	if (ev == 0)
1724 		return -EOPNOTSUPP;
1725 	if (ev == -1)
1726 		return -EINVAL;
1727 	*eventp = ev;
1728 	return 0;
1729 }
1730 
1731 static int power_pmu_event_init(struct perf_event *event)
1732 {
1733 	u64 ev;
1734 	unsigned long flags;
1735 	struct perf_event *ctrs[MAX_HWEVENTS];
1736 	u64 events[MAX_HWEVENTS];
1737 	unsigned int cflags[MAX_HWEVENTS];
1738 	int n;
1739 	int err;
1740 	struct cpu_hw_events *cpuhw;
1741 
1742 	if (!ppmu)
1743 		return -ENOENT;
1744 
1745 	if (has_branch_stack(event)) {
1746 	        /* PMU has BHRB enabled */
1747 		if (!(ppmu->flags & PPMU_ARCH_207S))
1748 			return -EOPNOTSUPP;
1749 	}
1750 
1751 	switch (event->attr.type) {
1752 	case PERF_TYPE_HARDWARE:
1753 		ev = event->attr.config;
1754 		if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1755 			return -EOPNOTSUPP;
1756 		ev = ppmu->generic_events[ev];
1757 		break;
1758 	case PERF_TYPE_HW_CACHE:
1759 		err = hw_perf_cache_event(event->attr.config, &ev);
1760 		if (err)
1761 			return err;
1762 		break;
1763 	case PERF_TYPE_RAW:
1764 		ev = event->attr.config;
1765 		break;
1766 	default:
1767 		return -ENOENT;
1768 	}
1769 
1770 	event->hw.config_base = ev;
1771 	event->hw.idx = 0;
1772 
1773 	/*
1774 	 * If we are not running on a hypervisor, force the
1775 	 * exclude_hv bit to 0 so that we don't care what
1776 	 * the user set it to.
1777 	 */
1778 	if (!firmware_has_feature(FW_FEATURE_LPAR))
1779 		event->attr.exclude_hv = 0;
1780 
1781 	/*
1782 	 * If this is a per-task event, then we can use
1783 	 * PM_RUN_* events interchangeably with their non RUN_*
1784 	 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1785 	 * XXX we should check if the task is an idle task.
1786 	 */
1787 	flags = 0;
1788 	if (event->attach_state & PERF_ATTACH_TASK)
1789 		flags |= PPMU_ONLY_COUNT_RUN;
1790 
1791 	/*
1792 	 * If this machine has limited events, check whether this
1793 	 * event_id could go on a limited event.
1794 	 */
1795 	if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1796 		if (can_go_on_limited_pmc(event, ev, flags)) {
1797 			flags |= PPMU_LIMITED_PMC_OK;
1798 		} else if (ppmu->limited_pmc_event(ev)) {
1799 			/*
1800 			 * The requested event_id is on a limited PMC,
1801 			 * but we can't use a limited PMC; see if any
1802 			 * alternative goes on a normal PMC.
1803 			 */
1804 			ev = normal_pmc_alternative(ev, flags);
1805 			if (!ev)
1806 				return -EINVAL;
1807 		}
1808 	}
1809 
1810 	/* Extra checks for EBB */
1811 	err = ebb_event_check(event);
1812 	if (err)
1813 		return err;
1814 
1815 	/*
1816 	 * If this is in a group, check if it can go on with all the
1817 	 * other hardware events in the group.  We assume the event
1818 	 * hasn't been linked into its leader's sibling list at this point.
1819 	 */
1820 	n = 0;
1821 	if (event->group_leader != event) {
1822 		n = collect_events(event->group_leader, ppmu->n_counter - 1,
1823 				   ctrs, events, cflags);
1824 		if (n < 0)
1825 			return -EINVAL;
1826 	}
1827 	events[n] = ev;
1828 	ctrs[n] = event;
1829 	cflags[n] = flags;
1830 	if (check_excludes(ctrs, cflags, n, 1))
1831 		return -EINVAL;
1832 
1833 	cpuhw = &get_cpu_var(cpu_hw_events);
1834 	err = power_check_constraints(cpuhw, events, cflags, n + 1);
1835 
1836 	if (has_branch_stack(event)) {
1837 		cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1838 					event->attr.branch_sample_type);
1839 
1840 		if (cpuhw->bhrb_filter == -1) {
1841 			put_cpu_var(cpu_hw_events);
1842 			return -EOPNOTSUPP;
1843 		}
1844 	}
1845 
1846 	put_cpu_var(cpu_hw_events);
1847 	if (err)
1848 		return -EINVAL;
1849 
1850 	event->hw.config = events[n];
1851 	event->hw.event_base = cflags[n];
1852 	event->hw.last_period = event->hw.sample_period;
1853 	local64_set(&event->hw.period_left, event->hw.last_period);
1854 
1855 	/*
1856 	 * For EBB events we just context switch the PMC value, we don't do any
1857 	 * of the sample_period logic. We use hw.prev_count for this.
1858 	 */
1859 	if (is_ebb_event(event))
1860 		local64_set(&event->hw.prev_count, 0);
1861 
1862 	/*
1863 	 * See if we need to reserve the PMU.
1864 	 * If no events are currently in use, then we have to take a
1865 	 * mutex to ensure that we don't race with another task doing
1866 	 * reserve_pmc_hardware or release_pmc_hardware.
1867 	 */
1868 	err = 0;
1869 	if (!atomic_inc_not_zero(&num_events)) {
1870 		mutex_lock(&pmc_reserve_mutex);
1871 		if (atomic_read(&num_events) == 0 &&
1872 		    reserve_pmc_hardware(perf_event_interrupt))
1873 			err = -EBUSY;
1874 		else
1875 			atomic_inc(&num_events);
1876 		mutex_unlock(&pmc_reserve_mutex);
1877 	}
1878 	event->destroy = hw_perf_event_destroy;
1879 
1880 	return err;
1881 }
1882 
1883 static int power_pmu_event_idx(struct perf_event *event)
1884 {
1885 	return event->hw.idx;
1886 }
1887 
1888 ssize_t power_events_sysfs_show(struct device *dev,
1889 				struct device_attribute *attr, char *page)
1890 {
1891 	struct perf_pmu_events_attr *pmu_attr;
1892 
1893 	pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
1894 
1895 	return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
1896 }
1897 
1898 static struct pmu power_pmu = {
1899 	.pmu_enable	= power_pmu_enable,
1900 	.pmu_disable	= power_pmu_disable,
1901 	.event_init	= power_pmu_event_init,
1902 	.add		= power_pmu_add,
1903 	.del		= power_pmu_del,
1904 	.start		= power_pmu_start,
1905 	.stop		= power_pmu_stop,
1906 	.read		= power_pmu_read,
1907 	.start_txn	= power_pmu_start_txn,
1908 	.cancel_txn	= power_pmu_cancel_txn,
1909 	.commit_txn	= power_pmu_commit_txn,
1910 	.event_idx	= power_pmu_event_idx,
1911 	.sched_task	= power_pmu_sched_task,
1912 };
1913 
1914 /*
1915  * A counter has overflowed; update its count and record
1916  * things if requested.  Note that interrupts are hard-disabled
1917  * here so there is no possibility of being interrupted.
1918  */
1919 static void record_and_restart(struct perf_event *event, unsigned long val,
1920 			       struct pt_regs *regs)
1921 {
1922 	u64 period = event->hw.sample_period;
1923 	s64 prev, delta, left;
1924 	int record = 0;
1925 
1926 	if (event->hw.state & PERF_HES_STOPPED) {
1927 		write_pmc(event->hw.idx, 0);
1928 		return;
1929 	}
1930 
1931 	/* we don't have to worry about interrupts here */
1932 	prev = local64_read(&event->hw.prev_count);
1933 	delta = check_and_compute_delta(prev, val);
1934 	local64_add(delta, &event->count);
1935 
1936 	/*
1937 	 * See if the total period for this event has expired,
1938 	 * and update for the next period.
1939 	 */
1940 	val = 0;
1941 	left = local64_read(&event->hw.period_left) - delta;
1942 	if (delta == 0)
1943 		left++;
1944 	if (period) {
1945 		if (left <= 0) {
1946 			left += period;
1947 			if (left <= 0)
1948 				left = period;
1949 			record = siar_valid(regs);
1950 			event->hw.last_period = event->hw.sample_period;
1951 		}
1952 		if (left < 0x80000000LL)
1953 			val = 0x80000000LL - left;
1954 	}
1955 
1956 	write_pmc(event->hw.idx, val);
1957 	local64_set(&event->hw.prev_count, val);
1958 	local64_set(&event->hw.period_left, left);
1959 	perf_event_update_userpage(event);
1960 
1961 	/*
1962 	 * Finally record data if requested.
1963 	 */
1964 	if (record) {
1965 		struct perf_sample_data data;
1966 
1967 		perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
1968 
1969 		if (event->attr.sample_type & PERF_SAMPLE_ADDR)
1970 			perf_get_data_addr(regs, &data.addr);
1971 
1972 		if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
1973 			struct cpu_hw_events *cpuhw;
1974 			cpuhw = this_cpu_ptr(&cpu_hw_events);
1975 			power_pmu_bhrb_read(cpuhw);
1976 			data.br_stack = &cpuhw->bhrb_stack;
1977 		}
1978 
1979 		if (perf_event_overflow(event, &data, regs))
1980 			power_pmu_stop(event, 0);
1981 	}
1982 }
1983 
1984 /*
1985  * Called from generic code to get the misc flags (i.e. processor mode)
1986  * for an event_id.
1987  */
1988 unsigned long perf_misc_flags(struct pt_regs *regs)
1989 {
1990 	u32 flags = perf_get_misc_flags(regs);
1991 
1992 	if (flags)
1993 		return flags;
1994 	return user_mode(regs) ? PERF_RECORD_MISC_USER :
1995 		PERF_RECORD_MISC_KERNEL;
1996 }
1997 
1998 /*
1999  * Called from generic code to get the instruction pointer
2000  * for an event_id.
2001  */
2002 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2003 {
2004 	bool use_siar = regs_use_siar(regs);
2005 
2006 	if (use_siar && siar_valid(regs))
2007 		return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2008 	else if (use_siar)
2009 		return 0;		// no valid instruction pointer
2010 	else
2011 		return regs->nip;
2012 }
2013 
2014 static bool pmc_overflow_power7(unsigned long val)
2015 {
2016 	/*
2017 	 * Events on POWER7 can roll back if a speculative event doesn't
2018 	 * eventually complete. Unfortunately in some rare cases they will
2019 	 * raise a performance monitor exception. We need to catch this to
2020 	 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2021 	 * cycles from overflow.
2022 	 *
2023 	 * We only do this if the first pass fails to find any overflowing
2024 	 * PMCs because a user might set a period of less than 256 and we
2025 	 * don't want to mistakenly reset them.
2026 	 */
2027 	if ((0x80000000 - val) <= 256)
2028 		return true;
2029 
2030 	return false;
2031 }
2032 
2033 static bool pmc_overflow(unsigned long val)
2034 {
2035 	if ((int)val < 0)
2036 		return true;
2037 
2038 	return false;
2039 }
2040 
2041 /*
2042  * Performance monitor interrupt stuff
2043  */
2044 static void perf_event_interrupt(struct pt_regs *regs)
2045 {
2046 	int i, j;
2047 	struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2048 	struct perf_event *event;
2049 	unsigned long val[8];
2050 	int found, active;
2051 	int nmi;
2052 
2053 	if (cpuhw->n_limited)
2054 		freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2055 					mfspr(SPRN_PMC6));
2056 
2057 	perf_read_regs(regs);
2058 
2059 	nmi = perf_intr_is_nmi(regs);
2060 	if (nmi)
2061 		nmi_enter();
2062 	else
2063 		irq_enter();
2064 
2065 	/* Read all the PMCs since we'll need them a bunch of times */
2066 	for (i = 0; i < ppmu->n_counter; ++i)
2067 		val[i] = read_pmc(i + 1);
2068 
2069 	/* Try to find what caused the IRQ */
2070 	found = 0;
2071 	for (i = 0; i < ppmu->n_counter; ++i) {
2072 		if (!pmc_overflow(val[i]))
2073 			continue;
2074 		if (is_limited_pmc(i + 1))
2075 			continue; /* these won't generate IRQs */
2076 		/*
2077 		 * We've found one that's overflowed.  For active
2078 		 * counters we need to log this.  For inactive
2079 		 * counters, we need to reset it anyway
2080 		 */
2081 		found = 1;
2082 		active = 0;
2083 		for (j = 0; j < cpuhw->n_events; ++j) {
2084 			event = cpuhw->event[j];
2085 			if (event->hw.idx == (i + 1)) {
2086 				active = 1;
2087 				record_and_restart(event, val[i], regs);
2088 				break;
2089 			}
2090 		}
2091 		if (!active)
2092 			/* reset non active counters that have overflowed */
2093 			write_pmc(i + 1, 0);
2094 	}
2095 	if (!found && pvr_version_is(PVR_POWER7)) {
2096 		/* check active counters for special buggy p7 overflow */
2097 		for (i = 0; i < cpuhw->n_events; ++i) {
2098 			event = cpuhw->event[i];
2099 			if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2100 				continue;
2101 			if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2102 				/* event has overflowed in a buggy way*/
2103 				found = 1;
2104 				record_and_restart(event,
2105 						   val[event->hw.idx - 1],
2106 						   regs);
2107 			}
2108 		}
2109 	}
2110 	if (!found && !nmi && printk_ratelimit())
2111 		printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2112 
2113 	/*
2114 	 * Reset MMCR0 to its normal value.  This will set PMXE and
2115 	 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2116 	 * and thus allow interrupts to occur again.
2117 	 * XXX might want to use MSR.PM to keep the events frozen until
2118 	 * we get back out of this interrupt.
2119 	 */
2120 	write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2121 
2122 	if (nmi)
2123 		nmi_exit();
2124 	else
2125 		irq_exit();
2126 }
2127 
2128 static void power_pmu_setup(int cpu)
2129 {
2130 	struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2131 
2132 	if (!ppmu)
2133 		return;
2134 	memset(cpuhw, 0, sizeof(*cpuhw));
2135 	cpuhw->mmcr[0] = MMCR0_FC;
2136 }
2137 
2138 static int
2139 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
2140 {
2141 	unsigned int cpu = (long)hcpu;
2142 
2143 	switch (action & ~CPU_TASKS_FROZEN) {
2144 	case CPU_UP_PREPARE:
2145 		power_pmu_setup(cpu);
2146 		break;
2147 
2148 	default:
2149 		break;
2150 	}
2151 
2152 	return NOTIFY_OK;
2153 }
2154 
2155 int register_power_pmu(struct power_pmu *pmu)
2156 {
2157 	if (ppmu)
2158 		return -EBUSY;		/* something's already registered */
2159 
2160 	ppmu = pmu;
2161 	pr_info("%s performance monitor hardware support registered\n",
2162 		pmu->name);
2163 
2164 	power_pmu.attr_groups = ppmu->attr_groups;
2165 
2166 #ifdef MSR_HV
2167 	/*
2168 	 * Use FCHV to ignore kernel events if MSR.HV is set.
2169 	 */
2170 	if (mfmsr() & MSR_HV)
2171 		freeze_events_kernel = MMCR0_FCHV;
2172 #endif /* CONFIG_PPC64 */
2173 
2174 	perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2175 	perf_cpu_notifier(power_pmu_notifier);
2176 
2177 	return 0;
2178 }
2179