1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Performance event support - powerpc architecture code 4 * 5 * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 6 */ 7 #include <linux/kernel.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/perf_event.h> 11 #include <linux/percpu.h> 12 #include <linux/hardirq.h> 13 #include <linux/uaccess.h> 14 #include <asm/reg.h> 15 #include <asm/pmc.h> 16 #include <asm/machdep.h> 17 #include <asm/firmware.h> 18 #include <asm/ptrace.h> 19 #include <asm/code-patching.h> 20 21 #ifdef CONFIG_PPC64 22 #include "internal.h" 23 #endif 24 25 #define BHRB_MAX_ENTRIES 32 26 #define BHRB_TARGET 0x0000000000000002 27 #define BHRB_PREDICTION 0x0000000000000001 28 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 29 30 struct cpu_hw_events { 31 int n_events; 32 int n_percpu; 33 int disabled; 34 int n_added; 35 int n_limited; 36 u8 pmcs_enabled; 37 struct perf_event *event[MAX_HWEVENTS]; 38 u64 events[MAX_HWEVENTS]; 39 unsigned int flags[MAX_HWEVENTS]; 40 /* 41 * The order of the MMCR array is: 42 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 43 * - 32-bit, MMCR0, MMCR1, MMCR2 44 */ 45 unsigned long mmcr[4]; 46 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 47 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 48 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 49 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 50 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 51 52 unsigned int txn_flags; 53 int n_txn_start; 54 55 /* BHRB bits */ 56 u64 bhrb_filter; /* BHRB HW branch filter */ 57 unsigned int bhrb_users; 58 void *bhrb_context; 59 struct perf_branch_stack bhrb_stack; 60 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 61 u64 ic_init; 62 }; 63 64 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 65 66 static struct power_pmu *ppmu; 67 68 /* 69 * Normally, to ignore kernel events we set the FCS (freeze counters 70 * in supervisor mode) bit in MMCR0, but if the kernel runs with the 71 * hypervisor bit set in the MSR, or if we are running on a processor 72 * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 73 * then we need to use the FCHV bit to ignore kernel events. 74 */ 75 static unsigned int freeze_events_kernel = MMCR0_FCS; 76 77 /* 78 * 32-bit doesn't have MMCRA but does have an MMCR2, 79 * and a few other names are different. 80 */ 81 #ifdef CONFIG_PPC32 82 83 #define MMCR0_FCHV 0 84 #define MMCR0_PMCjCE MMCR0_PMCnCE 85 #define MMCR0_FC56 0 86 #define MMCR0_PMAO 0 87 #define MMCR0_EBE 0 88 #define MMCR0_BHRBA 0 89 #define MMCR0_PMCC 0 90 #define MMCR0_PMCC_U6 0 91 92 #define SPRN_MMCRA SPRN_MMCR2 93 #define MMCRA_SAMPLE_ENABLE 0 94 95 static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 96 { 97 return 0; 98 } 99 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 100 static inline u32 perf_get_misc_flags(struct pt_regs *regs) 101 { 102 return 0; 103 } 104 static inline void perf_read_regs(struct pt_regs *regs) 105 { 106 regs->result = 0; 107 } 108 static inline int perf_intr_is_nmi(struct pt_regs *regs) 109 { 110 return 0; 111 } 112 113 static inline int siar_valid(struct pt_regs *regs) 114 { 115 return 1; 116 } 117 118 static bool is_ebb_event(struct perf_event *event) { return false; } 119 static int ebb_event_check(struct perf_event *event) { return 0; } 120 static void ebb_event_add(struct perf_event *event) { } 121 static void ebb_switch_out(unsigned long mmcr0) { } 122 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 123 { 124 return cpuhw->mmcr[0]; 125 } 126 127 static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 128 static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 129 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 130 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 131 static void pmao_restore_workaround(bool ebb) { } 132 #endif /* CONFIG_PPC32 */ 133 134 bool is_sier_available(void) 135 { 136 if (ppmu->flags & PPMU_HAS_SIER) 137 return true; 138 139 return false; 140 } 141 142 static bool regs_use_siar(struct pt_regs *regs) 143 { 144 /* 145 * When we take a performance monitor exception the regs are setup 146 * using perf_read_regs() which overloads some fields, in particular 147 * regs->result to tell us whether to use SIAR. 148 * 149 * However if the regs are from another exception, eg. a syscall, then 150 * they have not been setup using perf_read_regs() and so regs->result 151 * is something random. 152 */ 153 return ((TRAP(regs) == 0xf00) && regs->result); 154 } 155 156 /* 157 * Things that are specific to 64-bit implementations. 158 */ 159 #ifdef CONFIG_PPC64 160 161 static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 162 { 163 unsigned long mmcra = regs->dsisr; 164 165 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 166 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 167 if (slot > 1) 168 return 4 * (slot - 1); 169 } 170 171 return 0; 172 } 173 174 /* 175 * The user wants a data address recorded. 176 * If we're not doing instruction sampling, give them the SDAR 177 * (sampled data address). If we are doing instruction sampling, then 178 * only give them the SDAR if it corresponds to the instruction 179 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 180 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 181 */ 182 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 183 { 184 unsigned long mmcra = regs->dsisr; 185 bool sdar_valid; 186 187 if (ppmu->flags & PPMU_HAS_SIER) 188 sdar_valid = regs->dar & SIER_SDAR_VALID; 189 else { 190 unsigned long sdsync; 191 192 if (ppmu->flags & PPMU_SIAR_VALID) 193 sdsync = POWER7P_MMCRA_SDAR_VALID; 194 else if (ppmu->flags & PPMU_ALT_SIPR) 195 sdsync = POWER6_MMCRA_SDSYNC; 196 else if (ppmu->flags & PPMU_NO_SIAR) 197 sdsync = MMCRA_SAMPLE_ENABLE; 198 else 199 sdsync = MMCRA_SDSYNC; 200 201 sdar_valid = mmcra & sdsync; 202 } 203 204 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 205 *addrp = mfspr(SPRN_SDAR); 206 207 if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) && 208 is_kernel_addr(mfspr(SPRN_SDAR))) 209 *addrp = 0; 210 } 211 212 static bool regs_sihv(struct pt_regs *regs) 213 { 214 unsigned long sihv = MMCRA_SIHV; 215 216 if (ppmu->flags & PPMU_HAS_SIER) 217 return !!(regs->dar & SIER_SIHV); 218 219 if (ppmu->flags & PPMU_ALT_SIPR) 220 sihv = POWER6_MMCRA_SIHV; 221 222 return !!(regs->dsisr & sihv); 223 } 224 225 static bool regs_sipr(struct pt_regs *regs) 226 { 227 unsigned long sipr = MMCRA_SIPR; 228 229 if (ppmu->flags & PPMU_HAS_SIER) 230 return !!(regs->dar & SIER_SIPR); 231 232 if (ppmu->flags & PPMU_ALT_SIPR) 233 sipr = POWER6_MMCRA_SIPR; 234 235 return !!(regs->dsisr & sipr); 236 } 237 238 static inline u32 perf_flags_from_msr(struct pt_regs *regs) 239 { 240 if (regs->msr & MSR_PR) 241 return PERF_RECORD_MISC_USER; 242 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 243 return PERF_RECORD_MISC_HYPERVISOR; 244 return PERF_RECORD_MISC_KERNEL; 245 } 246 247 static inline u32 perf_get_misc_flags(struct pt_regs *regs) 248 { 249 bool use_siar = regs_use_siar(regs); 250 251 if (!use_siar) 252 return perf_flags_from_msr(regs); 253 254 /* 255 * If we don't have flags in MMCRA, rather than using 256 * the MSR, we intuit the flags from the address in 257 * SIAR which should give slightly more reliable 258 * results 259 */ 260 if (ppmu->flags & PPMU_NO_SIPR) { 261 unsigned long siar = mfspr(SPRN_SIAR); 262 if (is_kernel_addr(siar)) 263 return PERF_RECORD_MISC_KERNEL; 264 return PERF_RECORD_MISC_USER; 265 } 266 267 /* PR has priority over HV, so order below is important */ 268 if (regs_sipr(regs)) 269 return PERF_RECORD_MISC_USER; 270 271 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 272 return PERF_RECORD_MISC_HYPERVISOR; 273 274 return PERF_RECORD_MISC_KERNEL; 275 } 276 277 /* 278 * Overload regs->dsisr to store MMCRA so we only need to read it once 279 * on each interrupt. 280 * Overload regs->dar to store SIER if we have it. 281 * Overload regs->result to specify whether we should use the MSR (result 282 * is zero) or the SIAR (result is non zero). 283 */ 284 static inline void perf_read_regs(struct pt_regs *regs) 285 { 286 unsigned long mmcra = mfspr(SPRN_MMCRA); 287 int marked = mmcra & MMCRA_SAMPLE_ENABLE; 288 int use_siar; 289 290 regs->dsisr = mmcra; 291 292 if (ppmu->flags & PPMU_HAS_SIER) 293 regs->dar = mfspr(SPRN_SIER); 294 295 /* 296 * If this isn't a PMU exception (eg a software event) the SIAR is 297 * not valid. Use pt_regs. 298 * 299 * If it is a marked event use the SIAR. 300 * 301 * If the PMU doesn't update the SIAR for non marked events use 302 * pt_regs. 303 * 304 * If the PMU has HV/PR flags then check to see if they 305 * place the exception in userspace. If so, use pt_regs. In 306 * continuous sampling mode the SIAR and the PMU exception are 307 * not synchronised, so they may be many instructions apart. 308 * This can result in confusing backtraces. We still want 309 * hypervisor samples as well as samples in the kernel with 310 * interrupts off hence the userspace check. 311 */ 312 if (TRAP(regs) != 0xf00) 313 use_siar = 0; 314 else if ((ppmu->flags & PPMU_NO_SIAR)) 315 use_siar = 0; 316 else if (marked) 317 use_siar = 1; 318 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 319 use_siar = 0; 320 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 321 use_siar = 0; 322 else 323 use_siar = 1; 324 325 regs->result = use_siar; 326 } 327 328 /* 329 * If interrupts were soft-disabled when a PMU interrupt occurs, treat 330 * it as an NMI. 331 */ 332 static inline int perf_intr_is_nmi(struct pt_regs *regs) 333 { 334 return (regs->softe & IRQS_DISABLED); 335 } 336 337 /* 338 * On processors like P7+ that have the SIAR-Valid bit, marked instructions 339 * must be sampled only if the SIAR-valid bit is set. 340 * 341 * For unmarked instructions and for processors that don't have the SIAR-Valid 342 * bit, assume that SIAR is valid. 343 */ 344 static inline int siar_valid(struct pt_regs *regs) 345 { 346 unsigned long mmcra = regs->dsisr; 347 int marked = mmcra & MMCRA_SAMPLE_ENABLE; 348 349 if (marked) { 350 if (ppmu->flags & PPMU_HAS_SIER) 351 return regs->dar & SIER_SIAR_VALID; 352 353 if (ppmu->flags & PPMU_SIAR_VALID) 354 return mmcra & POWER7P_MMCRA_SIAR_VALID; 355 } 356 357 return 1; 358 } 359 360 361 /* Reset all possible BHRB entries */ 362 static void power_pmu_bhrb_reset(void) 363 { 364 asm volatile(PPC_CLRBHRB); 365 } 366 367 static void power_pmu_bhrb_enable(struct perf_event *event) 368 { 369 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 370 371 if (!ppmu->bhrb_nr) 372 return; 373 374 /* Clear BHRB if we changed task context to avoid data leaks */ 375 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 376 power_pmu_bhrb_reset(); 377 cpuhw->bhrb_context = event->ctx; 378 } 379 cpuhw->bhrb_users++; 380 perf_sched_cb_inc(event->ctx->pmu); 381 } 382 383 static void power_pmu_bhrb_disable(struct perf_event *event) 384 { 385 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 386 387 if (!ppmu->bhrb_nr) 388 return; 389 390 WARN_ON_ONCE(!cpuhw->bhrb_users); 391 cpuhw->bhrb_users--; 392 perf_sched_cb_dec(event->ctx->pmu); 393 394 if (!cpuhw->disabled && !cpuhw->bhrb_users) { 395 /* BHRB cannot be turned off when other 396 * events are active on the PMU. 397 */ 398 399 /* avoid stale pointer */ 400 cpuhw->bhrb_context = NULL; 401 } 402 } 403 404 /* Called from ctxsw to prevent one process's branch entries to 405 * mingle with the other process's entries during context switch. 406 */ 407 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 408 { 409 if (!ppmu->bhrb_nr) 410 return; 411 412 if (sched_in) 413 power_pmu_bhrb_reset(); 414 } 415 /* Calculate the to address for a branch */ 416 static __u64 power_pmu_bhrb_to(u64 addr) 417 { 418 unsigned int instr; 419 int ret; 420 __u64 target; 421 422 if (is_kernel_addr(addr)) { 423 if (probe_kernel_read(&instr, (void *)addr, sizeof(instr))) 424 return 0; 425 426 return branch_target(&instr); 427 } 428 429 /* Userspace: need copy instruction here then translate it */ 430 pagefault_disable(); 431 ret = __get_user_inatomic(instr, (unsigned int __user *)addr); 432 if (ret) { 433 pagefault_enable(); 434 return 0; 435 } 436 pagefault_enable(); 437 438 target = branch_target(&instr); 439 if ((!target) || (instr & BRANCH_ABSOLUTE)) 440 return target; 441 442 /* Translate relative branch target from kernel to user address */ 443 return target - (unsigned long)&instr + addr; 444 } 445 446 /* Processing BHRB entries */ 447 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 448 { 449 u64 val; 450 u64 addr; 451 int r_index, u_index, pred; 452 453 r_index = 0; 454 u_index = 0; 455 while (r_index < ppmu->bhrb_nr) { 456 /* Assembly read function */ 457 val = read_bhrb(r_index++); 458 if (!val) 459 /* Terminal marker: End of valid BHRB entries */ 460 break; 461 else { 462 addr = val & BHRB_EA; 463 pred = val & BHRB_PREDICTION; 464 465 if (!addr) 466 /* invalid entry */ 467 continue; 468 469 /* 470 * BHRB rolling buffer could very much contain the kernel 471 * addresses at this point. Check the privileges before 472 * exporting it to userspace (avoid exposure of regions 473 * where we could have speculative execution) 474 */ 475 if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) && 476 is_kernel_addr(addr)) 477 continue; 478 479 /* Branches are read most recent first (ie. mfbhrb 0 is 480 * the most recent branch). 481 * There are two types of valid entries: 482 * 1) a target entry which is the to address of a 483 * computed goto like a blr,bctr,btar. The next 484 * entry read from the bhrb will be branch 485 * corresponding to this target (ie. the actual 486 * blr/bctr/btar instruction). 487 * 2) a from address which is an actual branch. If a 488 * target entry proceeds this, then this is the 489 * matching branch for that target. If this is not 490 * following a target entry, then this is a branch 491 * where the target is given as an immediate field 492 * in the instruction (ie. an i or b form branch). 493 * In this case we need to read the instruction from 494 * memory to determine the target/to address. 495 */ 496 497 if (val & BHRB_TARGET) { 498 /* Target branches use two entries 499 * (ie. computed gotos/XL form) 500 */ 501 cpuhw->bhrb_entries[u_index].to = addr; 502 cpuhw->bhrb_entries[u_index].mispred = pred; 503 cpuhw->bhrb_entries[u_index].predicted = ~pred; 504 505 /* Get from address in next entry */ 506 val = read_bhrb(r_index++); 507 addr = val & BHRB_EA; 508 if (val & BHRB_TARGET) { 509 /* Shouldn't have two targets in a 510 row.. Reset index and try again */ 511 r_index--; 512 addr = 0; 513 } 514 cpuhw->bhrb_entries[u_index].from = addr; 515 } else { 516 /* Branches to immediate field 517 (ie I or B form) */ 518 cpuhw->bhrb_entries[u_index].from = addr; 519 cpuhw->bhrb_entries[u_index].to = 520 power_pmu_bhrb_to(addr); 521 cpuhw->bhrb_entries[u_index].mispred = pred; 522 cpuhw->bhrb_entries[u_index].predicted = ~pred; 523 } 524 u_index++; 525 526 } 527 } 528 cpuhw->bhrb_stack.nr = u_index; 529 return; 530 } 531 532 static bool is_ebb_event(struct perf_event *event) 533 { 534 /* 535 * This could be a per-PMU callback, but we'd rather avoid the cost. We 536 * check that the PMU supports EBB, meaning those that don't can still 537 * use bit 63 of the event code for something else if they wish. 538 */ 539 return (ppmu->flags & PPMU_ARCH_207S) && 540 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 541 } 542 543 static int ebb_event_check(struct perf_event *event) 544 { 545 struct perf_event *leader = event->group_leader; 546 547 /* Event and group leader must agree on EBB */ 548 if (is_ebb_event(leader) != is_ebb_event(event)) 549 return -EINVAL; 550 551 if (is_ebb_event(event)) { 552 if (!(event->attach_state & PERF_ATTACH_TASK)) 553 return -EINVAL; 554 555 if (!leader->attr.pinned || !leader->attr.exclusive) 556 return -EINVAL; 557 558 if (event->attr.freq || 559 event->attr.inherit || 560 event->attr.sample_type || 561 event->attr.sample_period || 562 event->attr.enable_on_exec) 563 return -EINVAL; 564 } 565 566 return 0; 567 } 568 569 static void ebb_event_add(struct perf_event *event) 570 { 571 if (!is_ebb_event(event) || current->thread.used_ebb) 572 return; 573 574 /* 575 * IFF this is the first time we've added an EBB event, set 576 * PMXE in the user MMCR0 so we can detect when it's cleared by 577 * userspace. We need this so that we can context switch while 578 * userspace is in the EBB handler (where PMXE is 0). 579 */ 580 current->thread.used_ebb = 1; 581 current->thread.mmcr0 |= MMCR0_PMXE; 582 } 583 584 static void ebb_switch_out(unsigned long mmcr0) 585 { 586 if (!(mmcr0 & MMCR0_EBE)) 587 return; 588 589 current->thread.siar = mfspr(SPRN_SIAR); 590 current->thread.sier = mfspr(SPRN_SIER); 591 current->thread.sdar = mfspr(SPRN_SDAR); 592 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 593 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 594 } 595 596 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 597 { 598 unsigned long mmcr0 = cpuhw->mmcr[0]; 599 600 if (!ebb) 601 goto out; 602 603 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 604 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 605 606 /* 607 * Add any bits from the user MMCR0, FC or PMAO. This is compatible 608 * with pmao_restore_workaround() because we may add PMAO but we never 609 * clear it here. 610 */ 611 mmcr0 |= current->thread.mmcr0; 612 613 /* 614 * Be careful not to set PMXE if userspace had it cleared. This is also 615 * compatible with pmao_restore_workaround() because it has already 616 * cleared PMXE and we leave PMAO alone. 617 */ 618 if (!(current->thread.mmcr0 & MMCR0_PMXE)) 619 mmcr0 &= ~MMCR0_PMXE; 620 621 mtspr(SPRN_SIAR, current->thread.siar); 622 mtspr(SPRN_SIER, current->thread.sier); 623 mtspr(SPRN_SDAR, current->thread.sdar); 624 625 /* 626 * Merge the kernel & user values of MMCR2. The semantics we implement 627 * are that the user MMCR2 can set bits, ie. cause counters to freeze, 628 * but not clear bits. If a task wants to be able to clear bits, ie. 629 * unfreeze counters, it should not set exclude_xxx in its events and 630 * instead manage the MMCR2 entirely by itself. 631 */ 632 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); 633 out: 634 return mmcr0; 635 } 636 637 static void pmao_restore_workaround(bool ebb) 638 { 639 unsigned pmcs[6]; 640 641 if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 642 return; 643 644 /* 645 * On POWER8E there is a hardware defect which affects the PMU context 646 * switch logic, ie. power_pmu_disable/enable(). 647 * 648 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 649 * by the hardware. Sometime later the actual PMU exception is 650 * delivered. 651 * 652 * If we context switch, or simply disable/enable, the PMU prior to the 653 * exception arriving, the exception will be lost when we clear PMAO. 654 * 655 * When we reenable the PMU, we will write the saved MMCR0 with PMAO 656 * set, and this _should_ generate an exception. However because of the 657 * defect no exception is generated when we write PMAO, and we get 658 * stuck with no counters counting but no exception delivered. 659 * 660 * The workaround is to detect this case and tweak the hardware to 661 * create another pending PMU exception. 662 * 663 * We do that by setting up PMC6 (cycles) for an imminent overflow and 664 * enabling the PMU. That causes a new exception to be generated in the 665 * chip, but we don't take it yet because we have interrupts hard 666 * disabled. We then write back the PMU state as we want it to be seen 667 * by the exception handler. When we reenable interrupts the exception 668 * handler will be called and see the correct state. 669 * 670 * The logic is the same for EBB, except that the exception is gated by 671 * us having interrupts hard disabled as well as the fact that we are 672 * not in userspace. The exception is finally delivered when we return 673 * to userspace. 674 */ 675 676 /* Only if PMAO is set and PMAO_SYNC is clear */ 677 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 678 return; 679 680 /* If we're doing EBB, only if BESCR[GE] is set */ 681 if (ebb && !(current->thread.bescr & BESCR_GE)) 682 return; 683 684 /* 685 * We are already soft-disabled in power_pmu_enable(). We need to hard 686 * disable to actually prevent the PMU exception from firing. 687 */ 688 hard_irq_disable(); 689 690 /* 691 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 692 * Using read/write_pmc() in a for loop adds 12 function calls and 693 * almost doubles our code size. 694 */ 695 pmcs[0] = mfspr(SPRN_PMC1); 696 pmcs[1] = mfspr(SPRN_PMC2); 697 pmcs[2] = mfspr(SPRN_PMC3); 698 pmcs[3] = mfspr(SPRN_PMC4); 699 pmcs[4] = mfspr(SPRN_PMC5); 700 pmcs[5] = mfspr(SPRN_PMC6); 701 702 /* Ensure all freeze bits are unset */ 703 mtspr(SPRN_MMCR2, 0); 704 705 /* Set up PMC6 to overflow in one cycle */ 706 mtspr(SPRN_PMC6, 0x7FFFFFFE); 707 708 /* Enable exceptions and unfreeze PMC6 */ 709 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 710 711 /* Now we need to refreeze and restore the PMCs */ 712 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 713 714 mtspr(SPRN_PMC1, pmcs[0]); 715 mtspr(SPRN_PMC2, pmcs[1]); 716 mtspr(SPRN_PMC3, pmcs[2]); 717 mtspr(SPRN_PMC4, pmcs[3]); 718 mtspr(SPRN_PMC5, pmcs[4]); 719 mtspr(SPRN_PMC6, pmcs[5]); 720 } 721 722 #endif /* CONFIG_PPC64 */ 723 724 static void perf_event_interrupt(struct pt_regs *regs); 725 726 /* 727 * Read one performance monitor counter (PMC). 728 */ 729 static unsigned long read_pmc(int idx) 730 { 731 unsigned long val; 732 733 switch (idx) { 734 case 1: 735 val = mfspr(SPRN_PMC1); 736 break; 737 case 2: 738 val = mfspr(SPRN_PMC2); 739 break; 740 case 3: 741 val = mfspr(SPRN_PMC3); 742 break; 743 case 4: 744 val = mfspr(SPRN_PMC4); 745 break; 746 case 5: 747 val = mfspr(SPRN_PMC5); 748 break; 749 case 6: 750 val = mfspr(SPRN_PMC6); 751 break; 752 #ifdef CONFIG_PPC64 753 case 7: 754 val = mfspr(SPRN_PMC7); 755 break; 756 case 8: 757 val = mfspr(SPRN_PMC8); 758 break; 759 #endif /* CONFIG_PPC64 */ 760 default: 761 printk(KERN_ERR "oops trying to read PMC%d\n", idx); 762 val = 0; 763 } 764 return val; 765 } 766 767 /* 768 * Write one PMC. 769 */ 770 static void write_pmc(int idx, unsigned long val) 771 { 772 switch (idx) { 773 case 1: 774 mtspr(SPRN_PMC1, val); 775 break; 776 case 2: 777 mtspr(SPRN_PMC2, val); 778 break; 779 case 3: 780 mtspr(SPRN_PMC3, val); 781 break; 782 case 4: 783 mtspr(SPRN_PMC4, val); 784 break; 785 case 5: 786 mtspr(SPRN_PMC5, val); 787 break; 788 case 6: 789 mtspr(SPRN_PMC6, val); 790 break; 791 #ifdef CONFIG_PPC64 792 case 7: 793 mtspr(SPRN_PMC7, val); 794 break; 795 case 8: 796 mtspr(SPRN_PMC8, val); 797 break; 798 #endif /* CONFIG_PPC64 */ 799 default: 800 printk(KERN_ERR "oops trying to write PMC%d\n", idx); 801 } 802 } 803 804 /* Called from sysrq_handle_showregs() */ 805 void perf_event_print_debug(void) 806 { 807 unsigned long sdar, sier, flags; 808 u32 pmcs[MAX_HWEVENTS]; 809 int i; 810 811 if (!ppmu) { 812 pr_info("Performance monitor hardware not registered.\n"); 813 return; 814 } 815 816 if (!ppmu->n_counter) 817 return; 818 819 local_irq_save(flags); 820 821 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 822 smp_processor_id(), ppmu->name, ppmu->n_counter); 823 824 for (i = 0; i < ppmu->n_counter; i++) 825 pmcs[i] = read_pmc(i + 1); 826 827 for (; i < MAX_HWEVENTS; i++) 828 pmcs[i] = 0xdeadbeef; 829 830 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 831 pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 832 833 if (ppmu->n_counter > 4) 834 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 835 pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 836 837 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 838 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 839 840 sdar = sier = 0; 841 #ifdef CONFIG_PPC64 842 sdar = mfspr(SPRN_SDAR); 843 844 if (ppmu->flags & PPMU_HAS_SIER) 845 sier = mfspr(SPRN_SIER); 846 847 if (ppmu->flags & PPMU_ARCH_207S) { 848 pr_info("MMCR2: %016lx EBBHR: %016lx\n", 849 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 850 pr_info("EBBRR: %016lx BESCR: %016lx\n", 851 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 852 } 853 #endif 854 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 855 mfspr(SPRN_SIAR), sdar, sier); 856 857 local_irq_restore(flags); 858 } 859 860 /* 861 * Check if a set of events can all go on the PMU at once. 862 * If they can't, this will look at alternative codes for the events 863 * and see if any combination of alternative codes is feasible. 864 * The feasible set is returned in event_id[]. 865 */ 866 static int power_check_constraints(struct cpu_hw_events *cpuhw, 867 u64 event_id[], unsigned int cflags[], 868 int n_ev) 869 { 870 unsigned long mask, value, nv; 871 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 872 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 873 int i, j; 874 unsigned long addf = ppmu->add_fields; 875 unsigned long tadd = ppmu->test_adder; 876 unsigned long grp_mask = ppmu->group_constraint_mask; 877 unsigned long grp_val = ppmu->group_constraint_val; 878 879 if (n_ev > ppmu->n_counter) 880 return -1; 881 882 /* First see if the events will go on as-is */ 883 for (i = 0; i < n_ev; ++i) { 884 if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 885 && !ppmu->limited_pmc_event(event_id[i])) { 886 ppmu->get_alternatives(event_id[i], cflags[i], 887 cpuhw->alternatives[i]); 888 event_id[i] = cpuhw->alternatives[i][0]; 889 } 890 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 891 &cpuhw->avalues[i][0])) 892 return -1; 893 } 894 value = mask = 0; 895 for (i = 0; i < n_ev; ++i) { 896 nv = (value | cpuhw->avalues[i][0]) + 897 (value & cpuhw->avalues[i][0] & addf); 898 899 if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0) 900 break; 901 902 if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0]) 903 & (~grp_mask)) != 0) 904 break; 905 906 value = nv; 907 mask |= cpuhw->amasks[i][0]; 908 } 909 if (i == n_ev) { 910 if ((value & mask & grp_mask) != (mask & grp_val)) 911 return -1; 912 else 913 return 0; /* all OK */ 914 } 915 916 /* doesn't work, gather alternatives... */ 917 if (!ppmu->get_alternatives) 918 return -1; 919 for (i = 0; i < n_ev; ++i) { 920 choice[i] = 0; 921 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 922 cpuhw->alternatives[i]); 923 for (j = 1; j < n_alt[i]; ++j) 924 ppmu->get_constraint(cpuhw->alternatives[i][j], 925 &cpuhw->amasks[i][j], 926 &cpuhw->avalues[i][j]); 927 } 928 929 /* enumerate all possibilities and see if any will work */ 930 i = 0; 931 j = -1; 932 value = mask = nv = 0; 933 while (i < n_ev) { 934 if (j >= 0) { 935 /* we're backtracking, restore context */ 936 value = svalues[i]; 937 mask = smasks[i]; 938 j = choice[i]; 939 } 940 /* 941 * See if any alternative k for event_id i, 942 * where k > j, will satisfy the constraints. 943 */ 944 while (++j < n_alt[i]) { 945 nv = (value | cpuhw->avalues[i][j]) + 946 (value & cpuhw->avalues[i][j] & addf); 947 if ((((nv + tadd) ^ value) & mask) == 0 && 948 (((nv + tadd) ^ cpuhw->avalues[i][j]) 949 & cpuhw->amasks[i][j]) == 0) 950 break; 951 } 952 if (j >= n_alt[i]) { 953 /* 954 * No feasible alternative, backtrack 955 * to event_id i-1 and continue enumerating its 956 * alternatives from where we got up to. 957 */ 958 if (--i < 0) 959 return -1; 960 } else { 961 /* 962 * Found a feasible alternative for event_id i, 963 * remember where we got up to with this event_id, 964 * go on to the next event_id, and start with 965 * the first alternative for it. 966 */ 967 choice[i] = j; 968 svalues[i] = value; 969 smasks[i] = mask; 970 value = nv; 971 mask |= cpuhw->amasks[i][j]; 972 ++i; 973 j = -1; 974 } 975 } 976 977 /* OK, we have a feasible combination, tell the caller the solution */ 978 for (i = 0; i < n_ev; ++i) 979 event_id[i] = cpuhw->alternatives[i][choice[i]]; 980 return 0; 981 } 982 983 /* 984 * Check if newly-added events have consistent settings for 985 * exclude_{user,kernel,hv} with each other and any previously 986 * added events. 987 */ 988 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 989 int n_prev, int n_new) 990 { 991 int eu = 0, ek = 0, eh = 0; 992 int i, n, first; 993 struct perf_event *event; 994 995 /* 996 * If the PMU we're on supports per event exclude settings then we 997 * don't need to do any of this logic. NB. This assumes no PMU has both 998 * per event exclude and limited PMCs. 999 */ 1000 if (ppmu->flags & PPMU_ARCH_207S) 1001 return 0; 1002 1003 n = n_prev + n_new; 1004 if (n <= 1) 1005 return 0; 1006 1007 first = 1; 1008 for (i = 0; i < n; ++i) { 1009 if (cflags[i] & PPMU_LIMITED_PMC_OK) { 1010 cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 1011 continue; 1012 } 1013 event = ctrs[i]; 1014 if (first) { 1015 eu = event->attr.exclude_user; 1016 ek = event->attr.exclude_kernel; 1017 eh = event->attr.exclude_hv; 1018 first = 0; 1019 } else if (event->attr.exclude_user != eu || 1020 event->attr.exclude_kernel != ek || 1021 event->attr.exclude_hv != eh) { 1022 return -EAGAIN; 1023 } 1024 } 1025 1026 if (eu || ek || eh) 1027 for (i = 0; i < n; ++i) 1028 if (cflags[i] & PPMU_LIMITED_PMC_OK) 1029 cflags[i] |= PPMU_LIMITED_PMC_REQD; 1030 1031 return 0; 1032 } 1033 1034 static u64 check_and_compute_delta(u64 prev, u64 val) 1035 { 1036 u64 delta = (val - prev) & 0xfffffffful; 1037 1038 /* 1039 * POWER7 can roll back counter values, if the new value is smaller 1040 * than the previous value it will cause the delta and the counter to 1041 * have bogus values unless we rolled a counter over. If a coutner is 1042 * rolled back, it will be smaller, but within 256, which is the maximum 1043 * number of events to rollback at once. If we detect a rollback 1044 * return 0. This can lead to a small lack of precision in the 1045 * counters. 1046 */ 1047 if (prev > val && (prev - val) < 256) 1048 delta = 0; 1049 1050 return delta; 1051 } 1052 1053 static void power_pmu_read(struct perf_event *event) 1054 { 1055 s64 val, delta, prev; 1056 1057 if (event->hw.state & PERF_HES_STOPPED) 1058 return; 1059 1060 if (!event->hw.idx) 1061 return; 1062 1063 if (is_ebb_event(event)) { 1064 val = read_pmc(event->hw.idx); 1065 local64_set(&event->hw.prev_count, val); 1066 return; 1067 } 1068 1069 /* 1070 * Performance monitor interrupts come even when interrupts 1071 * are soft-disabled, as long as interrupts are hard-enabled. 1072 * Therefore we treat them like NMIs. 1073 */ 1074 do { 1075 prev = local64_read(&event->hw.prev_count); 1076 barrier(); 1077 val = read_pmc(event->hw.idx); 1078 delta = check_and_compute_delta(prev, val); 1079 if (!delta) 1080 return; 1081 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1082 1083 local64_add(delta, &event->count); 1084 1085 /* 1086 * A number of places program the PMC with (0x80000000 - period_left). 1087 * We never want period_left to be less than 1 because we will program 1088 * the PMC with a value >= 0x800000000 and an edge detected PMC will 1089 * roll around to 0 before taking an exception. We have seen this 1090 * on POWER8. 1091 * 1092 * To fix this, clamp the minimum value of period_left to 1. 1093 */ 1094 do { 1095 prev = local64_read(&event->hw.period_left); 1096 val = prev - delta; 1097 if (val < 1) 1098 val = 1; 1099 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1100 } 1101 1102 /* 1103 * On some machines, PMC5 and PMC6 can't be written, don't respect 1104 * the freeze conditions, and don't generate interrupts. This tells 1105 * us if `event' is using such a PMC. 1106 */ 1107 static int is_limited_pmc(int pmcnum) 1108 { 1109 return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1110 && (pmcnum == 5 || pmcnum == 6); 1111 } 1112 1113 static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1114 unsigned long pmc5, unsigned long pmc6) 1115 { 1116 struct perf_event *event; 1117 u64 val, prev, delta; 1118 int i; 1119 1120 for (i = 0; i < cpuhw->n_limited; ++i) { 1121 event = cpuhw->limited_counter[i]; 1122 if (!event->hw.idx) 1123 continue; 1124 val = (event->hw.idx == 5) ? pmc5 : pmc6; 1125 prev = local64_read(&event->hw.prev_count); 1126 event->hw.idx = 0; 1127 delta = check_and_compute_delta(prev, val); 1128 if (delta) 1129 local64_add(delta, &event->count); 1130 } 1131 } 1132 1133 static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1134 unsigned long pmc5, unsigned long pmc6) 1135 { 1136 struct perf_event *event; 1137 u64 val, prev; 1138 int i; 1139 1140 for (i = 0; i < cpuhw->n_limited; ++i) { 1141 event = cpuhw->limited_counter[i]; 1142 event->hw.idx = cpuhw->limited_hwidx[i]; 1143 val = (event->hw.idx == 5) ? pmc5 : pmc6; 1144 prev = local64_read(&event->hw.prev_count); 1145 if (check_and_compute_delta(prev, val)) 1146 local64_set(&event->hw.prev_count, val); 1147 perf_event_update_userpage(event); 1148 } 1149 } 1150 1151 /* 1152 * Since limited events don't respect the freeze conditions, we 1153 * have to read them immediately after freezing or unfreezing the 1154 * other events. We try to keep the values from the limited 1155 * events as consistent as possible by keeping the delay (in 1156 * cycles and instructions) between freezing/unfreezing and reading 1157 * the limited events as small and consistent as possible. 1158 * Therefore, if any limited events are in use, we read them 1159 * both, and always in the same order, to minimize variability, 1160 * and do it inside the same asm that writes MMCR0. 1161 */ 1162 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1163 { 1164 unsigned long pmc5, pmc6; 1165 1166 if (!cpuhw->n_limited) { 1167 mtspr(SPRN_MMCR0, mmcr0); 1168 return; 1169 } 1170 1171 /* 1172 * Write MMCR0, then read PMC5 and PMC6 immediately. 1173 * To ensure we don't get a performance monitor interrupt 1174 * between writing MMCR0 and freezing/thawing the limited 1175 * events, we first write MMCR0 with the event overflow 1176 * interrupt enable bits turned off. 1177 */ 1178 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1179 : "=&r" (pmc5), "=&r" (pmc6) 1180 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1181 "i" (SPRN_MMCR0), 1182 "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1183 1184 if (mmcr0 & MMCR0_FC) 1185 freeze_limited_counters(cpuhw, pmc5, pmc6); 1186 else 1187 thaw_limited_counters(cpuhw, pmc5, pmc6); 1188 1189 /* 1190 * Write the full MMCR0 including the event overflow interrupt 1191 * enable bits, if necessary. 1192 */ 1193 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1194 mtspr(SPRN_MMCR0, mmcr0); 1195 } 1196 1197 /* 1198 * Disable all events to prevent PMU interrupts and to allow 1199 * events to be added or removed. 1200 */ 1201 static void power_pmu_disable(struct pmu *pmu) 1202 { 1203 struct cpu_hw_events *cpuhw; 1204 unsigned long flags, mmcr0, val; 1205 1206 if (!ppmu) 1207 return; 1208 local_irq_save(flags); 1209 cpuhw = this_cpu_ptr(&cpu_hw_events); 1210 1211 if (!cpuhw->disabled) { 1212 /* 1213 * Check if we ever enabled the PMU on this cpu. 1214 */ 1215 if (!cpuhw->pmcs_enabled) { 1216 ppc_enable_pmcs(); 1217 cpuhw->pmcs_enabled = 1; 1218 } 1219 1220 /* 1221 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1222 */ 1223 val = mmcr0 = mfspr(SPRN_MMCR0); 1224 val |= MMCR0_FC; 1225 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 1226 MMCR0_FC56); 1227 1228 /* 1229 * The barrier is to make sure the mtspr has been 1230 * executed and the PMU has frozen the events etc. 1231 * before we return. 1232 */ 1233 write_mmcr0(cpuhw, val); 1234 mb(); 1235 isync(); 1236 1237 /* 1238 * Disable instruction sampling if it was enabled 1239 */ 1240 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1241 mtspr(SPRN_MMCRA, 1242 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1243 mb(); 1244 isync(); 1245 } 1246 1247 cpuhw->disabled = 1; 1248 cpuhw->n_added = 0; 1249 1250 ebb_switch_out(mmcr0); 1251 1252 #ifdef CONFIG_PPC64 1253 /* 1254 * These are readable by userspace, may contain kernel 1255 * addresses and are not switched by context switch, so clear 1256 * them now to avoid leaking anything to userspace in general 1257 * including to another process. 1258 */ 1259 if (ppmu->flags & PPMU_ARCH_207S) { 1260 mtspr(SPRN_SDAR, 0); 1261 mtspr(SPRN_SIAR, 0); 1262 } 1263 #endif 1264 } 1265 1266 local_irq_restore(flags); 1267 } 1268 1269 /* 1270 * Re-enable all events if disable == 0. 1271 * If we were previously disabled and events were added, then 1272 * put the new config on the PMU. 1273 */ 1274 static void power_pmu_enable(struct pmu *pmu) 1275 { 1276 struct perf_event *event; 1277 struct cpu_hw_events *cpuhw; 1278 unsigned long flags; 1279 long i; 1280 unsigned long val, mmcr0; 1281 s64 left; 1282 unsigned int hwc_index[MAX_HWEVENTS]; 1283 int n_lim; 1284 int idx; 1285 bool ebb; 1286 1287 if (!ppmu) 1288 return; 1289 local_irq_save(flags); 1290 1291 cpuhw = this_cpu_ptr(&cpu_hw_events); 1292 if (!cpuhw->disabled) 1293 goto out; 1294 1295 if (cpuhw->n_events == 0) { 1296 ppc_set_pmu_inuse(0); 1297 goto out; 1298 } 1299 1300 cpuhw->disabled = 0; 1301 1302 /* 1303 * EBB requires an exclusive group and all events must have the EBB 1304 * flag set, or not set, so we can just check a single event. Also we 1305 * know we have at least one event. 1306 */ 1307 ebb = is_ebb_event(cpuhw->event[0]); 1308 1309 /* 1310 * If we didn't change anything, or only removed events, 1311 * no need to recalculate MMCR* settings and reset the PMCs. 1312 * Just reenable the PMU with the current MMCR* settings 1313 * (possibly updated for removal of events). 1314 */ 1315 if (!cpuhw->n_added) { 1316 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1317 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1318 goto out_enable; 1319 } 1320 1321 /* 1322 * Clear all MMCR settings and recompute them for the new set of events. 1323 */ 1324 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 1325 1326 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 1327 cpuhw->mmcr, cpuhw->event)) { 1328 /* shouldn't ever get here */ 1329 printk(KERN_ERR "oops compute_mmcr failed\n"); 1330 goto out; 1331 } 1332 1333 if (!(ppmu->flags & PPMU_ARCH_207S)) { 1334 /* 1335 * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 1336 * bits for the first event. We have already checked that all 1337 * events have the same value for these bits as the first event. 1338 */ 1339 event = cpuhw->event[0]; 1340 if (event->attr.exclude_user) 1341 cpuhw->mmcr[0] |= MMCR0_FCP; 1342 if (event->attr.exclude_kernel) 1343 cpuhw->mmcr[0] |= freeze_events_kernel; 1344 if (event->attr.exclude_hv) 1345 cpuhw->mmcr[0] |= MMCR0_FCHV; 1346 } 1347 1348 /* 1349 * Write the new configuration to MMCR* with the freeze 1350 * bit set and set the hardware events to their initial values. 1351 * Then unfreeze the events. 1352 */ 1353 ppc_set_pmu_inuse(1); 1354 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1355 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1356 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1357 | MMCR0_FC); 1358 if (ppmu->flags & PPMU_ARCH_207S) 1359 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); 1360 1361 /* 1362 * Read off any pre-existing events that need to move 1363 * to another PMC. 1364 */ 1365 for (i = 0; i < cpuhw->n_events; ++i) { 1366 event = cpuhw->event[i]; 1367 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1368 power_pmu_read(event); 1369 write_pmc(event->hw.idx, 0); 1370 event->hw.idx = 0; 1371 } 1372 } 1373 1374 /* 1375 * Initialize the PMCs for all the new and moved events. 1376 */ 1377 cpuhw->n_limited = n_lim = 0; 1378 for (i = 0; i < cpuhw->n_events; ++i) { 1379 event = cpuhw->event[i]; 1380 if (event->hw.idx) 1381 continue; 1382 idx = hwc_index[i] + 1; 1383 if (is_limited_pmc(idx)) { 1384 cpuhw->limited_counter[n_lim] = event; 1385 cpuhw->limited_hwidx[n_lim] = idx; 1386 ++n_lim; 1387 continue; 1388 } 1389 1390 if (ebb) 1391 val = local64_read(&event->hw.prev_count); 1392 else { 1393 val = 0; 1394 if (event->hw.sample_period) { 1395 left = local64_read(&event->hw.period_left); 1396 if (left < 0x80000000L) 1397 val = 0x80000000L - left; 1398 } 1399 local64_set(&event->hw.prev_count, val); 1400 } 1401 1402 event->hw.idx = idx; 1403 if (event->hw.state & PERF_HES_STOPPED) 1404 val = 0; 1405 write_pmc(idx, val); 1406 1407 perf_event_update_userpage(event); 1408 } 1409 cpuhw->n_limited = n_lim; 1410 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 1411 1412 out_enable: 1413 pmao_restore_workaround(ebb); 1414 1415 mmcr0 = ebb_switch_in(ebb, cpuhw); 1416 1417 mb(); 1418 if (cpuhw->bhrb_users) 1419 ppmu->config_bhrb(cpuhw->bhrb_filter); 1420 1421 write_mmcr0(cpuhw, mmcr0); 1422 1423 /* 1424 * Enable instruction sampling if necessary 1425 */ 1426 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1427 mb(); 1428 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 1429 } 1430 1431 out: 1432 1433 local_irq_restore(flags); 1434 } 1435 1436 static int collect_events(struct perf_event *group, int max_count, 1437 struct perf_event *ctrs[], u64 *events, 1438 unsigned int *flags) 1439 { 1440 int n = 0; 1441 struct perf_event *event; 1442 1443 if (group->pmu->task_ctx_nr == perf_hw_context) { 1444 if (n >= max_count) 1445 return -1; 1446 ctrs[n] = group; 1447 flags[n] = group->hw.event_base; 1448 events[n++] = group->hw.config; 1449 } 1450 for_each_sibling_event(event, group) { 1451 if (event->pmu->task_ctx_nr == perf_hw_context && 1452 event->state != PERF_EVENT_STATE_OFF) { 1453 if (n >= max_count) 1454 return -1; 1455 ctrs[n] = event; 1456 flags[n] = event->hw.event_base; 1457 events[n++] = event->hw.config; 1458 } 1459 } 1460 return n; 1461 } 1462 1463 /* 1464 * Add an event to the PMU. 1465 * If all events are not already frozen, then we disable and 1466 * re-enable the PMU in order to get hw_perf_enable to do the 1467 * actual work of reconfiguring the PMU. 1468 */ 1469 static int power_pmu_add(struct perf_event *event, int ef_flags) 1470 { 1471 struct cpu_hw_events *cpuhw; 1472 unsigned long flags; 1473 int n0; 1474 int ret = -EAGAIN; 1475 1476 local_irq_save(flags); 1477 perf_pmu_disable(event->pmu); 1478 1479 /* 1480 * Add the event to the list (if there is room) 1481 * and check whether the total set is still feasible. 1482 */ 1483 cpuhw = this_cpu_ptr(&cpu_hw_events); 1484 n0 = cpuhw->n_events; 1485 if (n0 >= ppmu->n_counter) 1486 goto out; 1487 cpuhw->event[n0] = event; 1488 cpuhw->events[n0] = event->hw.config; 1489 cpuhw->flags[n0] = event->hw.event_base; 1490 1491 /* 1492 * This event may have been disabled/stopped in record_and_restart() 1493 * because we exceeded the ->event_limit. If re-starting the event, 1494 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1495 * notification is re-enabled. 1496 */ 1497 if (!(ef_flags & PERF_EF_START)) 1498 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1499 else 1500 event->hw.state = 0; 1501 1502 /* 1503 * If group events scheduling transaction was started, 1504 * skip the schedulability test here, it will be performed 1505 * at commit time(->commit_txn) as a whole 1506 */ 1507 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) 1508 goto nocheck; 1509 1510 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1511 goto out; 1512 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1513 goto out; 1514 event->hw.config = cpuhw->events[n0]; 1515 1516 nocheck: 1517 ebb_event_add(event); 1518 1519 ++cpuhw->n_events; 1520 ++cpuhw->n_added; 1521 1522 ret = 0; 1523 out: 1524 if (has_branch_stack(event)) { 1525 power_pmu_bhrb_enable(event); 1526 cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1527 event->attr.branch_sample_type); 1528 } 1529 1530 perf_pmu_enable(event->pmu); 1531 local_irq_restore(flags); 1532 return ret; 1533 } 1534 1535 /* 1536 * Remove an event from the PMU. 1537 */ 1538 static void power_pmu_del(struct perf_event *event, int ef_flags) 1539 { 1540 struct cpu_hw_events *cpuhw; 1541 long i; 1542 unsigned long flags; 1543 1544 local_irq_save(flags); 1545 perf_pmu_disable(event->pmu); 1546 1547 power_pmu_read(event); 1548 1549 cpuhw = this_cpu_ptr(&cpu_hw_events); 1550 for (i = 0; i < cpuhw->n_events; ++i) { 1551 if (event == cpuhw->event[i]) { 1552 while (++i < cpuhw->n_events) { 1553 cpuhw->event[i-1] = cpuhw->event[i]; 1554 cpuhw->events[i-1] = cpuhw->events[i]; 1555 cpuhw->flags[i-1] = cpuhw->flags[i]; 1556 } 1557 --cpuhw->n_events; 1558 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1559 if (event->hw.idx) { 1560 write_pmc(event->hw.idx, 0); 1561 event->hw.idx = 0; 1562 } 1563 perf_event_update_userpage(event); 1564 break; 1565 } 1566 } 1567 for (i = 0; i < cpuhw->n_limited; ++i) 1568 if (event == cpuhw->limited_counter[i]) 1569 break; 1570 if (i < cpuhw->n_limited) { 1571 while (++i < cpuhw->n_limited) { 1572 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1573 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1574 } 1575 --cpuhw->n_limited; 1576 } 1577 if (cpuhw->n_events == 0) { 1578 /* disable exceptions if no events are running */ 1579 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1580 } 1581 1582 if (has_branch_stack(event)) 1583 power_pmu_bhrb_disable(event); 1584 1585 perf_pmu_enable(event->pmu); 1586 local_irq_restore(flags); 1587 } 1588 1589 /* 1590 * POWER-PMU does not support disabling individual counters, hence 1591 * program their cycle counter to their max value and ignore the interrupts. 1592 */ 1593 1594 static void power_pmu_start(struct perf_event *event, int ef_flags) 1595 { 1596 unsigned long flags; 1597 s64 left; 1598 unsigned long val; 1599 1600 if (!event->hw.idx || !event->hw.sample_period) 1601 return; 1602 1603 if (!(event->hw.state & PERF_HES_STOPPED)) 1604 return; 1605 1606 if (ef_flags & PERF_EF_RELOAD) 1607 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1608 1609 local_irq_save(flags); 1610 perf_pmu_disable(event->pmu); 1611 1612 event->hw.state = 0; 1613 left = local64_read(&event->hw.period_left); 1614 1615 val = 0; 1616 if (left < 0x80000000L) 1617 val = 0x80000000L - left; 1618 1619 write_pmc(event->hw.idx, val); 1620 1621 perf_event_update_userpage(event); 1622 perf_pmu_enable(event->pmu); 1623 local_irq_restore(flags); 1624 } 1625 1626 static void power_pmu_stop(struct perf_event *event, int ef_flags) 1627 { 1628 unsigned long flags; 1629 1630 if (!event->hw.idx || !event->hw.sample_period) 1631 return; 1632 1633 if (event->hw.state & PERF_HES_STOPPED) 1634 return; 1635 1636 local_irq_save(flags); 1637 perf_pmu_disable(event->pmu); 1638 1639 power_pmu_read(event); 1640 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1641 write_pmc(event->hw.idx, 0); 1642 1643 perf_event_update_userpage(event); 1644 perf_pmu_enable(event->pmu); 1645 local_irq_restore(flags); 1646 } 1647 1648 /* 1649 * Start group events scheduling transaction 1650 * Set the flag to make pmu::enable() not perform the 1651 * schedulability test, it will be performed at commit time 1652 * 1653 * We only support PERF_PMU_TXN_ADD transactions. Save the 1654 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1655 * transactions. 1656 */ 1657 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1658 { 1659 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1660 1661 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1662 1663 cpuhw->txn_flags = txn_flags; 1664 if (txn_flags & ~PERF_PMU_TXN_ADD) 1665 return; 1666 1667 perf_pmu_disable(pmu); 1668 cpuhw->n_txn_start = cpuhw->n_events; 1669 } 1670 1671 /* 1672 * Stop group events scheduling transaction 1673 * Clear the flag and pmu::enable() will perform the 1674 * schedulability test. 1675 */ 1676 static void power_pmu_cancel_txn(struct pmu *pmu) 1677 { 1678 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1679 unsigned int txn_flags; 1680 1681 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1682 1683 txn_flags = cpuhw->txn_flags; 1684 cpuhw->txn_flags = 0; 1685 if (txn_flags & ~PERF_PMU_TXN_ADD) 1686 return; 1687 1688 perf_pmu_enable(pmu); 1689 } 1690 1691 /* 1692 * Commit group events scheduling transaction 1693 * Perform the group schedulability test as a whole 1694 * Return 0 if success 1695 */ 1696 static int power_pmu_commit_txn(struct pmu *pmu) 1697 { 1698 struct cpu_hw_events *cpuhw; 1699 long i, n; 1700 1701 if (!ppmu) 1702 return -EAGAIN; 1703 1704 cpuhw = this_cpu_ptr(&cpu_hw_events); 1705 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1706 1707 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 1708 cpuhw->txn_flags = 0; 1709 return 0; 1710 } 1711 1712 n = cpuhw->n_events; 1713 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1714 return -EAGAIN; 1715 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1716 if (i < 0) 1717 return -EAGAIN; 1718 1719 for (i = cpuhw->n_txn_start; i < n; ++i) 1720 cpuhw->event[i]->hw.config = cpuhw->events[i]; 1721 1722 cpuhw->txn_flags = 0; 1723 perf_pmu_enable(pmu); 1724 return 0; 1725 } 1726 1727 /* 1728 * Return 1 if we might be able to put event on a limited PMC, 1729 * or 0 if not. 1730 * An event can only go on a limited PMC if it counts something 1731 * that a limited PMC can count, doesn't require interrupts, and 1732 * doesn't exclude any processor mode. 1733 */ 1734 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1735 unsigned int flags) 1736 { 1737 int n; 1738 u64 alt[MAX_EVENT_ALTERNATIVES]; 1739 1740 if (event->attr.exclude_user 1741 || event->attr.exclude_kernel 1742 || event->attr.exclude_hv 1743 || event->attr.sample_period) 1744 return 0; 1745 1746 if (ppmu->limited_pmc_event(ev)) 1747 return 1; 1748 1749 /* 1750 * The requested event_id isn't on a limited PMC already; 1751 * see if any alternative code goes on a limited PMC. 1752 */ 1753 if (!ppmu->get_alternatives) 1754 return 0; 1755 1756 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1757 n = ppmu->get_alternatives(ev, flags, alt); 1758 1759 return n > 0; 1760 } 1761 1762 /* 1763 * Find an alternative event_id that goes on a normal PMC, if possible, 1764 * and return the event_id code, or 0 if there is no such alternative. 1765 * (Note: event_id code 0 is "don't count" on all machines.) 1766 */ 1767 static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1768 { 1769 u64 alt[MAX_EVENT_ALTERNATIVES]; 1770 int n; 1771 1772 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1773 n = ppmu->get_alternatives(ev, flags, alt); 1774 if (!n) 1775 return 0; 1776 return alt[0]; 1777 } 1778 1779 /* Number of perf_events counting hardware events */ 1780 static atomic_t num_events; 1781 /* Used to avoid races in calling reserve/release_pmc_hardware */ 1782 static DEFINE_MUTEX(pmc_reserve_mutex); 1783 1784 /* 1785 * Release the PMU if this is the last perf_event. 1786 */ 1787 static void hw_perf_event_destroy(struct perf_event *event) 1788 { 1789 if (!atomic_add_unless(&num_events, -1, 1)) { 1790 mutex_lock(&pmc_reserve_mutex); 1791 if (atomic_dec_return(&num_events) == 0) 1792 release_pmc_hardware(); 1793 mutex_unlock(&pmc_reserve_mutex); 1794 } 1795 } 1796 1797 /* 1798 * Translate a generic cache event_id config to a raw event_id code. 1799 */ 1800 static int hw_perf_cache_event(u64 config, u64 *eventp) 1801 { 1802 unsigned long type, op, result; 1803 int ev; 1804 1805 if (!ppmu->cache_events) 1806 return -EINVAL; 1807 1808 /* unpack config */ 1809 type = config & 0xff; 1810 op = (config >> 8) & 0xff; 1811 result = (config >> 16) & 0xff; 1812 1813 if (type >= PERF_COUNT_HW_CACHE_MAX || 1814 op >= PERF_COUNT_HW_CACHE_OP_MAX || 1815 result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1816 return -EINVAL; 1817 1818 ev = (*ppmu->cache_events)[type][op][result]; 1819 if (ev == 0) 1820 return -EOPNOTSUPP; 1821 if (ev == -1) 1822 return -EINVAL; 1823 *eventp = ev; 1824 return 0; 1825 } 1826 1827 static bool is_event_blacklisted(u64 ev) 1828 { 1829 int i; 1830 1831 for (i=0; i < ppmu->n_blacklist_ev; i++) { 1832 if (ppmu->blacklist_ev[i] == ev) 1833 return true; 1834 } 1835 1836 return false; 1837 } 1838 1839 static int power_pmu_event_init(struct perf_event *event) 1840 { 1841 u64 ev; 1842 unsigned long flags; 1843 struct perf_event *ctrs[MAX_HWEVENTS]; 1844 u64 events[MAX_HWEVENTS]; 1845 unsigned int cflags[MAX_HWEVENTS]; 1846 int n; 1847 int err; 1848 struct cpu_hw_events *cpuhw; 1849 u64 bhrb_filter; 1850 1851 if (!ppmu) 1852 return -ENOENT; 1853 1854 if (has_branch_stack(event)) { 1855 /* PMU has BHRB enabled */ 1856 if (!(ppmu->flags & PPMU_ARCH_207S)) 1857 return -EOPNOTSUPP; 1858 } 1859 1860 switch (event->attr.type) { 1861 case PERF_TYPE_HARDWARE: 1862 ev = event->attr.config; 1863 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1864 return -EOPNOTSUPP; 1865 1866 if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1867 return -EINVAL; 1868 ev = ppmu->generic_events[ev]; 1869 break; 1870 case PERF_TYPE_HW_CACHE: 1871 err = hw_perf_cache_event(event->attr.config, &ev); 1872 if (err) 1873 return err; 1874 1875 if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1876 return -EINVAL; 1877 break; 1878 case PERF_TYPE_RAW: 1879 ev = event->attr.config; 1880 1881 if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1882 return -EINVAL; 1883 break; 1884 default: 1885 return -ENOENT; 1886 } 1887 1888 event->hw.config_base = ev; 1889 event->hw.idx = 0; 1890 1891 /* 1892 * If we are not running on a hypervisor, force the 1893 * exclude_hv bit to 0 so that we don't care what 1894 * the user set it to. 1895 */ 1896 if (!firmware_has_feature(FW_FEATURE_LPAR)) 1897 event->attr.exclude_hv = 0; 1898 1899 /* 1900 * If this is a per-task event, then we can use 1901 * PM_RUN_* events interchangeably with their non RUN_* 1902 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1903 * XXX we should check if the task is an idle task. 1904 */ 1905 flags = 0; 1906 if (event->attach_state & PERF_ATTACH_TASK) 1907 flags |= PPMU_ONLY_COUNT_RUN; 1908 1909 /* 1910 * If this machine has limited events, check whether this 1911 * event_id could go on a limited event. 1912 */ 1913 if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1914 if (can_go_on_limited_pmc(event, ev, flags)) { 1915 flags |= PPMU_LIMITED_PMC_OK; 1916 } else if (ppmu->limited_pmc_event(ev)) { 1917 /* 1918 * The requested event_id is on a limited PMC, 1919 * but we can't use a limited PMC; see if any 1920 * alternative goes on a normal PMC. 1921 */ 1922 ev = normal_pmc_alternative(ev, flags); 1923 if (!ev) 1924 return -EINVAL; 1925 } 1926 } 1927 1928 /* Extra checks for EBB */ 1929 err = ebb_event_check(event); 1930 if (err) 1931 return err; 1932 1933 /* 1934 * If this is in a group, check if it can go on with all the 1935 * other hardware events in the group. We assume the event 1936 * hasn't been linked into its leader's sibling list at this point. 1937 */ 1938 n = 0; 1939 if (event->group_leader != event) { 1940 n = collect_events(event->group_leader, ppmu->n_counter - 1, 1941 ctrs, events, cflags); 1942 if (n < 0) 1943 return -EINVAL; 1944 } 1945 events[n] = ev; 1946 ctrs[n] = event; 1947 cflags[n] = flags; 1948 if (check_excludes(ctrs, cflags, n, 1)) 1949 return -EINVAL; 1950 1951 cpuhw = &get_cpu_var(cpu_hw_events); 1952 err = power_check_constraints(cpuhw, events, cflags, n + 1); 1953 1954 if (has_branch_stack(event)) { 1955 bhrb_filter = ppmu->bhrb_filter_map( 1956 event->attr.branch_sample_type); 1957 1958 if (bhrb_filter == -1) { 1959 put_cpu_var(cpu_hw_events); 1960 return -EOPNOTSUPP; 1961 } 1962 cpuhw->bhrb_filter = bhrb_filter; 1963 } 1964 1965 put_cpu_var(cpu_hw_events); 1966 if (err) 1967 return -EINVAL; 1968 1969 event->hw.config = events[n]; 1970 event->hw.event_base = cflags[n]; 1971 event->hw.last_period = event->hw.sample_period; 1972 local64_set(&event->hw.period_left, event->hw.last_period); 1973 1974 /* 1975 * For EBB events we just context switch the PMC value, we don't do any 1976 * of the sample_period logic. We use hw.prev_count for this. 1977 */ 1978 if (is_ebb_event(event)) 1979 local64_set(&event->hw.prev_count, 0); 1980 1981 /* 1982 * See if we need to reserve the PMU. 1983 * If no events are currently in use, then we have to take a 1984 * mutex to ensure that we don't race with another task doing 1985 * reserve_pmc_hardware or release_pmc_hardware. 1986 */ 1987 err = 0; 1988 if (!atomic_inc_not_zero(&num_events)) { 1989 mutex_lock(&pmc_reserve_mutex); 1990 if (atomic_read(&num_events) == 0 && 1991 reserve_pmc_hardware(perf_event_interrupt)) 1992 err = -EBUSY; 1993 else 1994 atomic_inc(&num_events); 1995 mutex_unlock(&pmc_reserve_mutex); 1996 } 1997 event->destroy = hw_perf_event_destroy; 1998 1999 return err; 2000 } 2001 2002 static int power_pmu_event_idx(struct perf_event *event) 2003 { 2004 return event->hw.idx; 2005 } 2006 2007 ssize_t power_events_sysfs_show(struct device *dev, 2008 struct device_attribute *attr, char *page) 2009 { 2010 struct perf_pmu_events_attr *pmu_attr; 2011 2012 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 2013 2014 return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 2015 } 2016 2017 static struct pmu power_pmu = { 2018 .pmu_enable = power_pmu_enable, 2019 .pmu_disable = power_pmu_disable, 2020 .event_init = power_pmu_event_init, 2021 .add = power_pmu_add, 2022 .del = power_pmu_del, 2023 .start = power_pmu_start, 2024 .stop = power_pmu_stop, 2025 .read = power_pmu_read, 2026 .start_txn = power_pmu_start_txn, 2027 .cancel_txn = power_pmu_cancel_txn, 2028 .commit_txn = power_pmu_commit_txn, 2029 .event_idx = power_pmu_event_idx, 2030 .sched_task = power_pmu_sched_task, 2031 }; 2032 2033 /* 2034 * A counter has overflowed; update its count and record 2035 * things if requested. Note that interrupts are hard-disabled 2036 * here so there is no possibility of being interrupted. 2037 */ 2038 static void record_and_restart(struct perf_event *event, unsigned long val, 2039 struct pt_regs *regs) 2040 { 2041 u64 period = event->hw.sample_period; 2042 s64 prev, delta, left; 2043 int record = 0; 2044 2045 if (event->hw.state & PERF_HES_STOPPED) { 2046 write_pmc(event->hw.idx, 0); 2047 return; 2048 } 2049 2050 /* we don't have to worry about interrupts here */ 2051 prev = local64_read(&event->hw.prev_count); 2052 delta = check_and_compute_delta(prev, val); 2053 local64_add(delta, &event->count); 2054 2055 /* 2056 * See if the total period for this event has expired, 2057 * and update for the next period. 2058 */ 2059 val = 0; 2060 left = local64_read(&event->hw.period_left) - delta; 2061 if (delta == 0) 2062 left++; 2063 if (period) { 2064 if (left <= 0) { 2065 left += period; 2066 if (left <= 0) 2067 left = period; 2068 record = siar_valid(regs); 2069 event->hw.last_period = event->hw.sample_period; 2070 } 2071 if (left < 0x80000000LL) 2072 val = 0x80000000LL - left; 2073 } 2074 2075 write_pmc(event->hw.idx, val); 2076 local64_set(&event->hw.prev_count, val); 2077 local64_set(&event->hw.period_left, left); 2078 perf_event_update_userpage(event); 2079 2080 /* 2081 * Finally record data if requested. 2082 */ 2083 if (record) { 2084 struct perf_sample_data data; 2085 2086 perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 2087 2088 if (event->attr.sample_type & 2089 (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) 2090 perf_get_data_addr(regs, &data.addr); 2091 2092 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 2093 struct cpu_hw_events *cpuhw; 2094 cpuhw = this_cpu_ptr(&cpu_hw_events); 2095 power_pmu_bhrb_read(cpuhw); 2096 data.br_stack = &cpuhw->bhrb_stack; 2097 } 2098 2099 if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && 2100 ppmu->get_mem_data_src) 2101 ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); 2102 2103 if (event->attr.sample_type & PERF_SAMPLE_WEIGHT && 2104 ppmu->get_mem_weight) 2105 ppmu->get_mem_weight(&data.weight); 2106 2107 if (perf_event_overflow(event, &data, regs)) 2108 power_pmu_stop(event, 0); 2109 } 2110 } 2111 2112 /* 2113 * Called from generic code to get the misc flags (i.e. processor mode) 2114 * for an event_id. 2115 */ 2116 unsigned long perf_misc_flags(struct pt_regs *regs) 2117 { 2118 u32 flags = perf_get_misc_flags(regs); 2119 2120 if (flags) 2121 return flags; 2122 return user_mode(regs) ? PERF_RECORD_MISC_USER : 2123 PERF_RECORD_MISC_KERNEL; 2124 } 2125 2126 /* 2127 * Called from generic code to get the instruction pointer 2128 * for an event_id. 2129 */ 2130 unsigned long perf_instruction_pointer(struct pt_regs *regs) 2131 { 2132 bool use_siar = regs_use_siar(regs); 2133 2134 if (use_siar && siar_valid(regs)) 2135 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 2136 else if (use_siar) 2137 return 0; // no valid instruction pointer 2138 else 2139 return regs->nip; 2140 } 2141 2142 static bool pmc_overflow_power7(unsigned long val) 2143 { 2144 /* 2145 * Events on POWER7 can roll back if a speculative event doesn't 2146 * eventually complete. Unfortunately in some rare cases they will 2147 * raise a performance monitor exception. We need to catch this to 2148 * ensure we reset the PMC. In all cases the PMC will be 256 or less 2149 * cycles from overflow. 2150 * 2151 * We only do this if the first pass fails to find any overflowing 2152 * PMCs because a user might set a period of less than 256 and we 2153 * don't want to mistakenly reset them. 2154 */ 2155 if ((0x80000000 - val) <= 256) 2156 return true; 2157 2158 return false; 2159 } 2160 2161 static bool pmc_overflow(unsigned long val) 2162 { 2163 if ((int)val < 0) 2164 return true; 2165 2166 return false; 2167 } 2168 2169 /* 2170 * Performance monitor interrupt stuff 2171 */ 2172 static void __perf_event_interrupt(struct pt_regs *regs) 2173 { 2174 int i, j; 2175 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2176 struct perf_event *event; 2177 unsigned long val[8]; 2178 int found, active; 2179 int nmi; 2180 2181 if (cpuhw->n_limited) 2182 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2183 mfspr(SPRN_PMC6)); 2184 2185 perf_read_regs(regs); 2186 2187 nmi = perf_intr_is_nmi(regs); 2188 if (nmi) 2189 nmi_enter(); 2190 else 2191 irq_enter(); 2192 2193 /* Read all the PMCs since we'll need them a bunch of times */ 2194 for (i = 0; i < ppmu->n_counter; ++i) 2195 val[i] = read_pmc(i + 1); 2196 2197 /* Try to find what caused the IRQ */ 2198 found = 0; 2199 for (i = 0; i < ppmu->n_counter; ++i) { 2200 if (!pmc_overflow(val[i])) 2201 continue; 2202 if (is_limited_pmc(i + 1)) 2203 continue; /* these won't generate IRQs */ 2204 /* 2205 * We've found one that's overflowed. For active 2206 * counters we need to log this. For inactive 2207 * counters, we need to reset it anyway 2208 */ 2209 found = 1; 2210 active = 0; 2211 for (j = 0; j < cpuhw->n_events; ++j) { 2212 event = cpuhw->event[j]; 2213 if (event->hw.idx == (i + 1)) { 2214 active = 1; 2215 record_and_restart(event, val[i], regs); 2216 break; 2217 } 2218 } 2219 if (!active) 2220 /* reset non active counters that have overflowed */ 2221 write_pmc(i + 1, 0); 2222 } 2223 if (!found && pvr_version_is(PVR_POWER7)) { 2224 /* check active counters for special buggy p7 overflow */ 2225 for (i = 0; i < cpuhw->n_events; ++i) { 2226 event = cpuhw->event[i]; 2227 if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2228 continue; 2229 if (pmc_overflow_power7(val[event->hw.idx - 1])) { 2230 /* event has overflowed in a buggy way*/ 2231 found = 1; 2232 record_and_restart(event, 2233 val[event->hw.idx - 1], 2234 regs); 2235 } 2236 } 2237 } 2238 if (!found && !nmi && printk_ratelimit()) 2239 printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2240 2241 /* 2242 * Reset MMCR0 to its normal value. This will set PMXE and 2243 * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2244 * and thus allow interrupts to occur again. 2245 * XXX might want to use MSR.PM to keep the events frozen until 2246 * we get back out of this interrupt. 2247 */ 2248 write_mmcr0(cpuhw, cpuhw->mmcr[0]); 2249 2250 if (nmi) 2251 nmi_exit(); 2252 else 2253 irq_exit(); 2254 } 2255 2256 static void perf_event_interrupt(struct pt_regs *regs) 2257 { 2258 u64 start_clock = sched_clock(); 2259 2260 __perf_event_interrupt(regs); 2261 perf_sample_event_took(sched_clock() - start_clock); 2262 } 2263 2264 static int power_pmu_prepare_cpu(unsigned int cpu) 2265 { 2266 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2267 2268 if (ppmu) { 2269 memset(cpuhw, 0, sizeof(*cpuhw)); 2270 cpuhw->mmcr[0] = MMCR0_FC; 2271 } 2272 return 0; 2273 } 2274 2275 int register_power_pmu(struct power_pmu *pmu) 2276 { 2277 if (ppmu) 2278 return -EBUSY; /* something's already registered */ 2279 2280 ppmu = pmu; 2281 pr_info("%s performance monitor hardware support registered\n", 2282 pmu->name); 2283 2284 power_pmu.attr_groups = ppmu->attr_groups; 2285 2286 #ifdef MSR_HV 2287 /* 2288 * Use FCHV to ignore kernel events if MSR.HV is set. 2289 */ 2290 if (mfmsr() & MSR_HV) 2291 freeze_events_kernel = MMCR0_FCHV; 2292 #endif /* CONFIG_PPC64 */ 2293 2294 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 2295 cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", 2296 power_pmu_prepare_cpu, NULL); 2297 return 0; 2298 } 2299 2300 #ifdef CONFIG_PPC64 2301 static int __init init_ppc64_pmu(void) 2302 { 2303 /* run through all the pmu drivers one at a time */ 2304 if (!init_power5_pmu()) 2305 return 0; 2306 else if (!init_power5p_pmu()) 2307 return 0; 2308 else if (!init_power6_pmu()) 2309 return 0; 2310 else if (!init_power7_pmu()) 2311 return 0; 2312 else if (!init_power8_pmu()) 2313 return 0; 2314 else if (!init_power9_pmu()) 2315 return 0; 2316 else if (!init_ppc970_pmu()) 2317 return 0; 2318 else 2319 return init_generic_compat_pmu(); 2320 } 2321 early_initcall(init_ppc64_pmu); 2322 #endif 2323