12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2f2699491SMichael Ellerman /* 3f2699491SMichael Ellerman * Performance event support - powerpc architecture code 4f2699491SMichael Ellerman * 5f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 6f2699491SMichael Ellerman */ 7f2699491SMichael Ellerman #include <linux/kernel.h> 8f2699491SMichael Ellerman #include <linux/sched.h> 90c9108b0SRavi Bangoria #include <linux/sched/clock.h> 10f2699491SMichael Ellerman #include <linux/perf_event.h> 11f2699491SMichael Ellerman #include <linux/percpu.h> 12f2699491SMichael Ellerman #include <linux/hardirq.h> 1369123184SMichael Neuling #include <linux/uaccess.h> 14f2699491SMichael Ellerman #include <asm/reg.h> 15f2699491SMichael Ellerman #include <asm/pmc.h> 16f2699491SMichael Ellerman #include <asm/machdep.h> 17f2699491SMichael Ellerman #include <asm/firmware.h> 18f2699491SMichael Ellerman #include <asm/ptrace.h> 1969123184SMichael Neuling #include <asm/code-patching.h> 20f2699491SMichael Ellerman 21708597daSMadhavan Srinivasan #ifdef CONFIG_PPC64 22708597daSMadhavan Srinivasan #include "internal.h" 23708597daSMadhavan Srinivasan #endif 24708597daSMadhavan Srinivasan 253925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 263925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 273925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 28b0d436c7SAnton Blanchard #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 293925f46bSAnshuman Khandual 30f2699491SMichael Ellerman struct cpu_hw_events { 31f2699491SMichael Ellerman int n_events; 32f2699491SMichael Ellerman int n_percpu; 33f2699491SMichael Ellerman int disabled; 34f2699491SMichael Ellerman int n_added; 35f2699491SMichael Ellerman int n_limited; 36f2699491SMichael Ellerman u8 pmcs_enabled; 37f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 38f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 39f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 4078d76819SAthira Rajeev struct mmcr_regs mmcr; 41f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 42f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 43f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 44f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 45f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 46f2699491SMichael Ellerman 47fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 48f2699491SMichael Ellerman int n_txn_start; 493925f46bSAnshuman Khandual 503925f46bSAnshuman Khandual /* BHRB bits */ 513925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 52f0322f7fSAnshuman Khandual unsigned int bhrb_users; 533925f46bSAnshuman Khandual void *bhrb_context; 543925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 553925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 56356d8ce3SMadhavan Srinivasan u64 ic_init; 5791f3469aSAthira Rajeev 5891f3469aSAthira Rajeev /* Store the PMC values */ 5991f3469aSAthira Rajeev unsigned long pmcs[MAX_HWEVENTS]; 60f2699491SMichael Ellerman }; 613925f46bSAnshuman Khandual 62e51df2c1SAnton Blanchard static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 63f2699491SMichael Ellerman 64e51df2c1SAnton Blanchard static struct power_pmu *ppmu; 65f2699491SMichael Ellerman 66f2699491SMichael Ellerman /* 67f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 68f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 69f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 70f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 71f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 72f2699491SMichael Ellerman */ 73f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 74f2699491SMichael Ellerman 75f2699491SMichael Ellerman /* 76f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 77f2699491SMichael Ellerman * and a few other names are different. 78c718547eSMadhavan Srinivasan * Also 32-bit doesn't have MMCR3, SIER2 and SIER3. 79c718547eSMadhavan Srinivasan * Define them as zero knowing that any code path accessing 80c718547eSMadhavan Srinivasan * these registers (via mtspr/mfspr) are done under ppmu flag 81c718547eSMadhavan Srinivasan * check for PPMU_ARCH_31 and we will not enter that code path 82c718547eSMadhavan Srinivasan * for 32-bit. 83f2699491SMichael Ellerman */ 84f2699491SMichael Ellerman #ifdef CONFIG_PPC32 85f2699491SMichael Ellerman 86f2699491SMichael Ellerman #define MMCR0_FCHV 0 87f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 887a7a41f9SMichael Ellerman #define MMCR0_FC56 0 89378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 90330a1eb7SMichael Ellerman #define MMCR0_EBE 0 9176cb8a78SMichael Ellerman #define MMCR0_BHRBA 0 92330a1eb7SMichael Ellerman #define MMCR0_PMCC 0 93330a1eb7SMichael Ellerman #define MMCR0_PMCC_U6 0 94f2699491SMichael Ellerman 95f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 96c718547eSMadhavan Srinivasan #define SPRN_MMCR3 0 97c718547eSMadhavan Srinivasan #define SPRN_SIER2 0 98c718547eSMadhavan Srinivasan #define SPRN_SIER3 0 99f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 1009908c826SMadhavan Srinivasan #define MMCRA_BHRB_DISABLE 0 10191668ab7SAthira Rajeev #define MMCR0_PMCCEXT 0 102f2699491SMichael Ellerman 103f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 104f2699491SMichael Ellerman { 105f2699491SMichael Ellerman return 0; 106f2699491SMichael Ellerman } 107da97e184SJoel Fernandes (Google) static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { } 108f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 109f2699491SMichael Ellerman { 110f2699491SMichael Ellerman return 0; 111f2699491SMichael Ellerman } 11275382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 11375382aa7SAnton Blanchard { 11475382aa7SAnton Blanchard regs->result = 0; 11575382aa7SAnton Blanchard } 116f2699491SMichael Ellerman 117e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 118e6878835Ssukadev@linux.vnet.ibm.com { 119e6878835Ssukadev@linux.vnet.ibm.com return 1; 120e6878835Ssukadev@linux.vnet.ibm.com } 121e6878835Ssukadev@linux.vnet.ibm.com 122330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) { return false; } 123330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) { return 0; } 124330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) { } 125330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) { } 1269de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 127330a1eb7SMichael Ellerman { 12878d76819SAthira Rajeev return cpuhw->mmcr.mmcr0; 129330a1eb7SMichael Ellerman } 130330a1eb7SMichael Ellerman 131d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 132d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 133acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 134da97e184SJoel Fernandes (Google) static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {} 135c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) { } 136f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 137f2699491SMichael Ellerman 138333804dcSMadhavan Srinivasan bool is_sier_available(void) 139333804dcSMadhavan Srinivasan { 140f75e7d73SAthira Rajeev if (!ppmu) 141f75e7d73SAthira Rajeev return false; 142f75e7d73SAthira Rajeev 143333804dcSMadhavan Srinivasan if (ppmu->flags & PPMU_HAS_SIER) 144333804dcSMadhavan Srinivasan return true; 145333804dcSMadhavan Srinivasan 146333804dcSMadhavan Srinivasan return false; 147333804dcSMadhavan Srinivasan } 148333804dcSMadhavan Srinivasan 149e79b76e0SAthira Rajeev /* 150e79b76e0SAthira Rajeev * Return PMC value corresponding to the 151e79b76e0SAthira Rajeev * index passed. 152e79b76e0SAthira Rajeev */ 153e79b76e0SAthira Rajeev unsigned long get_pmcs_ext_regs(int idx) 154e79b76e0SAthira Rajeev { 155e79b76e0SAthira Rajeev struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 156e79b76e0SAthira Rajeev 157e79b76e0SAthira Rajeev return cpuhw->pmcs[idx]; 158e79b76e0SAthira Rajeev } 159e79b76e0SAthira Rajeev 16033904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 16133904054SMichael Ellerman { 16272e349f1SAnton Blanchard /* 16372e349f1SAnton Blanchard * When we take a performance monitor exception the regs are setup 16472e349f1SAnton Blanchard * using perf_read_regs() which overloads some fields, in particular 16572e349f1SAnton Blanchard * regs->result to tell us whether to use SIAR. 16672e349f1SAnton Blanchard * 16772e349f1SAnton Blanchard * However if the regs are from another exception, eg. a syscall, then 16872e349f1SAnton Blanchard * they have not been setup using perf_read_regs() and so regs->result 16972e349f1SAnton Blanchard * is something random. 17072e349f1SAnton Blanchard */ 17172e349f1SAnton Blanchard return ((TRAP(regs) == 0xf00) && regs->result); 17233904054SMichael Ellerman } 17333904054SMichael Ellerman 174f2699491SMichael Ellerman /* 175f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 176f2699491SMichael Ellerman */ 177f2699491SMichael Ellerman #ifdef CONFIG_PPC64 178f2699491SMichael Ellerman 179f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 180f2699491SMichael Ellerman { 181f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 182f2699491SMichael Ellerman 1837a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 184f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 185f2699491SMichael Ellerman if (slot > 1) 186f2699491SMichael Ellerman return 4 * (slot - 1); 187f2699491SMichael Ellerman } 1887a786832SMichael Ellerman 189f2699491SMichael Ellerman return 0; 190f2699491SMichael Ellerman } 191f2699491SMichael Ellerman 192f2699491SMichael Ellerman /* 193f2699491SMichael Ellerman * The user wants a data address recorded. 194f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 195f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 196f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 19758a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 19858a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 199f2699491SMichael Ellerman */ 200da97e184SJoel Fernandes (Google) static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) 201f2699491SMichael Ellerman { 202f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 20358a032c3SMichael Ellerman bool sdar_valid; 20458a032c3SMichael Ellerman 20558a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 20658a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 20758a032c3SMichael Ellerman else { 208e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 209e6878835Ssukadev@linux.vnet.ibm.com 210e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 211e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 212e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 213e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 214f04d1080SMadhavan Srinivasan else if (ppmu->flags & PPMU_NO_SIAR) 215f04d1080SMadhavan Srinivasan sdsync = MMCRA_SAMPLE_ENABLE; 216e6878835Ssukadev@linux.vnet.ibm.com else 217e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 218f2699491SMichael Ellerman 21958a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 22058a032c3SMichael Ellerman } 22158a032c3SMichael Ellerman 22258a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 223f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 224cd1231d7SMadhavan Srinivasan 225da97e184SJoel Fernandes (Google) if (is_kernel_addr(mfspr(SPRN_SDAR)) && perf_allow_kernel(&event->attr) != 0) 226cd1231d7SMadhavan Srinivasan *addrp = 0; 227f2699491SMichael Ellerman } 228f2699491SMichael Ellerman 2295682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 23068b30bb9SAnton Blanchard { 23168b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 23268b30bb9SAnton Blanchard 2338f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2348f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 2358f61aa32SMichael Ellerman 23668b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 23768b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 23868b30bb9SAnton Blanchard 2395682c460SMichael Ellerman return !!(regs->dsisr & sihv); 24068b30bb9SAnton Blanchard } 24168b30bb9SAnton Blanchard 2425682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 24368b30bb9SAnton Blanchard { 24468b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 24568b30bb9SAnton Blanchard 2468f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2478f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 2488f61aa32SMichael Ellerman 24968b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 25068b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 25168b30bb9SAnton Blanchard 2525682c460SMichael Ellerman return !!(regs->dsisr & sipr); 25368b30bb9SAnton Blanchard } 25468b30bb9SAnton Blanchard 2551ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 2561ce447b9SBenjamin Herrenschmidt { 2571ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 2581ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2591ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 2601ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2611ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2621ce447b9SBenjamin Herrenschmidt } 2631ce447b9SBenjamin Herrenschmidt 264f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 265f2699491SMichael Ellerman { 26633904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 267d9f7088dSAthira Rajeev unsigned long mmcra = regs->dsisr; 268d9f7088dSAthira Rajeev int marked = mmcra & MMCRA_SAMPLE_ENABLE; 269f2699491SMichael Ellerman 27075382aa7SAnton Blanchard if (!use_siar) 2711ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2721ce447b9SBenjamin Herrenschmidt 2731ce447b9SBenjamin Herrenschmidt /* 274d9f7088dSAthira Rajeev * Check the address in SIAR to identify the 275d9f7088dSAthira Rajeev * privilege levels since the SIER[MSR_HV, MSR_PR] 276d9f7088dSAthira Rajeev * bits are not set for marked events in power10 277d9f7088dSAthira Rajeev * DD1. 278d9f7088dSAthira Rajeev */ 279d9f7088dSAthira Rajeev if (marked && (ppmu->flags & PPMU_P10_DD1)) { 2802ca13a4cSMadhavan Srinivasan unsigned long siar = mfspr(SPRN_SIAR); 2812ca13a4cSMadhavan Srinivasan if (siar) { 2822ca13a4cSMadhavan Srinivasan if (is_kernel_addr(siar)) 283d9f7088dSAthira Rajeev return PERF_RECORD_MISC_KERNEL; 284d9f7088dSAthira Rajeev return PERF_RECORD_MISC_USER; 2852ca13a4cSMadhavan Srinivasan } else { 2862ca13a4cSMadhavan Srinivasan if (is_kernel_addr(regs->nip)) 2872ca13a4cSMadhavan Srinivasan return PERF_RECORD_MISC_KERNEL; 2882ca13a4cSMadhavan Srinivasan return PERF_RECORD_MISC_USER; 2892ca13a4cSMadhavan Srinivasan } 290d9f7088dSAthira Rajeev } 291d9f7088dSAthira Rajeev 292d9f7088dSAthira Rajeev /* 2931ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2941ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2951ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2961ce447b9SBenjamin Herrenschmidt * results 2971ce447b9SBenjamin Herrenschmidt */ 298cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 2991ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 300a2391b35SMadhavan Srinivasan if (is_kernel_addr(siar)) 3011ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 3021ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 3031ce447b9SBenjamin Herrenschmidt } 304f2699491SMichael Ellerman 305f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 3065682c460SMichael Ellerman if (regs_sipr(regs)) 307f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 3085682c460SMichael Ellerman 3095682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 310f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 3115682c460SMichael Ellerman 312f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 313f2699491SMichael Ellerman } 314f2699491SMichael Ellerman 315f2699491SMichael Ellerman /* 316f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 317f2699491SMichael Ellerman * on each interrupt. 3188f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 31975382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 32075382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 321f2699491SMichael Ellerman */ 322f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 323f2699491SMichael Ellerman { 32475382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 32575382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 32675382aa7SAnton Blanchard int use_siar; 32775382aa7SAnton Blanchard 3285682c460SMichael Ellerman regs->dsisr = mmcra; 329860aad71SMichael Ellerman 330cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 3318f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 3328f61aa32SMichael Ellerman 3338f61aa32SMichael Ellerman /* 3345c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 3355c093efaSAnton Blanchard * not valid. Use pt_regs. 3365c093efaSAnton Blanchard * 3375c093efaSAnton Blanchard * If it is a marked event use the SIAR. 3385c093efaSAnton Blanchard * 3395c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 3405c093efaSAnton Blanchard * pt_regs. 3415c093efaSAnton Blanchard * 3425c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 3435c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 3445c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 3455c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 3465c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 3475c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 3485c093efaSAnton Blanchard * interrupts off hence the userspace check. 3495c093efaSAnton Blanchard */ 35075382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 35175382aa7SAnton Blanchard use_siar = 0; 35227593d72SMadhavan Srinivasan else if ((ppmu->flags & PPMU_NO_SIAR)) 35327593d72SMadhavan Srinivasan use_siar = 0; 3545c093efaSAnton Blanchard else if (marked) 3555c093efaSAnton Blanchard use_siar = 1; 3565c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 3575c093efaSAnton Blanchard use_siar = 0; 358cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 35975382aa7SAnton Blanchard use_siar = 0; 36075382aa7SAnton Blanchard else 36175382aa7SAnton Blanchard use_siar = 1; 36275382aa7SAnton Blanchard 363cbda6aa1SMichael Ellerman regs->result = use_siar; 364f2699491SMichael Ellerman } 365f2699491SMichael Ellerman 366f2699491SMichael Ellerman /* 367e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 368e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 369e6878835Ssukadev@linux.vnet.ibm.com * 370e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 371e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 372e6878835Ssukadev@linux.vnet.ibm.com */ 373e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 374e6878835Ssukadev@linux.vnet.ibm.com { 375e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 376e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 377e6878835Ssukadev@linux.vnet.ibm.com 37858a032c3SMichael Ellerman if (marked) { 379fdf13a65SAthira Rajeev /* 380fdf13a65SAthira Rajeev * SIER[SIAR_VALID] is not set for some 381fdf13a65SAthira Rajeev * marked events on power10 DD1, so drop 382fdf13a65SAthira Rajeev * the check for SIER[SIAR_VALID] and return true. 383fdf13a65SAthira Rajeev */ 384fdf13a65SAthira Rajeev if (ppmu->flags & PPMU_P10_DD1) 385fdf13a65SAthira Rajeev return 0x1; 386fdf13a65SAthira Rajeev else if (ppmu->flags & PPMU_HAS_SIER) 38758a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 38858a032c3SMichael Ellerman 38958a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 390e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 39158a032c3SMichael Ellerman } 392e6878835Ssukadev@linux.vnet.ibm.com 393e6878835Ssukadev@linux.vnet.ibm.com return 1; 394e6878835Ssukadev@linux.vnet.ibm.com } 395e6878835Ssukadev@linux.vnet.ibm.com 396d52f2dc4SMichael Neuling 397d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 398d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 399d52f2dc4SMichael Neuling { 400d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 401d52f2dc4SMichael Neuling } 402d52f2dc4SMichael Neuling 403d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 404d52f2dc4SMichael Neuling { 40569111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 406d52f2dc4SMichael Neuling 407d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 408d52f2dc4SMichael Neuling return; 409d52f2dc4SMichael Neuling 410d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 411d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 412d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 413d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 414d52f2dc4SMichael Neuling } 415d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 416acba3c7eSPeter Zijlstra perf_sched_cb_inc(event->ctx->pmu); 417d52f2dc4SMichael Neuling } 418d52f2dc4SMichael Neuling 419d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 420d52f2dc4SMichael Neuling { 42169111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 422d52f2dc4SMichael Neuling 423d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 424d52f2dc4SMichael Neuling return; 425d52f2dc4SMichael Neuling 426f0322f7fSAnshuman Khandual WARN_ON_ONCE(!cpuhw->bhrb_users); 427d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 428acba3c7eSPeter Zijlstra perf_sched_cb_dec(event->ctx->pmu); 429d52f2dc4SMichael Neuling 430d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 431d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 432d52f2dc4SMichael Neuling * events are active on the PMU. 433d52f2dc4SMichael Neuling */ 434d52f2dc4SMichael Neuling 435d52f2dc4SMichael Neuling /* avoid stale pointer */ 436d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 437d52f2dc4SMichael Neuling } 438d52f2dc4SMichael Neuling } 439d52f2dc4SMichael Neuling 440d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 441d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 442d52f2dc4SMichael Neuling */ 443acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 444d52f2dc4SMichael Neuling { 445acba3c7eSPeter Zijlstra if (!ppmu->bhrb_nr) 446acba3c7eSPeter Zijlstra return; 447acba3c7eSPeter Zijlstra 448acba3c7eSPeter Zijlstra if (sched_in) 449d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 450d52f2dc4SMichael Neuling } 45169123184SMichael Neuling /* Calculate the to address for a branch */ 45269123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 45369123184SMichael Neuling { 45469123184SMichael Neuling unsigned int instr; 45569123184SMichael Neuling __u64 target; 45669123184SMichael Neuling 457f41d84ddSRavi Bangoria if (is_kernel_addr(addr)) { 458fe557319SChristoph Hellwig if (copy_from_kernel_nofault(&instr, (void *)addr, 459fe557319SChristoph Hellwig sizeof(instr))) 460f41d84ddSRavi Bangoria return 0; 461f41d84ddSRavi Bangoria 46294afd069SJordan Niethe return branch_target((struct ppc_inst *)&instr); 463f41d84ddSRavi Bangoria } 46469123184SMichael Neuling 46569123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 466c0ee37e8SChristoph Hellwig if (copy_from_user_nofault(&instr, (unsigned int __user *)addr, 467c0ee37e8SChristoph Hellwig sizeof(instr))) 46869123184SMichael Neuling return 0; 46969123184SMichael Neuling 47094afd069SJordan Niethe target = branch_target((struct ppc_inst *)&instr); 47169123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 47269123184SMichael Neuling return target; 47369123184SMichael Neuling 47469123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 47569123184SMichael Neuling return target - (unsigned long)&instr + addr; 47669123184SMichael Neuling } 477d52f2dc4SMichael Neuling 478d52f2dc4SMichael Neuling /* Processing BHRB entries */ 479da97e184SJoel Fernandes (Google) static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) 480d52f2dc4SMichael Neuling { 481d52f2dc4SMichael Neuling u64 val; 482d52f2dc4SMichael Neuling u64 addr; 483506e70d1SMichael Neuling int r_index, u_index, pred; 484d52f2dc4SMichael Neuling 485d52f2dc4SMichael Neuling r_index = 0; 486d52f2dc4SMichael Neuling u_index = 0; 487d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 488d52f2dc4SMichael Neuling /* Assembly read function */ 489506e70d1SMichael Neuling val = read_bhrb(r_index++); 490506e70d1SMichael Neuling if (!val) 491d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 492d52f2dc4SMichael Neuling break; 493506e70d1SMichael Neuling else { 494d52f2dc4SMichael Neuling addr = val & BHRB_EA; 495d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 496d52f2dc4SMichael Neuling 497506e70d1SMichael Neuling if (!addr) 498506e70d1SMichael Neuling /* invalid entry */ 499d52f2dc4SMichael Neuling continue; 500d52f2dc4SMichael Neuling 501bb19af81SMadhavan Srinivasan /* 502bb19af81SMadhavan Srinivasan * BHRB rolling buffer could very much contain the kernel 503bb19af81SMadhavan Srinivasan * addresses at this point. Check the privileges before 504bb19af81SMadhavan Srinivasan * exporting it to userspace (avoid exposure of regions 505bb19af81SMadhavan Srinivasan * where we could have speculative execution) 506bfe3b194SAthira Rajeev * Incase of ISA v3.1, BHRB will capture only user-space 507bfe3b194SAthira Rajeev * addresses, hence include a check before filtering code 508bb19af81SMadhavan Srinivasan */ 509bfe3b194SAthira Rajeev if (!(ppmu->flags & PPMU_ARCH_31) && 510bfe3b194SAthira Rajeev is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0) 511bb19af81SMadhavan Srinivasan continue; 512bb19af81SMadhavan Srinivasan 513506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 514506e70d1SMichael Neuling * the most recent branch). 515506e70d1SMichael Neuling * There are two types of valid entries: 516506e70d1SMichael Neuling * 1) a target entry which is the to address of a 517506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 518506e70d1SMichael Neuling * entry read from the bhrb will be branch 519506e70d1SMichael Neuling * corresponding to this target (ie. the actual 520506e70d1SMichael Neuling * blr/bctr/btar instruction). 521506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 522506e70d1SMichael Neuling * target entry proceeds this, then this is the 523506e70d1SMichael Neuling * matching branch for that target. If this is not 524506e70d1SMichael Neuling * following a target entry, then this is a branch 525506e70d1SMichael Neuling * where the target is given as an immediate field 526506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 527506e70d1SMichael Neuling * In this case we need to read the instruction from 528506e70d1SMichael Neuling * memory to determine the target/to address. 529506e70d1SMichael Neuling */ 530d52f2dc4SMichael Neuling 531d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 532506e70d1SMichael Neuling /* Target branches use two entries 533506e70d1SMichael Neuling * (ie. computed gotos/XL form) 534506e70d1SMichael Neuling */ 535506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 536d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 537d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 538d52f2dc4SMichael Neuling 539506e70d1SMichael Neuling /* Get from address in next entry */ 540506e70d1SMichael Neuling val = read_bhrb(r_index++); 541506e70d1SMichael Neuling addr = val & BHRB_EA; 542506e70d1SMichael Neuling if (val & BHRB_TARGET) { 543506e70d1SMichael Neuling /* Shouldn't have two targets in a 544506e70d1SMichael Neuling row.. Reset index and try again */ 545506e70d1SMichael Neuling r_index--; 546506e70d1SMichael Neuling addr = 0; 547d52f2dc4SMichael Neuling } 548506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 549506e70d1SMichael Neuling } else { 550506e70d1SMichael Neuling /* Branches to immediate field 551506e70d1SMichael Neuling (ie I or B form) */ 552506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 55369123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 55469123184SMichael Neuling power_pmu_bhrb_to(addr); 555506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 556506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 557506e70d1SMichael Neuling } 558506e70d1SMichael Neuling u_index++; 559506e70d1SMichael Neuling 560d52f2dc4SMichael Neuling } 561d52f2dc4SMichael Neuling } 562d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 563bbfd5e4fSKan Liang cpuhw->bhrb_stack.hw_idx = -1ULL; 564d52f2dc4SMichael Neuling return; 565d52f2dc4SMichael Neuling } 566d52f2dc4SMichael Neuling 567330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) 568330a1eb7SMichael Ellerman { 569330a1eb7SMichael Ellerman /* 570330a1eb7SMichael Ellerman * This could be a per-PMU callback, but we'd rather avoid the cost. We 571330a1eb7SMichael Ellerman * check that the PMU supports EBB, meaning those that don't can still 572330a1eb7SMichael Ellerman * use bit 63 of the event code for something else if they wish. 573330a1eb7SMichael Ellerman */ 5744d9690ddSJoel Stanley return (ppmu->flags & PPMU_ARCH_207S) && 5758d7c55d0SMichael Ellerman ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 576330a1eb7SMichael Ellerman } 577330a1eb7SMichael Ellerman 578330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) 579330a1eb7SMichael Ellerman { 580330a1eb7SMichael Ellerman struct perf_event *leader = event->group_leader; 581330a1eb7SMichael Ellerman 582330a1eb7SMichael Ellerman /* Event and group leader must agree on EBB */ 583330a1eb7SMichael Ellerman if (is_ebb_event(leader) != is_ebb_event(event)) 584330a1eb7SMichael Ellerman return -EINVAL; 585330a1eb7SMichael Ellerman 586330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 587330a1eb7SMichael Ellerman if (!(event->attach_state & PERF_ATTACH_TASK)) 588330a1eb7SMichael Ellerman return -EINVAL; 589330a1eb7SMichael Ellerman 590330a1eb7SMichael Ellerman if (!leader->attr.pinned || !leader->attr.exclusive) 591330a1eb7SMichael Ellerman return -EINVAL; 592330a1eb7SMichael Ellerman 59358b5fb00SMichael Ellerman if (event->attr.freq || 59458b5fb00SMichael Ellerman event->attr.inherit || 59558b5fb00SMichael Ellerman event->attr.sample_type || 59658b5fb00SMichael Ellerman event->attr.sample_period || 59758b5fb00SMichael Ellerman event->attr.enable_on_exec) 598330a1eb7SMichael Ellerman return -EINVAL; 599330a1eb7SMichael Ellerman } 600330a1eb7SMichael Ellerman 601330a1eb7SMichael Ellerman return 0; 602330a1eb7SMichael Ellerman } 603330a1eb7SMichael Ellerman 604330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) 605330a1eb7SMichael Ellerman { 606330a1eb7SMichael Ellerman if (!is_ebb_event(event) || current->thread.used_ebb) 607330a1eb7SMichael Ellerman return; 608330a1eb7SMichael Ellerman 609330a1eb7SMichael Ellerman /* 610330a1eb7SMichael Ellerman * IFF this is the first time we've added an EBB event, set 611330a1eb7SMichael Ellerman * PMXE in the user MMCR0 so we can detect when it's cleared by 612330a1eb7SMichael Ellerman * userspace. We need this so that we can context switch while 613330a1eb7SMichael Ellerman * userspace is in the EBB handler (where PMXE is 0). 614330a1eb7SMichael Ellerman */ 615330a1eb7SMichael Ellerman current->thread.used_ebb = 1; 616330a1eb7SMichael Ellerman current->thread.mmcr0 |= MMCR0_PMXE; 617330a1eb7SMichael Ellerman } 618330a1eb7SMichael Ellerman 619330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) 620330a1eb7SMichael Ellerman { 621330a1eb7SMichael Ellerman if (!(mmcr0 & MMCR0_EBE)) 622330a1eb7SMichael Ellerman return; 623330a1eb7SMichael Ellerman 624330a1eb7SMichael Ellerman current->thread.siar = mfspr(SPRN_SIAR); 625330a1eb7SMichael Ellerman current->thread.sier = mfspr(SPRN_SIER); 626330a1eb7SMichael Ellerman current->thread.sdar = mfspr(SPRN_SDAR); 627330a1eb7SMichael Ellerman current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 628330a1eb7SMichael Ellerman current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 629c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 630c718547eSMadhavan Srinivasan current->thread.mmcr3 = mfspr(SPRN_MMCR3); 631c718547eSMadhavan Srinivasan current->thread.sier2 = mfspr(SPRN_SIER2); 632c718547eSMadhavan Srinivasan current->thread.sier3 = mfspr(SPRN_SIER3); 633c718547eSMadhavan Srinivasan } 634330a1eb7SMichael Ellerman } 635330a1eb7SMichael Ellerman 6369de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 637330a1eb7SMichael Ellerman { 63878d76819SAthira Rajeev unsigned long mmcr0 = cpuhw->mmcr.mmcr0; 6399de5cb0fSMichael Ellerman 640330a1eb7SMichael Ellerman if (!ebb) 641330a1eb7SMichael Ellerman goto out; 642330a1eb7SMichael Ellerman 64376cb8a78SMichael Ellerman /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 64476cb8a78SMichael Ellerman mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 645330a1eb7SMichael Ellerman 646c2e37a26SMichael Ellerman /* 647c2e37a26SMichael Ellerman * Add any bits from the user MMCR0, FC or PMAO. This is compatible 648c2e37a26SMichael Ellerman * with pmao_restore_workaround() because we may add PMAO but we never 649c2e37a26SMichael Ellerman * clear it here. 650c2e37a26SMichael Ellerman */ 651330a1eb7SMichael Ellerman mmcr0 |= current->thread.mmcr0; 652330a1eb7SMichael Ellerman 653c2e37a26SMichael Ellerman /* 654c2e37a26SMichael Ellerman * Be careful not to set PMXE if userspace had it cleared. This is also 655c2e37a26SMichael Ellerman * compatible with pmao_restore_workaround() because it has already 656c2e37a26SMichael Ellerman * cleared PMXE and we leave PMAO alone. 657c2e37a26SMichael Ellerman */ 658330a1eb7SMichael Ellerman if (!(current->thread.mmcr0 & MMCR0_PMXE)) 659330a1eb7SMichael Ellerman mmcr0 &= ~MMCR0_PMXE; 660330a1eb7SMichael Ellerman 661330a1eb7SMichael Ellerman mtspr(SPRN_SIAR, current->thread.siar); 662330a1eb7SMichael Ellerman mtspr(SPRN_SIER, current->thread.sier); 663330a1eb7SMichael Ellerman mtspr(SPRN_SDAR, current->thread.sdar); 6649de5cb0fSMichael Ellerman 6659de5cb0fSMichael Ellerman /* 6669de5cb0fSMichael Ellerman * Merge the kernel & user values of MMCR2. The semantics we implement 6679de5cb0fSMichael Ellerman * are that the user MMCR2 can set bits, ie. cause counters to freeze, 6689de5cb0fSMichael Ellerman * but not clear bits. If a task wants to be able to clear bits, ie. 6699de5cb0fSMichael Ellerman * unfreeze counters, it should not set exclude_xxx in its events and 6709de5cb0fSMichael Ellerman * instead manage the MMCR2 entirely by itself. 6719de5cb0fSMichael Ellerman */ 67278d76819SAthira Rajeev mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2); 673c718547eSMadhavan Srinivasan 674c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 675c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, current->thread.mmcr3); 676c718547eSMadhavan Srinivasan mtspr(SPRN_SIER2, current->thread.sier2); 677c718547eSMadhavan Srinivasan mtspr(SPRN_SIER3, current->thread.sier3); 678c718547eSMadhavan Srinivasan } 679330a1eb7SMichael Ellerman out: 680330a1eb7SMichael Ellerman return mmcr0; 681330a1eb7SMichael Ellerman } 682c2e37a26SMichael Ellerman 683c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) 684c2e37a26SMichael Ellerman { 685c2e37a26SMichael Ellerman unsigned pmcs[6]; 686c2e37a26SMichael Ellerman 687c2e37a26SMichael Ellerman if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 688c2e37a26SMichael Ellerman return; 689c2e37a26SMichael Ellerman 690c2e37a26SMichael Ellerman /* 691c2e37a26SMichael Ellerman * On POWER8E there is a hardware defect which affects the PMU context 692c2e37a26SMichael Ellerman * switch logic, ie. power_pmu_disable/enable(). 693c2e37a26SMichael Ellerman * 694c2e37a26SMichael Ellerman * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 695c2e37a26SMichael Ellerman * by the hardware. Sometime later the actual PMU exception is 696c2e37a26SMichael Ellerman * delivered. 697c2e37a26SMichael Ellerman * 698c2e37a26SMichael Ellerman * If we context switch, or simply disable/enable, the PMU prior to the 699c2e37a26SMichael Ellerman * exception arriving, the exception will be lost when we clear PMAO. 700c2e37a26SMichael Ellerman * 701c2e37a26SMichael Ellerman * When we reenable the PMU, we will write the saved MMCR0 with PMAO 702c2e37a26SMichael Ellerman * set, and this _should_ generate an exception. However because of the 703c2e37a26SMichael Ellerman * defect no exception is generated when we write PMAO, and we get 704c2e37a26SMichael Ellerman * stuck with no counters counting but no exception delivered. 705c2e37a26SMichael Ellerman * 706c2e37a26SMichael Ellerman * The workaround is to detect this case and tweak the hardware to 707c2e37a26SMichael Ellerman * create another pending PMU exception. 708c2e37a26SMichael Ellerman * 709c2e37a26SMichael Ellerman * We do that by setting up PMC6 (cycles) for an imminent overflow and 710c2e37a26SMichael Ellerman * enabling the PMU. That causes a new exception to be generated in the 711c2e37a26SMichael Ellerman * chip, but we don't take it yet because we have interrupts hard 712c2e37a26SMichael Ellerman * disabled. We then write back the PMU state as we want it to be seen 713c2e37a26SMichael Ellerman * by the exception handler. When we reenable interrupts the exception 714c2e37a26SMichael Ellerman * handler will be called and see the correct state. 715c2e37a26SMichael Ellerman * 716c2e37a26SMichael Ellerman * The logic is the same for EBB, except that the exception is gated by 717c2e37a26SMichael Ellerman * us having interrupts hard disabled as well as the fact that we are 718c2e37a26SMichael Ellerman * not in userspace. The exception is finally delivered when we return 719c2e37a26SMichael Ellerman * to userspace. 720c2e37a26SMichael Ellerman */ 721c2e37a26SMichael Ellerman 722c2e37a26SMichael Ellerman /* Only if PMAO is set and PMAO_SYNC is clear */ 723c2e37a26SMichael Ellerman if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 724c2e37a26SMichael Ellerman return; 725c2e37a26SMichael Ellerman 726c2e37a26SMichael Ellerman /* If we're doing EBB, only if BESCR[GE] is set */ 727c2e37a26SMichael Ellerman if (ebb && !(current->thread.bescr & BESCR_GE)) 728c2e37a26SMichael Ellerman return; 729c2e37a26SMichael Ellerman 730c2e37a26SMichael Ellerman /* 731c2e37a26SMichael Ellerman * We are already soft-disabled in power_pmu_enable(). We need to hard 73258bffb5bSMadhavan Srinivasan * disable to actually prevent the PMU exception from firing. 733c2e37a26SMichael Ellerman */ 734c2e37a26SMichael Ellerman hard_irq_disable(); 735c2e37a26SMichael Ellerman 736c2e37a26SMichael Ellerman /* 737c2e37a26SMichael Ellerman * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 738c2e37a26SMichael Ellerman * Using read/write_pmc() in a for loop adds 12 function calls and 739c2e37a26SMichael Ellerman * almost doubles our code size. 740c2e37a26SMichael Ellerman */ 741c2e37a26SMichael Ellerman pmcs[0] = mfspr(SPRN_PMC1); 742c2e37a26SMichael Ellerman pmcs[1] = mfspr(SPRN_PMC2); 743c2e37a26SMichael Ellerman pmcs[2] = mfspr(SPRN_PMC3); 744c2e37a26SMichael Ellerman pmcs[3] = mfspr(SPRN_PMC4); 745c2e37a26SMichael Ellerman pmcs[4] = mfspr(SPRN_PMC5); 746c2e37a26SMichael Ellerman pmcs[5] = mfspr(SPRN_PMC6); 747c2e37a26SMichael Ellerman 748c2e37a26SMichael Ellerman /* Ensure all freeze bits are unset */ 749c2e37a26SMichael Ellerman mtspr(SPRN_MMCR2, 0); 750c2e37a26SMichael Ellerman 751c2e37a26SMichael Ellerman /* Set up PMC6 to overflow in one cycle */ 752c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, 0x7FFFFFFE); 753c2e37a26SMichael Ellerman 754c2e37a26SMichael Ellerman /* Enable exceptions and unfreeze PMC6 */ 755c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 756c2e37a26SMichael Ellerman 757c2e37a26SMichael Ellerman /* Now we need to refreeze and restore the PMCs */ 758c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 759c2e37a26SMichael Ellerman 760c2e37a26SMichael Ellerman mtspr(SPRN_PMC1, pmcs[0]); 761c2e37a26SMichael Ellerman mtspr(SPRN_PMC2, pmcs[1]); 762c2e37a26SMichael Ellerman mtspr(SPRN_PMC3, pmcs[2]); 763c2e37a26SMichael Ellerman mtspr(SPRN_PMC4, pmcs[3]); 764c2e37a26SMichael Ellerman mtspr(SPRN_PMC5, pmcs[4]); 765c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, pmcs[5]); 766c2e37a26SMichael Ellerman } 767356d8ce3SMadhavan Srinivasan 768f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 769f2699491SMichael Ellerman 770f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 771f2699491SMichael Ellerman 772f2699491SMichael Ellerman /* 773f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 774f2699491SMichael Ellerman */ 775f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 776f2699491SMichael Ellerman { 777f2699491SMichael Ellerman unsigned long val; 778f2699491SMichael Ellerman 779f2699491SMichael Ellerman switch (idx) { 780f2699491SMichael Ellerman case 1: 781f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 782f2699491SMichael Ellerman break; 783f2699491SMichael Ellerman case 2: 784f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 785f2699491SMichael Ellerman break; 786f2699491SMichael Ellerman case 3: 787f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 788f2699491SMichael Ellerman break; 789f2699491SMichael Ellerman case 4: 790f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 791f2699491SMichael Ellerman break; 792f2699491SMichael Ellerman case 5: 793f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 794f2699491SMichael Ellerman break; 795f2699491SMichael Ellerman case 6: 796f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 797f2699491SMichael Ellerman break; 798f2699491SMichael Ellerman #ifdef CONFIG_PPC64 799f2699491SMichael Ellerman case 7: 800f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 801f2699491SMichael Ellerman break; 802f2699491SMichael Ellerman case 8: 803f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 804f2699491SMichael Ellerman break; 805f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 806f2699491SMichael Ellerman default: 807f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 808f2699491SMichael Ellerman val = 0; 809f2699491SMichael Ellerman } 810f2699491SMichael Ellerman return val; 811f2699491SMichael Ellerman } 812f2699491SMichael Ellerman 813f2699491SMichael Ellerman /* 814f2699491SMichael Ellerman * Write one PMC. 815f2699491SMichael Ellerman */ 816f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 817f2699491SMichael Ellerman { 818f2699491SMichael Ellerman switch (idx) { 819f2699491SMichael Ellerman case 1: 820f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 821f2699491SMichael Ellerman break; 822f2699491SMichael Ellerman case 2: 823f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 824f2699491SMichael Ellerman break; 825f2699491SMichael Ellerman case 3: 826f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 827f2699491SMichael Ellerman break; 828f2699491SMichael Ellerman case 4: 829f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 830f2699491SMichael Ellerman break; 831f2699491SMichael Ellerman case 5: 832f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 833f2699491SMichael Ellerman break; 834f2699491SMichael Ellerman case 6: 835f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 836f2699491SMichael Ellerman break; 837f2699491SMichael Ellerman #ifdef CONFIG_PPC64 838f2699491SMichael Ellerman case 7: 839f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 840f2699491SMichael Ellerman break; 841f2699491SMichael Ellerman case 8: 842f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 843f2699491SMichael Ellerman break; 844f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 845f2699491SMichael Ellerman default: 846f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 847f2699491SMichael Ellerman } 848f2699491SMichael Ellerman } 849f2699491SMichael Ellerman 8505f6d0380SAnshuman Khandual /* Called from sysrq_handle_showregs() */ 8515f6d0380SAnshuman Khandual void perf_event_print_debug(void) 8525f6d0380SAnshuman Khandual { 8535f6d0380SAnshuman Khandual unsigned long sdar, sier, flags; 8545f6d0380SAnshuman Khandual u32 pmcs[MAX_HWEVENTS]; 8555f6d0380SAnshuman Khandual int i; 8565f6d0380SAnshuman Khandual 8574917fcb5SRavi Bangoria if (!ppmu) { 8584917fcb5SRavi Bangoria pr_info("Performance monitor hardware not registered.\n"); 8594917fcb5SRavi Bangoria return; 8604917fcb5SRavi Bangoria } 8614917fcb5SRavi Bangoria 8625f6d0380SAnshuman Khandual if (!ppmu->n_counter) 8635f6d0380SAnshuman Khandual return; 8645f6d0380SAnshuman Khandual 8655f6d0380SAnshuman Khandual local_irq_save(flags); 8665f6d0380SAnshuman Khandual 8675f6d0380SAnshuman Khandual pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 8685f6d0380SAnshuman Khandual smp_processor_id(), ppmu->name, ppmu->n_counter); 8695f6d0380SAnshuman Khandual 8705f6d0380SAnshuman Khandual for (i = 0; i < ppmu->n_counter; i++) 8715f6d0380SAnshuman Khandual pmcs[i] = read_pmc(i + 1); 8725f6d0380SAnshuman Khandual 8735f6d0380SAnshuman Khandual for (; i < MAX_HWEVENTS; i++) 8745f6d0380SAnshuman Khandual pmcs[i] = 0xdeadbeef; 8755f6d0380SAnshuman Khandual 8765f6d0380SAnshuman Khandual pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 8775f6d0380SAnshuman Khandual pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 8785f6d0380SAnshuman Khandual 8795f6d0380SAnshuman Khandual if (ppmu->n_counter > 4) 8805f6d0380SAnshuman Khandual pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 8815f6d0380SAnshuman Khandual pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 8825f6d0380SAnshuman Khandual 8835f6d0380SAnshuman Khandual pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 8845f6d0380SAnshuman Khandual mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 8855f6d0380SAnshuman Khandual 8865f6d0380SAnshuman Khandual sdar = sier = 0; 8875f6d0380SAnshuman Khandual #ifdef CONFIG_PPC64 8885f6d0380SAnshuman Khandual sdar = mfspr(SPRN_SDAR); 8895f6d0380SAnshuman Khandual 8905f6d0380SAnshuman Khandual if (ppmu->flags & PPMU_HAS_SIER) 8915f6d0380SAnshuman Khandual sier = mfspr(SPRN_SIER); 8925f6d0380SAnshuman Khandual 8934d9690ddSJoel Stanley if (ppmu->flags & PPMU_ARCH_207S) { 8945f6d0380SAnshuman Khandual pr_info("MMCR2: %016lx EBBHR: %016lx\n", 8955f6d0380SAnshuman Khandual mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 8965f6d0380SAnshuman Khandual pr_info("EBBRR: %016lx BESCR: %016lx\n", 8975f6d0380SAnshuman Khandual mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 8985f6d0380SAnshuman Khandual } 899c718547eSMadhavan Srinivasan 900c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 901c718547eSMadhavan Srinivasan pr_info("MMCR3: %016lx SIER2: %016lx SIER3: %016lx\n", 902c718547eSMadhavan Srinivasan mfspr(SPRN_MMCR3), mfspr(SPRN_SIER2), mfspr(SPRN_SIER3)); 903c718547eSMadhavan Srinivasan } 9045f6d0380SAnshuman Khandual #endif 9055f6d0380SAnshuman Khandual pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 9065f6d0380SAnshuman Khandual mfspr(SPRN_SIAR), sdar, sier); 9075f6d0380SAnshuman Khandual 9085f6d0380SAnshuman Khandual local_irq_restore(flags); 9095f6d0380SAnshuman Khandual } 9105f6d0380SAnshuman Khandual 911f2699491SMichael Ellerman /* 912f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 913f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 914f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 915f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 916f2699491SMichael Ellerman */ 917f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 918f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 919f2699491SMichael Ellerman int n_ev) 920f2699491SMichael Ellerman { 921f2699491SMichael Ellerman unsigned long mask, value, nv; 922f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 923f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 924f2699491SMichael Ellerman int i, j; 925f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 926f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 92759029136SMadhavan Srinivasan unsigned long grp_mask = ppmu->group_constraint_mask; 92859029136SMadhavan Srinivasan unsigned long grp_val = ppmu->group_constraint_val; 929f2699491SMichael Ellerman 930f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 931f2699491SMichael Ellerman return -1; 932f2699491SMichael Ellerman 933f2699491SMichael Ellerman /* First see if the events will go on as-is */ 934f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 935f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 936f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 937f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 938f2699491SMichael Ellerman cpuhw->alternatives[i]); 939f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 940f2699491SMichael Ellerman } 941f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 942f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 943f2699491SMichael Ellerman return -1; 944f2699491SMichael Ellerman } 945f2699491SMichael Ellerman value = mask = 0; 946f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 947f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 948f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 94959029136SMadhavan Srinivasan 95059029136SMadhavan Srinivasan if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0) 951f2699491SMichael Ellerman break; 95259029136SMadhavan Srinivasan 95359029136SMadhavan Srinivasan if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0]) 95459029136SMadhavan Srinivasan & (~grp_mask)) != 0) 95559029136SMadhavan Srinivasan break; 95659029136SMadhavan Srinivasan 957f2699491SMichael Ellerman value = nv; 958f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 959f2699491SMichael Ellerman } 96059029136SMadhavan Srinivasan if (i == n_ev) { 96159029136SMadhavan Srinivasan if ((value & mask & grp_mask) != (mask & grp_val)) 96259029136SMadhavan Srinivasan return -1; 96359029136SMadhavan Srinivasan else 964f2699491SMichael Ellerman return 0; /* all OK */ 96559029136SMadhavan Srinivasan } 966f2699491SMichael Ellerman 967f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 968f2699491SMichael Ellerman if (!ppmu->get_alternatives) 969f2699491SMichael Ellerman return -1; 970f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 971f2699491SMichael Ellerman choice[i] = 0; 972f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 973f2699491SMichael Ellerman cpuhw->alternatives[i]); 974f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 975f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 976f2699491SMichael Ellerman &cpuhw->amasks[i][j], 977f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 978f2699491SMichael Ellerman } 979f2699491SMichael Ellerman 980f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 981f2699491SMichael Ellerman i = 0; 982f2699491SMichael Ellerman j = -1; 983f2699491SMichael Ellerman value = mask = nv = 0; 984f2699491SMichael Ellerman while (i < n_ev) { 985f2699491SMichael Ellerman if (j >= 0) { 986f2699491SMichael Ellerman /* we're backtracking, restore context */ 987f2699491SMichael Ellerman value = svalues[i]; 988f2699491SMichael Ellerman mask = smasks[i]; 989f2699491SMichael Ellerman j = choice[i]; 990f2699491SMichael Ellerman } 991f2699491SMichael Ellerman /* 992f2699491SMichael Ellerman * See if any alternative k for event_id i, 993f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 994f2699491SMichael Ellerman */ 995f2699491SMichael Ellerman while (++j < n_alt[i]) { 996f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 997f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 998f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 999f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 1000f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 1001f2699491SMichael Ellerman break; 1002f2699491SMichael Ellerman } 1003f2699491SMichael Ellerman if (j >= n_alt[i]) { 1004f2699491SMichael Ellerman /* 1005f2699491SMichael Ellerman * No feasible alternative, backtrack 1006f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 1007f2699491SMichael Ellerman * alternatives from where we got up to. 1008f2699491SMichael Ellerman */ 1009f2699491SMichael Ellerman if (--i < 0) 1010f2699491SMichael Ellerman return -1; 1011f2699491SMichael Ellerman } else { 1012f2699491SMichael Ellerman /* 1013f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 1014f2699491SMichael Ellerman * remember where we got up to with this event_id, 1015f2699491SMichael Ellerman * go on to the next event_id, and start with 1016f2699491SMichael Ellerman * the first alternative for it. 1017f2699491SMichael Ellerman */ 1018f2699491SMichael Ellerman choice[i] = j; 1019f2699491SMichael Ellerman svalues[i] = value; 1020f2699491SMichael Ellerman smasks[i] = mask; 1021f2699491SMichael Ellerman value = nv; 1022f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 1023f2699491SMichael Ellerman ++i; 1024f2699491SMichael Ellerman j = -1; 1025f2699491SMichael Ellerman } 1026f2699491SMichael Ellerman } 1027f2699491SMichael Ellerman 1028f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 1029f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 1030f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 1031f2699491SMichael Ellerman return 0; 1032f2699491SMichael Ellerman } 1033f2699491SMichael Ellerman 1034f2699491SMichael Ellerman /* 1035f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 1036f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 1037f2699491SMichael Ellerman * added events. 1038f2699491SMichael Ellerman */ 1039f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 1040f2699491SMichael Ellerman int n_prev, int n_new) 1041f2699491SMichael Ellerman { 1042f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 1043f2699491SMichael Ellerman int i, n, first; 1044f2699491SMichael Ellerman struct perf_event *event; 1045f2699491SMichael Ellerman 10469de5cb0fSMichael Ellerman /* 10479de5cb0fSMichael Ellerman * If the PMU we're on supports per event exclude settings then we 10489de5cb0fSMichael Ellerman * don't need to do any of this logic. NB. This assumes no PMU has both 10499de5cb0fSMichael Ellerman * per event exclude and limited PMCs. 10509de5cb0fSMichael Ellerman */ 10519de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 10529de5cb0fSMichael Ellerman return 0; 10539de5cb0fSMichael Ellerman 1054f2699491SMichael Ellerman n = n_prev + n_new; 1055f2699491SMichael Ellerman if (n <= 1) 1056f2699491SMichael Ellerman return 0; 1057f2699491SMichael Ellerman 1058f2699491SMichael Ellerman first = 1; 1059f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 1060f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 1061f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 1062f2699491SMichael Ellerman continue; 1063f2699491SMichael Ellerman } 1064f2699491SMichael Ellerman event = ctrs[i]; 1065f2699491SMichael Ellerman if (first) { 1066f2699491SMichael Ellerman eu = event->attr.exclude_user; 1067f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 1068f2699491SMichael Ellerman eh = event->attr.exclude_hv; 1069f2699491SMichael Ellerman first = 0; 1070f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 1071f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 1072f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 1073f2699491SMichael Ellerman return -EAGAIN; 1074f2699491SMichael Ellerman } 1075f2699491SMichael Ellerman } 1076f2699491SMichael Ellerman 1077f2699491SMichael Ellerman if (eu || ek || eh) 1078f2699491SMichael Ellerman for (i = 0; i < n; ++i) 1079f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 1080f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 1081f2699491SMichael Ellerman 1082f2699491SMichael Ellerman return 0; 1083f2699491SMichael Ellerman } 1084f2699491SMichael Ellerman 1085f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 1086f2699491SMichael Ellerman { 1087f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 1088f2699491SMichael Ellerman 1089f2699491SMichael Ellerman /* 1090f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 1091f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 1092f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 1093f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 1094027dfac6SMichael Ellerman * number of events to rollback at once. If we detect a rollback 1095f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 1096f2699491SMichael Ellerman * counters. 1097f2699491SMichael Ellerman */ 1098f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 1099f2699491SMichael Ellerman delta = 0; 1100f2699491SMichael Ellerman 1101f2699491SMichael Ellerman return delta; 1102f2699491SMichael Ellerman } 1103f2699491SMichael Ellerman 1104f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 1105f2699491SMichael Ellerman { 1106f2699491SMichael Ellerman s64 val, delta, prev; 1107f2699491SMichael Ellerman 1108f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1109f2699491SMichael Ellerman return; 1110f2699491SMichael Ellerman 1111f2699491SMichael Ellerman if (!event->hw.idx) 1112f2699491SMichael Ellerman return; 1113330a1eb7SMichael Ellerman 1114330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 1115330a1eb7SMichael Ellerman val = read_pmc(event->hw.idx); 1116330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, val); 1117330a1eb7SMichael Ellerman return; 1118330a1eb7SMichael Ellerman } 1119330a1eb7SMichael Ellerman 1120f2699491SMichael Ellerman /* 1121f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 1122f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 1123f2699491SMichael Ellerman * Therefore we treat them like NMIs. 1124f2699491SMichael Ellerman */ 1125f2699491SMichael Ellerman do { 1126f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1127f2699491SMichael Ellerman barrier(); 1128f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 1129f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1130f2699491SMichael Ellerman if (!delta) 1131f2699491SMichael Ellerman return; 1132f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1133f2699491SMichael Ellerman 1134f2699491SMichael Ellerman local64_add(delta, &event->count); 1135f5602941SAnton Blanchard 1136f5602941SAnton Blanchard /* 1137f5602941SAnton Blanchard * A number of places program the PMC with (0x80000000 - period_left). 1138f5602941SAnton Blanchard * We never want period_left to be less than 1 because we will program 1139f5602941SAnton Blanchard * the PMC with a value >= 0x800000000 and an edge detected PMC will 1140f5602941SAnton Blanchard * roll around to 0 before taking an exception. We have seen this 1141f5602941SAnton Blanchard * on POWER8. 1142f5602941SAnton Blanchard * 1143f5602941SAnton Blanchard * To fix this, clamp the minimum value of period_left to 1. 1144f5602941SAnton Blanchard */ 1145f5602941SAnton Blanchard do { 1146f5602941SAnton Blanchard prev = local64_read(&event->hw.period_left); 1147f5602941SAnton Blanchard val = prev - delta; 1148f5602941SAnton Blanchard if (val < 1) 1149f5602941SAnton Blanchard val = 1; 1150f5602941SAnton Blanchard } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1151f2699491SMichael Ellerman } 1152f2699491SMichael Ellerman 1153f2699491SMichael Ellerman /* 1154f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 1155f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 1156f2699491SMichael Ellerman * us if `event' is using such a PMC. 1157f2699491SMichael Ellerman */ 1158f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 1159f2699491SMichael Ellerman { 1160f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1161f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 1162f2699491SMichael Ellerman } 1163f2699491SMichael Ellerman 1164f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1165f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1166f2699491SMichael Ellerman { 1167f2699491SMichael Ellerman struct perf_event *event; 1168f2699491SMichael Ellerman u64 val, prev, delta; 1169f2699491SMichael Ellerman int i; 1170f2699491SMichael Ellerman 1171f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1172f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1173f2699491SMichael Ellerman if (!event->hw.idx) 1174f2699491SMichael Ellerman continue; 1175f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1176f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1177f2699491SMichael Ellerman event->hw.idx = 0; 1178f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1179f2699491SMichael Ellerman if (delta) 1180f2699491SMichael Ellerman local64_add(delta, &event->count); 1181f2699491SMichael Ellerman } 1182f2699491SMichael Ellerman } 1183f2699491SMichael Ellerman 1184f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1185f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1186f2699491SMichael Ellerman { 1187f2699491SMichael Ellerman struct perf_event *event; 1188f2699491SMichael Ellerman u64 val, prev; 1189f2699491SMichael Ellerman int i; 1190f2699491SMichael Ellerman 1191f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1192f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1193f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 1194f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1195f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1196f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 1197f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1198f2699491SMichael Ellerman perf_event_update_userpage(event); 1199f2699491SMichael Ellerman } 1200f2699491SMichael Ellerman } 1201f2699491SMichael Ellerman 1202f2699491SMichael Ellerman /* 1203f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 1204f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 1205f2699491SMichael Ellerman * other events. We try to keep the values from the limited 1206f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 1207f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 1208f2699491SMichael Ellerman * the limited events as small and consistent as possible. 1209f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 1210f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 1211f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 1212f2699491SMichael Ellerman */ 1213f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1214f2699491SMichael Ellerman { 1215f2699491SMichael Ellerman unsigned long pmc5, pmc6; 1216f2699491SMichael Ellerman 1217f2699491SMichael Ellerman if (!cpuhw->n_limited) { 1218f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1219f2699491SMichael Ellerman return; 1220f2699491SMichael Ellerman } 1221f2699491SMichael Ellerman 1222f2699491SMichael Ellerman /* 1223f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 1224f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 1225f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 1226f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 1227f2699491SMichael Ellerman * interrupt enable bits turned off. 1228f2699491SMichael Ellerman */ 1229f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1230f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 1231f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1232f2699491SMichael Ellerman "i" (SPRN_MMCR0), 1233f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1234f2699491SMichael Ellerman 1235f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 1236f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 1237f2699491SMichael Ellerman else 1238f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 1239f2699491SMichael Ellerman 1240f2699491SMichael Ellerman /* 1241f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 1242f2699491SMichael Ellerman * enable bits, if necessary. 1243f2699491SMichael Ellerman */ 1244f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1245f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1246f2699491SMichael Ellerman } 1247f2699491SMichael Ellerman 1248f2699491SMichael Ellerman /* 1249f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 1250f2699491SMichael Ellerman * events to be added or removed. 1251f2699491SMichael Ellerman */ 1252f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 1253f2699491SMichael Ellerman { 1254f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 12551cade527SAthira Rajeev unsigned long flags, mmcr0, val, mmcra; 1256f2699491SMichael Ellerman 1257f2699491SMichael Ellerman if (!ppmu) 1258f2699491SMichael Ellerman return; 1259f2699491SMichael Ellerman local_irq_save(flags); 126069111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1261f2699491SMichael Ellerman 1262f2699491SMichael Ellerman if (!cpuhw->disabled) { 1263f2699491SMichael Ellerman /* 1264f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 1265f2699491SMichael Ellerman */ 1266f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 1267f2699491SMichael Ellerman ppc_enable_pmcs(); 1268f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 1269f2699491SMichael Ellerman } 1270f2699491SMichael Ellerman 1271f2699491SMichael Ellerman /* 127276cb8a78SMichael Ellerman * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1273378a6ee9SMichael Ellerman */ 1274330a1eb7SMichael Ellerman val = mmcr0 = mfspr(SPRN_MMCR0); 1275378a6ee9SMichael Ellerman val |= MMCR0_FC; 127676cb8a78SMichael Ellerman val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 127776cb8a78SMichael Ellerman MMCR0_FC56); 127891668ab7SAthira Rajeev /* Set mmcr0 PMCCEXT for p10 */ 127991668ab7SAthira Rajeev if (ppmu->flags & PPMU_ARCH_31) 128091668ab7SAthira Rajeev val |= MMCR0_PMCCEXT; 1281378a6ee9SMichael Ellerman 1282378a6ee9SMichael Ellerman /* 1283378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 1284378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 1285378a6ee9SMichael Ellerman * before we return. 1286378a6ee9SMichael Ellerman */ 1287378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 1288378a6ee9SMichael Ellerman mb(); 1289e1ebd0e5SMichael Ellerman isync(); 1290378a6ee9SMichael Ellerman 12911cade527SAthira Rajeev val = mmcra = cpuhw->mmcr.mmcra; 12921cade527SAthira Rajeev 1293378a6ee9SMichael Ellerman /* 1294f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 1295f2699491SMichael Ellerman */ 12961cade527SAthira Rajeev if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) 12971cade527SAthira Rajeev val &= ~MMCRA_SAMPLE_ENABLE; 12981cade527SAthira Rajeev 12991cade527SAthira Rajeev /* Disable BHRB via mmcra (BHRBRD) for p10 */ 13001cade527SAthira Rajeev if (ppmu->flags & PPMU_ARCH_31) 13011cade527SAthira Rajeev val |= MMCRA_BHRB_DISABLE; 13021cade527SAthira Rajeev 13031cade527SAthira Rajeev /* 13041cade527SAthira Rajeev * Write SPRN_MMCRA if mmcra has either disabled 13051cade527SAthira Rajeev * instruction sampling or BHRB. 13061cade527SAthira Rajeev */ 13071cade527SAthira Rajeev if (val != mmcra) { 13081cade527SAthira Rajeev mtspr(SPRN_MMCRA, mmcra); 1309f2699491SMichael Ellerman mb(); 1310e1ebd0e5SMichael Ellerman isync(); 1311f2699491SMichael Ellerman } 1312f2699491SMichael Ellerman 1313378a6ee9SMichael Ellerman cpuhw->disabled = 1; 1314378a6ee9SMichael Ellerman cpuhw->n_added = 0; 1315330a1eb7SMichael Ellerman 1316330a1eb7SMichael Ellerman ebb_switch_out(mmcr0); 1317e1ebd0e5SMichael Ellerman 1318e1ebd0e5SMichael Ellerman #ifdef CONFIG_PPC64 1319e1ebd0e5SMichael Ellerman /* 1320e1ebd0e5SMichael Ellerman * These are readable by userspace, may contain kernel 1321e1ebd0e5SMichael Ellerman * addresses and are not switched by context switch, so clear 1322e1ebd0e5SMichael Ellerman * them now to avoid leaking anything to userspace in general 1323e1ebd0e5SMichael Ellerman * including to another process. 1324e1ebd0e5SMichael Ellerman */ 1325e1ebd0e5SMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) { 1326e1ebd0e5SMichael Ellerman mtspr(SPRN_SDAR, 0); 1327e1ebd0e5SMichael Ellerman mtspr(SPRN_SIAR, 0); 1328e1ebd0e5SMichael Ellerman } 1329e1ebd0e5SMichael Ellerman #endif 1330f2699491SMichael Ellerman } 1331330a1eb7SMichael Ellerman 1332f2699491SMichael Ellerman local_irq_restore(flags); 1333f2699491SMichael Ellerman } 1334f2699491SMichael Ellerman 1335f2699491SMichael Ellerman /* 1336f2699491SMichael Ellerman * Re-enable all events if disable == 0. 1337f2699491SMichael Ellerman * If we were previously disabled and events were added, then 1338f2699491SMichael Ellerman * put the new config on the PMU. 1339f2699491SMichael Ellerman */ 1340f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 1341f2699491SMichael Ellerman { 1342f2699491SMichael Ellerman struct perf_event *event; 1343f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1344f2699491SMichael Ellerman unsigned long flags; 1345f2699491SMichael Ellerman long i; 1346330a1eb7SMichael Ellerman unsigned long val, mmcr0; 1347f2699491SMichael Ellerman s64 left; 1348f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 1349f2699491SMichael Ellerman int n_lim; 1350f2699491SMichael Ellerman int idx; 1351330a1eb7SMichael Ellerman bool ebb; 1352f2699491SMichael Ellerman 1353f2699491SMichael Ellerman if (!ppmu) 1354f2699491SMichael Ellerman return; 1355f2699491SMichael Ellerman local_irq_save(flags); 13560a48843dSMichael Ellerman 135769111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 13580a48843dSMichael Ellerman if (!cpuhw->disabled) 13590a48843dSMichael Ellerman goto out; 13600a48843dSMichael Ellerman 13614ea355b5SMichael Ellerman if (cpuhw->n_events == 0) { 13624ea355b5SMichael Ellerman ppc_set_pmu_inuse(0); 13634ea355b5SMichael Ellerman goto out; 13644ea355b5SMichael Ellerman } 13654ea355b5SMichael Ellerman 1366f2699491SMichael Ellerman cpuhw->disabled = 0; 1367f2699491SMichael Ellerman 1368f2699491SMichael Ellerman /* 1369330a1eb7SMichael Ellerman * EBB requires an exclusive group and all events must have the EBB 1370330a1eb7SMichael Ellerman * flag set, or not set, so we can just check a single event. Also we 1371330a1eb7SMichael Ellerman * know we have at least one event. 1372330a1eb7SMichael Ellerman */ 1373330a1eb7SMichael Ellerman ebb = is_ebb_event(cpuhw->event[0]); 1374330a1eb7SMichael Ellerman 1375330a1eb7SMichael Ellerman /* 1376f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 1377f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 1378f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 1379f2699491SMichael Ellerman * (possibly updated for removal of events). 1380f2699491SMichael Ellerman */ 1381f2699491SMichael Ellerman if (!cpuhw->n_added) { 138278d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 138378d76819SAthira Rajeev mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 1384c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) 1385c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1386f2699491SMichael Ellerman goto out_enable; 1387f2699491SMichael Ellerman } 1388f2699491SMichael Ellerman 1389f2699491SMichael Ellerman /* 139079a4cb28SMichael Ellerman * Clear all MMCR settings and recompute them for the new set of events. 1391f2699491SMichael Ellerman */ 139278d76819SAthira Rajeev memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 139379a4cb28SMichael Ellerman 1394f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 139578d76819SAthira Rajeev &cpuhw->mmcr, cpuhw->event)) { 1396f2699491SMichael Ellerman /* shouldn't ever get here */ 1397f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 1398f2699491SMichael Ellerman goto out; 1399f2699491SMichael Ellerman } 1400f2699491SMichael Ellerman 14019de5cb0fSMichael Ellerman if (!(ppmu->flags & PPMU_ARCH_207S)) { 1402f2699491SMichael Ellerman /* 14039de5cb0fSMichael Ellerman * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 14049de5cb0fSMichael Ellerman * bits for the first event. We have already checked that all 14059de5cb0fSMichael Ellerman * events have the same value for these bits as the first event. 1406f2699491SMichael Ellerman */ 1407f2699491SMichael Ellerman event = cpuhw->event[0]; 1408f2699491SMichael Ellerman if (event->attr.exclude_user) 140978d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_FCP; 1410f2699491SMichael Ellerman if (event->attr.exclude_kernel) 141178d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= freeze_events_kernel; 1412f2699491SMichael Ellerman if (event->attr.exclude_hv) 141378d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_FCHV; 14149de5cb0fSMichael Ellerman } 1415f2699491SMichael Ellerman 1416f2699491SMichael Ellerman /* 1417f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 1418f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 1419f2699491SMichael Ellerman * Then unfreeze the events. 1420f2699491SMichael Ellerman */ 1421f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 142278d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 142378d76819SAthira Rajeev mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 142478d76819SAthira Rajeev mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1425f2699491SMichael Ellerman | MMCR0_FC); 14269de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 142778d76819SAthira Rajeev mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2); 1428f2699491SMichael Ellerman 1429c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) 1430c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1431f2699491SMichael Ellerman 1432f2699491SMichael Ellerman /* 1433f2699491SMichael Ellerman * Read off any pre-existing events that need to move 1434f2699491SMichael Ellerman * to another PMC. 1435f2699491SMichael Ellerman */ 1436f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1437f2699491SMichael Ellerman event = cpuhw->event[i]; 1438f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1439f2699491SMichael Ellerman power_pmu_read(event); 1440f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1441f2699491SMichael Ellerman event->hw.idx = 0; 1442f2699491SMichael Ellerman } 1443f2699491SMichael Ellerman } 1444f2699491SMichael Ellerman 1445f2699491SMichael Ellerman /* 1446f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 1447f2699491SMichael Ellerman */ 1448f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 1449f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1450f2699491SMichael Ellerman event = cpuhw->event[i]; 1451f2699491SMichael Ellerman if (event->hw.idx) 1452f2699491SMichael Ellerman continue; 1453f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1454f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1455f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1456f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1457f2699491SMichael Ellerman ++n_lim; 1458f2699491SMichael Ellerman continue; 1459f2699491SMichael Ellerman } 1460330a1eb7SMichael Ellerman 1461330a1eb7SMichael Ellerman if (ebb) 1462330a1eb7SMichael Ellerman val = local64_read(&event->hw.prev_count); 1463330a1eb7SMichael Ellerman else { 1464f2699491SMichael Ellerman val = 0; 1465f2699491SMichael Ellerman if (event->hw.sample_period) { 1466f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1467f2699491SMichael Ellerman if (left < 0x80000000L) 1468f2699491SMichael Ellerman val = 0x80000000L - left; 1469f2699491SMichael Ellerman } 1470f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1471330a1eb7SMichael Ellerman } 1472330a1eb7SMichael Ellerman 1473f2699491SMichael Ellerman event->hw.idx = idx; 1474f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1475f2699491SMichael Ellerman val = 0; 1476f2699491SMichael Ellerman write_pmc(idx, val); 1477330a1eb7SMichael Ellerman 1478f2699491SMichael Ellerman perf_event_update_userpage(event); 1479f2699491SMichael Ellerman } 1480f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 148178d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE; 1482f2699491SMichael Ellerman 1483f2699491SMichael Ellerman out_enable: 1484c2e37a26SMichael Ellerman pmao_restore_workaround(ebb); 1485c2e37a26SMichael Ellerman 14869de5cb0fSMichael Ellerman mmcr0 = ebb_switch_in(ebb, cpuhw); 1487330a1eb7SMichael Ellerman 1488f2699491SMichael Ellerman mb(); 1489b4d6c06cSAnshuman Khandual if (cpuhw->bhrb_users) 1490b4d6c06cSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 1491b4d6c06cSAnshuman Khandual 1492330a1eb7SMichael Ellerman write_mmcr0(cpuhw, mmcr0); 1493f2699491SMichael Ellerman 1494f2699491SMichael Ellerman /* 1495f2699491SMichael Ellerman * Enable instruction sampling if necessary 1496f2699491SMichael Ellerman */ 149778d76819SAthira Rajeev if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) { 1498f2699491SMichael Ellerman mb(); 149978d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra); 1500f2699491SMichael Ellerman } 1501f2699491SMichael Ellerman 1502f2699491SMichael Ellerman out: 15033925f46bSAnshuman Khandual 1504f2699491SMichael Ellerman local_irq_restore(flags); 1505f2699491SMichael Ellerman } 1506f2699491SMichael Ellerman 1507f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1508f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1509f2699491SMichael Ellerman unsigned int *flags) 1510f2699491SMichael Ellerman { 1511f2699491SMichael Ellerman int n = 0; 1512f2699491SMichael Ellerman struct perf_event *event; 1513f2699491SMichael Ellerman 15145aa04b3eSRavi Bangoria if (group->pmu->task_ctx_nr == perf_hw_context) { 1515f2699491SMichael Ellerman if (n >= max_count) 1516f2699491SMichael Ellerman return -1; 1517f2699491SMichael Ellerman ctrs[n] = group; 1518f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1519f2699491SMichael Ellerman events[n++] = group->hw.config; 1520f2699491SMichael Ellerman } 1521edb39592SPeter Zijlstra for_each_sibling_event(event, group) { 15225aa04b3eSRavi Bangoria if (event->pmu->task_ctx_nr == perf_hw_context && 1523f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1524f2699491SMichael Ellerman if (n >= max_count) 1525f2699491SMichael Ellerman return -1; 1526f2699491SMichael Ellerman ctrs[n] = event; 1527f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1528f2699491SMichael Ellerman events[n++] = event->hw.config; 1529f2699491SMichael Ellerman } 1530f2699491SMichael Ellerman } 1531f2699491SMichael Ellerman return n; 1532f2699491SMichael Ellerman } 1533f2699491SMichael Ellerman 1534f2699491SMichael Ellerman /* 1535788faab7STobias Tefke * Add an event to the PMU. 1536f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1537f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1538f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1539f2699491SMichael Ellerman */ 1540f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1541f2699491SMichael Ellerman { 1542f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1543f2699491SMichael Ellerman unsigned long flags; 1544f2699491SMichael Ellerman int n0; 1545f2699491SMichael Ellerman int ret = -EAGAIN; 1546f2699491SMichael Ellerman 1547f2699491SMichael Ellerman local_irq_save(flags); 1548f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1549f2699491SMichael Ellerman 1550f2699491SMichael Ellerman /* 1551f2699491SMichael Ellerman * Add the event to the list (if there is room) 1552f2699491SMichael Ellerman * and check whether the total set is still feasible. 1553f2699491SMichael Ellerman */ 155469111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1555f2699491SMichael Ellerman n0 = cpuhw->n_events; 1556f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1557f2699491SMichael Ellerman goto out; 1558f2699491SMichael Ellerman cpuhw->event[n0] = event; 1559f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1560f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1561f2699491SMichael Ellerman 1562f53d168cSsukadev@linux.vnet.ibm.com /* 1563f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1564f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1565f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1566f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1567f53d168cSsukadev@linux.vnet.ibm.com */ 1568f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1569f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1570f53d168cSsukadev@linux.vnet.ibm.com else 1571f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1572f2699491SMichael Ellerman 1573f2699491SMichael Ellerman /* 1574f2699491SMichael Ellerman * If group events scheduling transaction was started, 1575f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1576f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1577f2699491SMichael Ellerman */ 15788f3e5684SSukadev Bhattiprolu if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) 1579f2699491SMichael Ellerman goto nocheck; 1580f2699491SMichael Ellerman 1581f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1582f2699491SMichael Ellerman goto out; 1583f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1584f2699491SMichael Ellerman goto out; 1585f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1586f2699491SMichael Ellerman 1587f2699491SMichael Ellerman nocheck: 1588330a1eb7SMichael Ellerman ebb_event_add(event); 1589330a1eb7SMichael Ellerman 1590f2699491SMichael Ellerman ++cpuhw->n_events; 1591f2699491SMichael Ellerman ++cpuhw->n_added; 1592f2699491SMichael Ellerman 1593f2699491SMichael Ellerman ret = 0; 1594f2699491SMichael Ellerman out: 1595ff3d79dcSAnshuman Khandual if (has_branch_stack(event)) { 1596b460b512SAlexey Kardashevskiy u64 bhrb_filter = -1; 1597b460b512SAlexey Kardashevskiy 1598b460b512SAlexey Kardashevskiy if (ppmu->bhrb_filter_map) 1599b460b512SAlexey Kardashevskiy bhrb_filter = ppmu->bhrb_filter_map( 1600ff3d79dcSAnshuman Khandual event->attr.branch_sample_type); 1601b460b512SAlexey Kardashevskiy 1602b460b512SAlexey Kardashevskiy if (bhrb_filter != -1) { 1603b460b512SAlexey Kardashevskiy cpuhw->bhrb_filter = bhrb_filter; 1604b460b512SAlexey Kardashevskiy power_pmu_bhrb_enable(event); 1605b460b512SAlexey Kardashevskiy } 1606ff3d79dcSAnshuman Khandual } 16073925f46bSAnshuman Khandual 1608f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1609f2699491SMichael Ellerman local_irq_restore(flags); 1610f2699491SMichael Ellerman return ret; 1611f2699491SMichael Ellerman } 1612f2699491SMichael Ellerman 1613f2699491SMichael Ellerman /* 1614788faab7STobias Tefke * Remove an event from the PMU. 1615f2699491SMichael Ellerman */ 1616f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1617f2699491SMichael Ellerman { 1618f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1619f2699491SMichael Ellerman long i; 1620f2699491SMichael Ellerman unsigned long flags; 1621f2699491SMichael Ellerman 1622f2699491SMichael Ellerman local_irq_save(flags); 1623f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1624f2699491SMichael Ellerman 1625f2699491SMichael Ellerman power_pmu_read(event); 1626f2699491SMichael Ellerman 162769111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1628f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1629f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1630f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1631f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1632f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1633f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1634f2699491SMichael Ellerman } 1635f2699491SMichael Ellerman --cpuhw->n_events; 163678d76819SAthira Rajeev ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr); 1637f2699491SMichael Ellerman if (event->hw.idx) { 1638f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1639f2699491SMichael Ellerman event->hw.idx = 0; 1640f2699491SMichael Ellerman } 1641f2699491SMichael Ellerman perf_event_update_userpage(event); 1642f2699491SMichael Ellerman break; 1643f2699491SMichael Ellerman } 1644f2699491SMichael Ellerman } 1645f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1646f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1647f2699491SMichael Ellerman break; 1648f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1649f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1650f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1651f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1652f2699491SMichael Ellerman } 1653f2699491SMichael Ellerman --cpuhw->n_limited; 1654f2699491SMichael Ellerman } 1655f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1656f2699491SMichael Ellerman /* disable exceptions if no events are running */ 165778d76819SAthira Rajeev cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE); 1658f2699491SMichael Ellerman } 1659f2699491SMichael Ellerman 16603925f46bSAnshuman Khandual if (has_branch_stack(event)) 16613925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 16623925f46bSAnshuman Khandual 1663f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1664f2699491SMichael Ellerman local_irq_restore(flags); 1665f2699491SMichael Ellerman } 1666f2699491SMichael Ellerman 1667f2699491SMichael Ellerman /* 1668f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1669f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1670f2699491SMichael Ellerman */ 1671f2699491SMichael Ellerman 1672f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1673f2699491SMichael Ellerman { 1674f2699491SMichael Ellerman unsigned long flags; 1675f2699491SMichael Ellerman s64 left; 1676f2699491SMichael Ellerman unsigned long val; 1677f2699491SMichael Ellerman 1678f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1679f2699491SMichael Ellerman return; 1680f2699491SMichael Ellerman 1681f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1682f2699491SMichael Ellerman return; 1683f2699491SMichael Ellerman 1684f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1685f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1686f2699491SMichael Ellerman 1687f2699491SMichael Ellerman local_irq_save(flags); 1688f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1689f2699491SMichael Ellerman 1690f2699491SMichael Ellerman event->hw.state = 0; 1691f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1692f2699491SMichael Ellerman 1693f2699491SMichael Ellerman val = 0; 1694f2699491SMichael Ellerman if (left < 0x80000000L) 1695f2699491SMichael Ellerman val = 0x80000000L - left; 1696f2699491SMichael Ellerman 1697f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1698f2699491SMichael Ellerman 1699f2699491SMichael Ellerman perf_event_update_userpage(event); 1700f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1701f2699491SMichael Ellerman local_irq_restore(flags); 1702f2699491SMichael Ellerman } 1703f2699491SMichael Ellerman 1704f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1705f2699491SMichael Ellerman { 1706f2699491SMichael Ellerman unsigned long flags; 1707f2699491SMichael Ellerman 1708f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1709f2699491SMichael Ellerman return; 1710f2699491SMichael Ellerman 1711f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1712f2699491SMichael Ellerman return; 1713f2699491SMichael Ellerman 1714f2699491SMichael Ellerman local_irq_save(flags); 1715f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1716f2699491SMichael Ellerman 1717f2699491SMichael Ellerman power_pmu_read(event); 1718f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1719f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1720f2699491SMichael Ellerman 1721f2699491SMichael Ellerman perf_event_update_userpage(event); 1722f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1723f2699491SMichael Ellerman local_irq_restore(flags); 1724f2699491SMichael Ellerman } 1725f2699491SMichael Ellerman 1726f2699491SMichael Ellerman /* 1727f2699491SMichael Ellerman * Start group events scheduling transaction 1728f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1729f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1730fbbe0701SSukadev Bhattiprolu * 1731fbbe0701SSukadev Bhattiprolu * We only support PERF_PMU_TXN_ADD transactions. Save the 1732fbbe0701SSukadev Bhattiprolu * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1733fbbe0701SSukadev Bhattiprolu * transactions. 1734f2699491SMichael Ellerman */ 1735fbbe0701SSukadev Bhattiprolu static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1736f2699491SMichael Ellerman { 173769111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1738f2699491SMichael Ellerman 1739fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1740fbbe0701SSukadev Bhattiprolu 1741fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = txn_flags; 1742fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1743fbbe0701SSukadev Bhattiprolu return; 1744fbbe0701SSukadev Bhattiprolu 1745f2699491SMichael Ellerman perf_pmu_disable(pmu); 1746f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1747f2699491SMichael Ellerman } 1748f2699491SMichael Ellerman 1749f2699491SMichael Ellerman /* 1750f2699491SMichael Ellerman * Stop group events scheduling transaction 1751f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1752f2699491SMichael Ellerman * schedulability test. 1753f2699491SMichael Ellerman */ 1754e51df2c1SAnton Blanchard static void power_pmu_cancel_txn(struct pmu *pmu) 1755f2699491SMichael Ellerman { 175669111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1757fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 1758fbbe0701SSukadev Bhattiprolu 1759fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1760fbbe0701SSukadev Bhattiprolu 1761fbbe0701SSukadev Bhattiprolu txn_flags = cpuhw->txn_flags; 1762fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1763fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1764fbbe0701SSukadev Bhattiprolu return; 1765f2699491SMichael Ellerman 1766f2699491SMichael Ellerman perf_pmu_enable(pmu); 1767f2699491SMichael Ellerman } 1768f2699491SMichael Ellerman 1769f2699491SMichael Ellerman /* 1770f2699491SMichael Ellerman * Commit group events scheduling transaction 1771f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1772f2699491SMichael Ellerman * Return 0 if success 1773f2699491SMichael Ellerman */ 1774e51df2c1SAnton Blanchard static int power_pmu_commit_txn(struct pmu *pmu) 1775f2699491SMichael Ellerman { 1776f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1777f2699491SMichael Ellerman long i, n; 1778f2699491SMichael Ellerman 1779f2699491SMichael Ellerman if (!ppmu) 1780f2699491SMichael Ellerman return -EAGAIN; 1781fbbe0701SSukadev Bhattiprolu 178269111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1783fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1784fbbe0701SSukadev Bhattiprolu 1785fbbe0701SSukadev Bhattiprolu if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 1786fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1787fbbe0701SSukadev Bhattiprolu return 0; 1788fbbe0701SSukadev Bhattiprolu } 1789fbbe0701SSukadev Bhattiprolu 1790f2699491SMichael Ellerman n = cpuhw->n_events; 1791f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1792f2699491SMichael Ellerman return -EAGAIN; 1793f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1794f2699491SMichael Ellerman if (i < 0) 1795f2699491SMichael Ellerman return -EAGAIN; 1796f2699491SMichael Ellerman 1797f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1798f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1799f2699491SMichael Ellerman 1800fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1801f2699491SMichael Ellerman perf_pmu_enable(pmu); 1802f2699491SMichael Ellerman return 0; 1803f2699491SMichael Ellerman } 1804f2699491SMichael Ellerman 1805f2699491SMichael Ellerman /* 1806f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1807f2699491SMichael Ellerman * or 0 if not. 1808788faab7STobias Tefke * An event can only go on a limited PMC if it counts something 1809f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1810f2699491SMichael Ellerman * doesn't exclude any processor mode. 1811f2699491SMichael Ellerman */ 1812f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1813f2699491SMichael Ellerman unsigned int flags) 1814f2699491SMichael Ellerman { 1815f2699491SMichael Ellerman int n; 1816f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1817f2699491SMichael Ellerman 1818f2699491SMichael Ellerman if (event->attr.exclude_user 1819f2699491SMichael Ellerman || event->attr.exclude_kernel 1820f2699491SMichael Ellerman || event->attr.exclude_hv 1821f2699491SMichael Ellerman || event->attr.sample_period) 1822f2699491SMichael Ellerman return 0; 1823f2699491SMichael Ellerman 1824f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1825f2699491SMichael Ellerman return 1; 1826f2699491SMichael Ellerman 1827f2699491SMichael Ellerman /* 1828f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1829f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1830f2699491SMichael Ellerman */ 1831f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1832f2699491SMichael Ellerman return 0; 1833f2699491SMichael Ellerman 1834f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1835f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1836f2699491SMichael Ellerman 1837f2699491SMichael Ellerman return n > 0; 1838f2699491SMichael Ellerman } 1839f2699491SMichael Ellerman 1840f2699491SMichael Ellerman /* 1841f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1842f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1843f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1844f2699491SMichael Ellerman */ 1845f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1846f2699491SMichael Ellerman { 1847f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1848f2699491SMichael Ellerman int n; 1849f2699491SMichael Ellerman 1850f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1851f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1852f2699491SMichael Ellerman if (!n) 1853f2699491SMichael Ellerman return 0; 1854f2699491SMichael Ellerman return alt[0]; 1855f2699491SMichael Ellerman } 1856f2699491SMichael Ellerman 1857f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1858f2699491SMichael Ellerman static atomic_t num_events; 1859f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1860f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1861f2699491SMichael Ellerman 1862f2699491SMichael Ellerman /* 1863f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1864f2699491SMichael Ellerman */ 1865f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1866f2699491SMichael Ellerman { 1867f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1868f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1869f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1870f2699491SMichael Ellerman release_pmc_hardware(); 1871f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1872f2699491SMichael Ellerman } 1873f2699491SMichael Ellerman } 1874f2699491SMichael Ellerman 1875f2699491SMichael Ellerman /* 1876f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1877f2699491SMichael Ellerman */ 1878f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1879f2699491SMichael Ellerman { 1880f2699491SMichael Ellerman unsigned long type, op, result; 18819d4fc86dSAthira Rajeev u64 ev; 1882f2699491SMichael Ellerman 1883f2699491SMichael Ellerman if (!ppmu->cache_events) 1884f2699491SMichael Ellerman return -EINVAL; 1885f2699491SMichael Ellerman 1886f2699491SMichael Ellerman /* unpack config */ 1887f2699491SMichael Ellerman type = config & 0xff; 1888f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1889f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1890f2699491SMichael Ellerman 1891f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1892f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1893f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1894f2699491SMichael Ellerman return -EINVAL; 1895f2699491SMichael Ellerman 1896f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1897f2699491SMichael Ellerman if (ev == 0) 1898f2699491SMichael Ellerman return -EOPNOTSUPP; 1899f2699491SMichael Ellerman if (ev == -1) 1900f2699491SMichael Ellerman return -EINVAL; 1901f2699491SMichael Ellerman *eventp = ev; 1902f2699491SMichael Ellerman return 0; 1903f2699491SMichael Ellerman } 1904f2699491SMichael Ellerman 1905b58064daSMadhavan Srinivasan static bool is_event_blacklisted(u64 ev) 1906b58064daSMadhavan Srinivasan { 1907b58064daSMadhavan Srinivasan int i; 1908b58064daSMadhavan Srinivasan 1909b58064daSMadhavan Srinivasan for (i=0; i < ppmu->n_blacklist_ev; i++) { 1910b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev[i] == ev) 1911b58064daSMadhavan Srinivasan return true; 1912b58064daSMadhavan Srinivasan } 1913b58064daSMadhavan Srinivasan 1914b58064daSMadhavan Srinivasan return false; 1915b58064daSMadhavan Srinivasan } 1916b58064daSMadhavan Srinivasan 1917f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1918f2699491SMichael Ellerman { 1919f2699491SMichael Ellerman u64 ev; 1920f66de7acSAthira Rajeev unsigned long flags, irq_flags; 1921f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1922f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1923f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1924f2699491SMichael Ellerman int n; 1925f2699491SMichael Ellerman int err; 1926f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1927f2699491SMichael Ellerman 1928f2699491SMichael Ellerman if (!ppmu) 1929f2699491SMichael Ellerman return -ENOENT; 1930f2699491SMichael Ellerman 19313925f46bSAnshuman Khandual if (has_branch_stack(event)) { 19323925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 19334d9690ddSJoel Stanley if (!(ppmu->flags & PPMU_ARCH_207S)) 19345375871dSLinus Torvalds return -EOPNOTSUPP; 19353925f46bSAnshuman Khandual } 19365375871dSLinus Torvalds 1937f2699491SMichael Ellerman switch (event->attr.type) { 1938f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1939f2699491SMichael Ellerman ev = event->attr.config; 1940f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1941f2699491SMichael Ellerman return -EOPNOTSUPP; 1942b58064daSMadhavan Srinivasan 1943b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1944b58064daSMadhavan Srinivasan return -EINVAL; 1945f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1946f2699491SMichael Ellerman break; 1947f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1948f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1949f2699491SMichael Ellerman if (err) 1950f2699491SMichael Ellerman return err; 1951b58064daSMadhavan Srinivasan 1952b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1953b58064daSMadhavan Srinivasan return -EINVAL; 1954f2699491SMichael Ellerman break; 1955f2699491SMichael Ellerman case PERF_TYPE_RAW: 1956f2699491SMichael Ellerman ev = event->attr.config; 1957b58064daSMadhavan Srinivasan 1958b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1959b58064daSMadhavan Srinivasan return -EINVAL; 1960f2699491SMichael Ellerman break; 1961f2699491SMichael Ellerman default: 1962f2699491SMichael Ellerman return -ENOENT; 1963f2699491SMichael Ellerman } 1964f2699491SMichael Ellerman 1965f2699491SMichael Ellerman event->hw.config_base = ev; 1966f2699491SMichael Ellerman event->hw.idx = 0; 1967f2699491SMichael Ellerman 1968f2699491SMichael Ellerman /* 1969f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1970f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1971f2699491SMichael Ellerman * the user set it to. 1972f2699491SMichael Ellerman */ 1973f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1974f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1975f2699491SMichael Ellerman 1976f2699491SMichael Ellerman /* 1977f2699491SMichael Ellerman * If this is a per-task event, then we can use 1978f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1979f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1980f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1981f2699491SMichael Ellerman */ 1982f2699491SMichael Ellerman flags = 0; 1983f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1984f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1985f2699491SMichael Ellerman 1986f2699491SMichael Ellerman /* 1987f2699491SMichael Ellerman * If this machine has limited events, check whether this 1988f2699491SMichael Ellerman * event_id could go on a limited event. 1989f2699491SMichael Ellerman */ 1990f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1991f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1992f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1993f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1994f2699491SMichael Ellerman /* 1995f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1996f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1997f2699491SMichael Ellerman * alternative goes on a normal PMC. 1998f2699491SMichael Ellerman */ 1999f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 2000f2699491SMichael Ellerman if (!ev) 2001f2699491SMichael Ellerman return -EINVAL; 2002f2699491SMichael Ellerman } 2003f2699491SMichael Ellerman } 2004f2699491SMichael Ellerman 2005330a1eb7SMichael Ellerman /* Extra checks for EBB */ 2006330a1eb7SMichael Ellerman err = ebb_event_check(event); 2007330a1eb7SMichael Ellerman if (err) 2008330a1eb7SMichael Ellerman return err; 2009330a1eb7SMichael Ellerman 2010f2699491SMichael Ellerman /* 2011f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 2012f2699491SMichael Ellerman * other hardware events in the group. We assume the event 2013f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 2014f2699491SMichael Ellerman */ 2015f2699491SMichael Ellerman n = 0; 2016f2699491SMichael Ellerman if (event->group_leader != event) { 2017f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 2018f2699491SMichael Ellerman ctrs, events, cflags); 2019f2699491SMichael Ellerman if (n < 0) 2020f2699491SMichael Ellerman return -EINVAL; 2021f2699491SMichael Ellerman } 2022f2699491SMichael Ellerman events[n] = ev; 2023f2699491SMichael Ellerman ctrs[n] = event; 2024f2699491SMichael Ellerman cflags[n] = flags; 2025f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 2026f2699491SMichael Ellerman return -EINVAL; 2027f2699491SMichael Ellerman 2028f66de7acSAthira Rajeev local_irq_save(irq_flags); 2029f66de7acSAthira Rajeev cpuhw = this_cpu_ptr(&cpu_hw_events); 2030f66de7acSAthira Rajeev 2031f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 20323925f46bSAnshuman Khandual 20333925f46bSAnshuman Khandual if (has_branch_stack(event)) { 2034b460b512SAlexey Kardashevskiy u64 bhrb_filter = -1; 2035b460b512SAlexey Kardashevskiy 2036b460b512SAlexey Kardashevskiy if (ppmu->bhrb_filter_map) 20373202e35eSRavi Bangoria bhrb_filter = ppmu->bhrb_filter_map( 20383925f46bSAnshuman Khandual event->attr.branch_sample_type); 20393925f46bSAnshuman Khandual 20403202e35eSRavi Bangoria if (bhrb_filter == -1) { 2041f66de7acSAthira Rajeev local_irq_restore(irq_flags); 20423925f46bSAnshuman Khandual return -EOPNOTSUPP; 20433925f46bSAnshuman Khandual } 20443202e35eSRavi Bangoria cpuhw->bhrb_filter = bhrb_filter; 204568de8867SJan Stancek } 20463925f46bSAnshuman Khandual 2047f66de7acSAthira Rajeev local_irq_restore(irq_flags); 2048f2699491SMichael Ellerman if (err) 2049f2699491SMichael Ellerman return -EINVAL; 2050f2699491SMichael Ellerman 2051f2699491SMichael Ellerman event->hw.config = events[n]; 2052f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 2053f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2054f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 2055f2699491SMichael Ellerman 2056f2699491SMichael Ellerman /* 2057330a1eb7SMichael Ellerman * For EBB events we just context switch the PMC value, we don't do any 2058330a1eb7SMichael Ellerman * of the sample_period logic. We use hw.prev_count for this. 2059330a1eb7SMichael Ellerman */ 2060330a1eb7SMichael Ellerman if (is_ebb_event(event)) 2061330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, 0); 2062330a1eb7SMichael Ellerman 2063330a1eb7SMichael Ellerman /* 2064f2699491SMichael Ellerman * See if we need to reserve the PMU. 2065f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 2066f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 2067f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 2068f2699491SMichael Ellerman */ 2069f2699491SMichael Ellerman err = 0; 2070f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 2071f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 2072f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 2073f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 2074f2699491SMichael Ellerman err = -EBUSY; 2075f2699491SMichael Ellerman else 2076f2699491SMichael Ellerman atomic_inc(&num_events); 2077f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 2078f2699491SMichael Ellerman } 2079f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 2080f2699491SMichael Ellerman 2081f2699491SMichael Ellerman return err; 2082f2699491SMichael Ellerman } 2083f2699491SMichael Ellerman 20845375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 20855375871dSLinus Torvalds { 20865375871dSLinus Torvalds return event->hw.idx; 20875375871dSLinus Torvalds } 20885375871dSLinus Torvalds 20891c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 20901c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 20911c53a270SSukadev Bhattiprolu { 20921c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 20931c53a270SSukadev Bhattiprolu 20941c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 20951c53a270SSukadev Bhattiprolu 20961c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 20971c53a270SSukadev Bhattiprolu } 20981c53a270SSukadev Bhattiprolu 2099e51df2c1SAnton Blanchard static struct pmu power_pmu = { 2100f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 2101f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 2102f2699491SMichael Ellerman .event_init = power_pmu_event_init, 2103f2699491SMichael Ellerman .add = power_pmu_add, 2104f2699491SMichael Ellerman .del = power_pmu_del, 2105f2699491SMichael Ellerman .start = power_pmu_start, 2106f2699491SMichael Ellerman .stop = power_pmu_stop, 2107f2699491SMichael Ellerman .read = power_pmu_read, 2108f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 2109f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 2110f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 21115375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 2112acba3c7eSPeter Zijlstra .sched_task = power_pmu_sched_task, 2113f2699491SMichael Ellerman }; 2114f2699491SMichael Ellerman 21154cb6a42eSKan Liang #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \ 21164cb6a42eSKan Liang PERF_SAMPLE_PHYS_ADDR | \ 21174cb6a42eSKan Liang PERF_SAMPLE_DATA_PAGE_SIZE) 2118f2699491SMichael Ellerman /* 2119f2699491SMichael Ellerman * A counter has overflowed; update its count and record 2120f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 2121f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 2122f2699491SMichael Ellerman */ 2123f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 2124f2699491SMichael Ellerman struct pt_regs *regs) 2125f2699491SMichael Ellerman { 2126f2699491SMichael Ellerman u64 period = event->hw.sample_period; 2127f2699491SMichael Ellerman s64 prev, delta, left; 2128f2699491SMichael Ellerman int record = 0; 2129f2699491SMichael Ellerman 2130f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 2131f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 2132f2699491SMichael Ellerman return; 2133f2699491SMichael Ellerman } 2134f2699491SMichael Ellerman 2135f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 2136f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 2137f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 2138f2699491SMichael Ellerman local64_add(delta, &event->count); 2139f2699491SMichael Ellerman 2140f2699491SMichael Ellerman /* 2141f2699491SMichael Ellerman * See if the total period for this event has expired, 2142f2699491SMichael Ellerman * and update for the next period. 2143f2699491SMichael Ellerman */ 2144f2699491SMichael Ellerman val = 0; 2145f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 2146e13e895fSMichael Neuling if (delta == 0) 2147e13e895fSMichael Neuling left++; 2148f2699491SMichael Ellerman if (period) { 2149f2699491SMichael Ellerman if (left <= 0) { 2150f2699491SMichael Ellerman left += period; 2151f2699491SMichael Ellerman if (left <= 0) 2152f2699491SMichael Ellerman left = period; 2153*d137845cSAthira Rajeev 2154*d137845cSAthira Rajeev /* 2155*d137845cSAthira Rajeev * If address is not requested in the sample via 2156*d137845cSAthira Rajeev * PERF_SAMPLE_IP, just record that sample irrespective 2157*d137845cSAthira Rajeev * of SIAR valid check. 2158*d137845cSAthira Rajeev */ 2159*d137845cSAthira Rajeev if (event->attr.sample_type & PERF_SAMPLE_IP) 2160e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 2161*d137845cSAthira Rajeev else 2162*d137845cSAthira Rajeev record = 1; 2163*d137845cSAthira Rajeev 2164f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2165f2699491SMichael Ellerman } 2166f2699491SMichael Ellerman if (left < 0x80000000LL) 2167f2699491SMichael Ellerman val = 0x80000000LL - left; 2168f2699491SMichael Ellerman } 2169f2699491SMichael Ellerman 2170f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 2171f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 2172f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 2173f2699491SMichael Ellerman perf_event_update_userpage(event); 2174f2699491SMichael Ellerman 2175f2699491SMichael Ellerman /* 2176aa8e21c0SAthira Rajeev * Due to hardware limitation, sometimes SIAR could sample a kernel 2177aa8e21c0SAthira Rajeev * address even when freeze on supervisor state (kernel) is set in 2178aa8e21c0SAthira Rajeev * MMCR2. Check attr.exclude_kernel and address to drop the sample in 2179aa8e21c0SAthira Rajeev * these cases. 2180aa8e21c0SAthira Rajeev */ 2181*d137845cSAthira Rajeev if (event->attr.exclude_kernel && 2182*d137845cSAthira Rajeev (event->attr.sample_type & PERF_SAMPLE_IP) && 2183*d137845cSAthira Rajeev is_kernel_addr(mfspr(SPRN_SIAR))) 2184aa8e21c0SAthira Rajeev record = 0; 2185aa8e21c0SAthira Rajeev 2186aa8e21c0SAthira Rajeev /* 2187f2699491SMichael Ellerman * Finally record data if requested. 2188f2699491SMichael Ellerman */ 2189f2699491SMichael Ellerman if (record) { 2190f2699491SMichael Ellerman struct perf_sample_data data; 2191f2699491SMichael Ellerman 2192fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 2193f2699491SMichael Ellerman 21944cb6a42eSKan Liang if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE) 2195da97e184SJoel Fernandes (Google) perf_get_data_addr(event, regs, &data.addr); 2196f2699491SMichael Ellerman 21973925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 21983925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 219969111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 2200da97e184SJoel Fernandes (Google) power_pmu_bhrb_read(event, cpuhw); 22013925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 22023925f46bSAnshuman Khandual } 22033925f46bSAnshuman Khandual 220479e96f8fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && 220579e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src) 220679e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); 220779e96f8fSMadhavan Srinivasan 2208170a315fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_WEIGHT && 2209170a315fSMadhavan Srinivasan ppmu->get_mem_weight) 2210170a315fSMadhavan Srinivasan ppmu->get_mem_weight(&data.weight); 2211170a315fSMadhavan Srinivasan 2212f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 2213f2699491SMichael Ellerman power_pmu_stop(event, 0); 221417899eafSAthira Rajeev } else if (period) { 221517899eafSAthira Rajeev /* Account for interrupt in case of invalid SIAR */ 221617899eafSAthira Rajeev if (perf_event_account_interrupt(event)) 221717899eafSAthira Rajeev power_pmu_stop(event, 0); 2218f2699491SMichael Ellerman } 2219f2699491SMichael Ellerman } 2220f2699491SMichael Ellerman 2221f2699491SMichael Ellerman /* 2222f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 2223f2699491SMichael Ellerman * for an event_id. 2224f2699491SMichael Ellerman */ 2225f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 2226f2699491SMichael Ellerman { 2227f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 2228f2699491SMichael Ellerman 2229f2699491SMichael Ellerman if (flags) 2230f2699491SMichael Ellerman return flags; 2231f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 2232f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 2233f2699491SMichael Ellerman } 2234f2699491SMichael Ellerman 2235f2699491SMichael Ellerman /* 2236f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 2237f2699491SMichael Ellerman * for an event_id. 2238f2699491SMichael Ellerman */ 2239f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 2240f2699491SMichael Ellerman { 224133904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 22422ca13a4cSMadhavan Srinivasan unsigned long siar = mfspr(SPRN_SIAR); 2243f2699491SMichael Ellerman 22442ca13a4cSMadhavan Srinivasan if (ppmu->flags & PPMU_P10_DD1) { 22452ca13a4cSMadhavan Srinivasan if (siar) 22462ca13a4cSMadhavan Srinivasan return siar; 22472ca13a4cSMadhavan Srinivasan else 22482ca13a4cSMadhavan Srinivasan return regs->nip; 22492ca13a4cSMadhavan Srinivasan } else if (use_siar && siar_valid(regs)) 22501ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 2251e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 2252e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 225375382aa7SAnton Blanchard else 225475382aa7SAnton Blanchard return regs->nip; 2255f2699491SMichael Ellerman } 2256f2699491SMichael Ellerman 2257bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 2258f2699491SMichael Ellerman { 2259f2699491SMichael Ellerman /* 2260f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 2261f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 2262f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 2263f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 2264f2699491SMichael Ellerman * cycles from overflow. 2265f2699491SMichael Ellerman * 2266f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 2267f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 2268f2699491SMichael Ellerman * don't want to mistakenly reset them. 2269f2699491SMichael Ellerman */ 2270bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 2271bc09c219SMichael Neuling return true; 2272bc09c219SMichael Neuling 2273bc09c219SMichael Neuling return false; 2274bc09c219SMichael Neuling } 2275bc09c219SMichael Neuling 2276bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 2277bc09c219SMichael Neuling { 2278bc09c219SMichael Neuling if ((int)val < 0) 2279f2699491SMichael Ellerman return true; 2280f2699491SMichael Ellerman 2281f2699491SMichael Ellerman return false; 2282f2699491SMichael Ellerman } 2283f2699491SMichael Ellerman 2284f2699491SMichael Ellerman /* 2285f2699491SMichael Ellerman * Performance monitor interrupt stuff 2286f2699491SMichael Ellerman */ 22870c9108b0SRavi Bangoria static void __perf_event_interrupt(struct pt_regs *regs) 2288f2699491SMichael Ellerman { 2289bc09c219SMichael Neuling int i, j; 229069111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2291f2699491SMichael Ellerman struct perf_event *event; 2292bc09c219SMichael Neuling int found, active; 2293f2699491SMichael Ellerman 2294f2699491SMichael Ellerman if (cpuhw->n_limited) 2295f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2296f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 2297f2699491SMichael Ellerman 2298f2699491SMichael Ellerman perf_read_regs(regs); 2299f2699491SMichael Ellerman 2300bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 2301bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 230291f3469aSAthira Rajeev cpuhw->pmcs[i] = read_pmc(i + 1); 2303bc09c219SMichael Neuling 2304bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 2305bc09c219SMichael Neuling found = 0; 2306bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 230791f3469aSAthira Rajeev if (!pmc_overflow(cpuhw->pmcs[i])) 2308bc09c219SMichael Neuling continue; 2309bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 2310bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 2311bc09c219SMichael Neuling /* 2312bc09c219SMichael Neuling * We've found one that's overflowed. For active 2313bc09c219SMichael Neuling * counters we need to log this. For inactive 2314bc09c219SMichael Neuling * counters, we need to reset it anyway 2315bc09c219SMichael Neuling */ 2316bc09c219SMichael Neuling found = 1; 2317bc09c219SMichael Neuling active = 0; 2318bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 2319bc09c219SMichael Neuling event = cpuhw->event[j]; 2320bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 2321bc09c219SMichael Neuling active = 1; 232291f3469aSAthira Rajeev record_and_restart(event, cpuhw->pmcs[i], regs); 2323bc09c219SMichael Neuling break; 2324bc09c219SMichael Neuling } 2325bc09c219SMichael Neuling } 2326bc09c219SMichael Neuling if (!active) 2327bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 2328bc09c219SMichael Neuling write_pmc(i + 1, 0); 2329bc09c219SMichael Neuling } 2330bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 2331bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 2332f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 2333f2699491SMichael Ellerman event = cpuhw->event[i]; 2334f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2335f2699491SMichael Ellerman continue; 233691f3469aSAthira Rajeev if (pmc_overflow_power7(cpuhw->pmcs[event->hw.idx - 1])) { 2337bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 2338f2699491SMichael Ellerman found = 1; 2339bc09c219SMichael Neuling record_and_restart(event, 234091f3469aSAthira Rajeev cpuhw->pmcs[event->hw.idx - 1], 2341bc09c219SMichael Neuling regs); 2342f2699491SMichael Ellerman } 2343f2699491SMichael Ellerman } 2344f2699491SMichael Ellerman } 2345156b5371SNicholas Piggin if (unlikely(!found) && !arch_irq_disabled_regs(regs)) 2346156b5371SNicholas Piggin printk_ratelimited(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2347f2699491SMichael Ellerman 2348f2699491SMichael Ellerman /* 2349f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 2350f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2351f2699491SMichael Ellerman * and thus allow interrupts to occur again. 2352f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 2353f2699491SMichael Ellerman * we get back out of this interrupt. 2354f2699491SMichael Ellerman */ 235578d76819SAthira Rajeev write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0); 235691f3469aSAthira Rajeev 235791f3469aSAthira Rajeev /* Clear the cpuhw->pmcs */ 235891f3469aSAthira Rajeev memset(&cpuhw->pmcs, 0, sizeof(cpuhw->pmcs)); 235991f3469aSAthira Rajeev 2360f2699491SMichael Ellerman } 2361f2699491SMichael Ellerman 23620c9108b0SRavi Bangoria static void perf_event_interrupt(struct pt_regs *regs) 23630c9108b0SRavi Bangoria { 23640c9108b0SRavi Bangoria u64 start_clock = sched_clock(); 23650c9108b0SRavi Bangoria 23660c9108b0SRavi Bangoria __perf_event_interrupt(regs); 23670c9108b0SRavi Bangoria perf_sample_event_took(sched_clock() - start_clock); 23680c9108b0SRavi Bangoria } 23690c9108b0SRavi Bangoria 23707c98bd72SDaniel Axtens static int power_pmu_prepare_cpu(unsigned int cpu) 2371f2699491SMichael Ellerman { 2372f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2373f2699491SMichael Ellerman 237457ecde42SThomas Gleixner if (ppmu) { 2375f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 237678d76819SAthira Rajeev cpuhw->mmcr.mmcr0 = MMCR0_FC; 2377f2699491SMichael Ellerman } 237857ecde42SThomas Gleixner return 0; 2379f2699491SMichael Ellerman } 2380f2699491SMichael Ellerman 2381061d19f2SPaul Gortmaker int register_power_pmu(struct power_pmu *pmu) 2382f2699491SMichael Ellerman { 2383f2699491SMichael Ellerman if (ppmu) 2384f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 2385f2699491SMichael Ellerman 2386f2699491SMichael Ellerman ppmu = pmu; 2387f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 2388f2699491SMichael Ellerman pmu->name); 2389f2699491SMichael Ellerman 23901c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 2391781fa481SAnju T Sudhakar power_pmu.capabilities |= (ppmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS); 23921c53a270SSukadev Bhattiprolu 2393f2699491SMichael Ellerman #ifdef MSR_HV 2394f2699491SMichael Ellerman /* 2395f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 2396f2699491SMichael Ellerman */ 2397f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 2398f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 2399f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 2400f2699491SMichael Ellerman 2401f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 240273c1b41eSThomas Gleixner cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", 240357ecde42SThomas Gleixner power_pmu_prepare_cpu, NULL); 2404f2699491SMichael Ellerman return 0; 2405f2699491SMichael Ellerman } 2406708597daSMadhavan Srinivasan 2407708597daSMadhavan Srinivasan #ifdef CONFIG_PPC64 2408708597daSMadhavan Srinivasan static int __init init_ppc64_pmu(void) 2409708597daSMadhavan Srinivasan { 2410708597daSMadhavan Srinivasan /* run through all the pmu drivers one at a time */ 2411708597daSMadhavan Srinivasan if (!init_power5_pmu()) 2412708597daSMadhavan Srinivasan return 0; 2413708597daSMadhavan Srinivasan else if (!init_power5p_pmu()) 2414708597daSMadhavan Srinivasan return 0; 2415708597daSMadhavan Srinivasan else if (!init_power6_pmu()) 2416708597daSMadhavan Srinivasan return 0; 2417708597daSMadhavan Srinivasan else if (!init_power7_pmu()) 2418708597daSMadhavan Srinivasan return 0; 2419708597daSMadhavan Srinivasan else if (!init_power8_pmu()) 2420708597daSMadhavan Srinivasan return 0; 2421708597daSMadhavan Srinivasan else if (!init_power9_pmu()) 2422708597daSMadhavan Srinivasan return 0; 2423a64e697cSAthira Rajeev else if (!init_power10_pmu()) 2424a64e697cSAthira Rajeev return 0; 2425708597daSMadhavan Srinivasan else if (!init_ppc970_pmu()) 2426708597daSMadhavan Srinivasan return 0; 2427708597daSMadhavan Srinivasan else 2428be80e758SMadhavan Srinivasan return init_generic_compat_pmu(); 2429708597daSMadhavan Srinivasan } 2430708597daSMadhavan Srinivasan early_initcall(init_ppc64_pmu); 2431708597daSMadhavan Srinivasan #endif 2432