1f2699491SMichael Ellerman /* 2f2699491SMichael Ellerman * Performance event support - powerpc architecture code 3f2699491SMichael Ellerman * 4f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5f2699491SMichael Ellerman * 6f2699491SMichael Ellerman * This program is free software; you can redistribute it and/or 7f2699491SMichael Ellerman * modify it under the terms of the GNU General Public License 8f2699491SMichael Ellerman * as published by the Free Software Foundation; either version 9f2699491SMichael Ellerman * 2 of the License, or (at your option) any later version. 10f2699491SMichael Ellerman */ 11f2699491SMichael Ellerman #include <linux/kernel.h> 12f2699491SMichael Ellerman #include <linux/sched.h> 13f2699491SMichael Ellerman #include <linux/perf_event.h> 14f2699491SMichael Ellerman #include <linux/percpu.h> 15f2699491SMichael Ellerman #include <linux/hardirq.h> 1669123184SMichael Neuling #include <linux/uaccess.h> 17f2699491SMichael Ellerman #include <asm/reg.h> 18f2699491SMichael Ellerman #include <asm/pmc.h> 19f2699491SMichael Ellerman #include <asm/machdep.h> 20f2699491SMichael Ellerman #include <asm/firmware.h> 21f2699491SMichael Ellerman #include <asm/ptrace.h> 2269123184SMichael Neuling #include <asm/code-patching.h> 23f2699491SMichael Ellerman 243925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 253925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 263925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 27b0d436c7SAnton Blanchard #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 283925f46bSAnshuman Khandual 29f2699491SMichael Ellerman struct cpu_hw_events { 30f2699491SMichael Ellerman int n_events; 31f2699491SMichael Ellerman int n_percpu; 32f2699491SMichael Ellerman int disabled; 33f2699491SMichael Ellerman int n_added; 34f2699491SMichael Ellerman int n_limited; 35f2699491SMichael Ellerman u8 pmcs_enabled; 36f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 37f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 38f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 399de5cb0fSMichael Ellerman /* 409de5cb0fSMichael Ellerman * The order of the MMCR array is: 419de5cb0fSMichael Ellerman * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 429de5cb0fSMichael Ellerman * - 32-bit, MMCR0, MMCR1, MMCR2 439de5cb0fSMichael Ellerman */ 449de5cb0fSMichael Ellerman unsigned long mmcr[4]; 45f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 46f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 47f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 48f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 49f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 50f2699491SMichael Ellerman 51fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 52f2699491SMichael Ellerman int n_txn_start; 533925f46bSAnshuman Khandual 543925f46bSAnshuman Khandual /* BHRB bits */ 553925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 56f0322f7fSAnshuman Khandual unsigned int bhrb_users; 573925f46bSAnshuman Khandual void *bhrb_context; 583925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 593925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 60356d8ce3SMadhavan Srinivasan u64 ic_init; 61f2699491SMichael Ellerman }; 623925f46bSAnshuman Khandual 63e51df2c1SAnton Blanchard static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 64f2699491SMichael Ellerman 65e51df2c1SAnton Blanchard static struct power_pmu *ppmu; 66f2699491SMichael Ellerman 67f2699491SMichael Ellerman /* 68f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 69f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 70f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 71f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 72f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 73f2699491SMichael Ellerman */ 74f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 75f2699491SMichael Ellerman 76f2699491SMichael Ellerman /* 77f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 78f2699491SMichael Ellerman * and a few other names are different. 79f2699491SMichael Ellerman */ 80f2699491SMichael Ellerman #ifdef CONFIG_PPC32 81f2699491SMichael Ellerman 82f2699491SMichael Ellerman #define MMCR0_FCHV 0 83f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 847a7a41f9SMichael Ellerman #define MMCR0_FC56 0 85378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 86330a1eb7SMichael Ellerman #define MMCR0_EBE 0 8776cb8a78SMichael Ellerman #define MMCR0_BHRBA 0 88330a1eb7SMichael Ellerman #define MMCR0_PMCC 0 89330a1eb7SMichael Ellerman #define MMCR0_PMCC_U6 0 90f2699491SMichael Ellerman 91f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 92f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 93f2699491SMichael Ellerman 94f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 95f2699491SMichael Ellerman { 96f2699491SMichael Ellerman return 0; 97f2699491SMichael Ellerman } 98f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 99f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 100f2699491SMichael Ellerman { 101f2699491SMichael Ellerman return 0; 102f2699491SMichael Ellerman } 10375382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 10475382aa7SAnton Blanchard { 10575382aa7SAnton Blanchard regs->result = 0; 10675382aa7SAnton Blanchard } 107f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 108f2699491SMichael Ellerman { 109f2699491SMichael Ellerman return 0; 110f2699491SMichael Ellerman } 111f2699491SMichael Ellerman 112e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 113e6878835Ssukadev@linux.vnet.ibm.com { 114e6878835Ssukadev@linux.vnet.ibm.com return 1; 115e6878835Ssukadev@linux.vnet.ibm.com } 116e6878835Ssukadev@linux.vnet.ibm.com 117330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) { return false; } 118330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) { return 0; } 119330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) { } 120330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) { } 1219de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 122330a1eb7SMichael Ellerman { 1239de5cb0fSMichael Ellerman return cpuhw->mmcr[0]; 124330a1eb7SMichael Ellerman } 125330a1eb7SMichael Ellerman 126d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 127d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 128acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 129d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 130c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) { } 131356d8ce3SMadhavan Srinivasan static bool use_ic(u64 event) 132356d8ce3SMadhavan Srinivasan { 133356d8ce3SMadhavan Srinivasan return false; 134356d8ce3SMadhavan Srinivasan } 135f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 136f2699491SMichael Ellerman 13733904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 13833904054SMichael Ellerman { 13972e349f1SAnton Blanchard /* 14072e349f1SAnton Blanchard * When we take a performance monitor exception the regs are setup 14172e349f1SAnton Blanchard * using perf_read_regs() which overloads some fields, in particular 14272e349f1SAnton Blanchard * regs->result to tell us whether to use SIAR. 14372e349f1SAnton Blanchard * 14472e349f1SAnton Blanchard * However if the regs are from another exception, eg. a syscall, then 14572e349f1SAnton Blanchard * they have not been setup using perf_read_regs() and so regs->result 14672e349f1SAnton Blanchard * is something random. 14772e349f1SAnton Blanchard */ 14872e349f1SAnton Blanchard return ((TRAP(regs) == 0xf00) && regs->result); 14933904054SMichael Ellerman } 15033904054SMichael Ellerman 151f2699491SMichael Ellerman /* 152f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 153f2699491SMichael Ellerman */ 154f2699491SMichael Ellerman #ifdef CONFIG_PPC64 155f2699491SMichael Ellerman 156f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 157f2699491SMichael Ellerman { 158f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 159f2699491SMichael Ellerman 1607a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 161f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 162f2699491SMichael Ellerman if (slot > 1) 163f2699491SMichael Ellerman return 4 * (slot - 1); 164f2699491SMichael Ellerman } 1657a786832SMichael Ellerman 166f2699491SMichael Ellerman return 0; 167f2699491SMichael Ellerman } 168f2699491SMichael Ellerman 169f2699491SMichael Ellerman /* 170f2699491SMichael Ellerman * The user wants a data address recorded. 171f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 172f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 173f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 17458a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 17558a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 176f2699491SMichael Ellerman */ 177f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 178f2699491SMichael Ellerman { 179f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 18058a032c3SMichael Ellerman bool sdar_valid; 18158a032c3SMichael Ellerman 18258a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 18358a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 18458a032c3SMichael Ellerman else { 185e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 186e6878835Ssukadev@linux.vnet.ibm.com 187e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 188e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 189e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 190e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 191f04d1080SMadhavan Srinivasan else if (ppmu->flags & PPMU_NO_SIAR) 192f04d1080SMadhavan Srinivasan sdsync = MMCRA_SAMPLE_ENABLE; 193e6878835Ssukadev@linux.vnet.ibm.com else 194e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 195f2699491SMichael Ellerman 19658a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 19758a032c3SMichael Ellerman } 19858a032c3SMichael Ellerman 19958a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 200f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 201f2699491SMichael Ellerman } 202f2699491SMichael Ellerman 2035682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 20468b30bb9SAnton Blanchard { 20568b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 20668b30bb9SAnton Blanchard 2078f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2088f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 2098f61aa32SMichael Ellerman 21068b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 21168b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 21268b30bb9SAnton Blanchard 2135682c460SMichael Ellerman return !!(regs->dsisr & sihv); 21468b30bb9SAnton Blanchard } 21568b30bb9SAnton Blanchard 2165682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 21768b30bb9SAnton Blanchard { 21868b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 21968b30bb9SAnton Blanchard 2208f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2218f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 2228f61aa32SMichael Ellerman 22368b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 22468b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 22568b30bb9SAnton Blanchard 2265682c460SMichael Ellerman return !!(regs->dsisr & sipr); 22768b30bb9SAnton Blanchard } 22868b30bb9SAnton Blanchard 2291ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 2301ce447b9SBenjamin Herrenschmidt { 2311ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 2321ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2331ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 2341ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2351ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2361ce447b9SBenjamin Herrenschmidt } 2371ce447b9SBenjamin Herrenschmidt 238f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 239f2699491SMichael Ellerman { 24033904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 241f2699491SMichael Ellerman 24275382aa7SAnton Blanchard if (!use_siar) 2431ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2441ce447b9SBenjamin Herrenschmidt 2451ce447b9SBenjamin Herrenschmidt /* 2461ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2471ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2481ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2491ce447b9SBenjamin Herrenschmidt * results 2501ce447b9SBenjamin Herrenschmidt */ 251cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 2521ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 253a2391b35SMadhavan Srinivasan if (is_kernel_addr(siar)) 2541ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2551ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2561ce447b9SBenjamin Herrenschmidt } 257f2699491SMichael Ellerman 258f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 2595682c460SMichael Ellerman if (regs_sipr(regs)) 260f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 2615682c460SMichael Ellerman 2625682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 263f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 2645682c460SMichael Ellerman 265f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 266f2699491SMichael Ellerman } 267f2699491SMichael Ellerman 268f2699491SMichael Ellerman /* 269f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 270f2699491SMichael Ellerman * on each interrupt. 2718f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 27275382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 27375382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 274f2699491SMichael Ellerman */ 275f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 276f2699491SMichael Ellerman { 27775382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 27875382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 27975382aa7SAnton Blanchard int use_siar; 28075382aa7SAnton Blanchard 2815682c460SMichael Ellerman regs->dsisr = mmcra; 282860aad71SMichael Ellerman 283cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2848f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 2858f61aa32SMichael Ellerman 2868f61aa32SMichael Ellerman /* 2875c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 2885c093efaSAnton Blanchard * not valid. Use pt_regs. 2895c093efaSAnton Blanchard * 2905c093efaSAnton Blanchard * If it is a marked event use the SIAR. 2915c093efaSAnton Blanchard * 2925c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 2935c093efaSAnton Blanchard * pt_regs. 2945c093efaSAnton Blanchard * 2955c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 2965c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 2975c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 2985c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 2995c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 3005c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 3015c093efaSAnton Blanchard * interrupts off hence the userspace check. 3025c093efaSAnton Blanchard */ 30375382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 30475382aa7SAnton Blanchard use_siar = 0; 30527593d72SMadhavan Srinivasan else if ((ppmu->flags & PPMU_NO_SIAR)) 30627593d72SMadhavan Srinivasan use_siar = 0; 3075c093efaSAnton Blanchard else if (marked) 3085c093efaSAnton Blanchard use_siar = 1; 3095c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 3105c093efaSAnton Blanchard use_siar = 0; 311cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 31275382aa7SAnton Blanchard use_siar = 0; 31375382aa7SAnton Blanchard else 31475382aa7SAnton Blanchard use_siar = 1; 31575382aa7SAnton Blanchard 316cbda6aa1SMichael Ellerman regs->result = use_siar; 317f2699491SMichael Ellerman } 318f2699491SMichael Ellerman 319f2699491SMichael Ellerman /* 320f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 321f2699491SMichael Ellerman * it as an NMI. 322f2699491SMichael Ellerman */ 323f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 324f2699491SMichael Ellerman { 32501417c6cSMadhavan Srinivasan return (regs->softe & IRQS_DISABLED); 326f2699491SMichael Ellerman } 327f2699491SMichael Ellerman 328e6878835Ssukadev@linux.vnet.ibm.com /* 329e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 330e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 331e6878835Ssukadev@linux.vnet.ibm.com * 332e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 333e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 334e6878835Ssukadev@linux.vnet.ibm.com */ 335e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 336e6878835Ssukadev@linux.vnet.ibm.com { 337e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 338e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 339e6878835Ssukadev@linux.vnet.ibm.com 34058a032c3SMichael Ellerman if (marked) { 34158a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 34258a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 34358a032c3SMichael Ellerman 34458a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 345e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 34658a032c3SMichael Ellerman } 347e6878835Ssukadev@linux.vnet.ibm.com 348e6878835Ssukadev@linux.vnet.ibm.com return 1; 349e6878835Ssukadev@linux.vnet.ibm.com } 350e6878835Ssukadev@linux.vnet.ibm.com 351d52f2dc4SMichael Neuling 352d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 353d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 354d52f2dc4SMichael Neuling { 355d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 356d52f2dc4SMichael Neuling } 357d52f2dc4SMichael Neuling 358d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 359d52f2dc4SMichael Neuling { 36069111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 361d52f2dc4SMichael Neuling 362d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 363d52f2dc4SMichael Neuling return; 364d52f2dc4SMichael Neuling 365d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 366d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 367d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 368d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 369d52f2dc4SMichael Neuling } 370d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 371acba3c7eSPeter Zijlstra perf_sched_cb_inc(event->ctx->pmu); 372d52f2dc4SMichael Neuling } 373d52f2dc4SMichael Neuling 374d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 375d52f2dc4SMichael Neuling { 37669111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 377d52f2dc4SMichael Neuling 378d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 379d52f2dc4SMichael Neuling return; 380d52f2dc4SMichael Neuling 381f0322f7fSAnshuman Khandual WARN_ON_ONCE(!cpuhw->bhrb_users); 382d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 383acba3c7eSPeter Zijlstra perf_sched_cb_dec(event->ctx->pmu); 384d52f2dc4SMichael Neuling 385d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 386d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 387d52f2dc4SMichael Neuling * events are active on the PMU. 388d52f2dc4SMichael Neuling */ 389d52f2dc4SMichael Neuling 390d52f2dc4SMichael Neuling /* avoid stale pointer */ 391d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 392d52f2dc4SMichael Neuling } 393d52f2dc4SMichael Neuling } 394d52f2dc4SMichael Neuling 395d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 396d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 397d52f2dc4SMichael Neuling */ 398acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 399d52f2dc4SMichael Neuling { 400acba3c7eSPeter Zijlstra if (!ppmu->bhrb_nr) 401acba3c7eSPeter Zijlstra return; 402acba3c7eSPeter Zijlstra 403acba3c7eSPeter Zijlstra if (sched_in) 404d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 405d52f2dc4SMichael Neuling } 40669123184SMichael Neuling /* Calculate the to address for a branch */ 40769123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 40869123184SMichael Neuling { 40969123184SMichael Neuling unsigned int instr; 41069123184SMichael Neuling int ret; 41169123184SMichael Neuling __u64 target; 41269123184SMichael Neuling 413f41d84ddSRavi Bangoria if (is_kernel_addr(addr)) { 414f41d84ddSRavi Bangoria if (probe_kernel_read(&instr, (void *)addr, sizeof(instr))) 415f41d84ddSRavi Bangoria return 0; 416f41d84ddSRavi Bangoria 417f41d84ddSRavi Bangoria return branch_target(&instr); 418f41d84ddSRavi Bangoria } 41969123184SMichael Neuling 42069123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 42169123184SMichael Neuling pagefault_disable(); 42269123184SMichael Neuling ret = __get_user_inatomic(instr, (unsigned int __user *)addr); 42369123184SMichael Neuling if (ret) { 42469123184SMichael Neuling pagefault_enable(); 42569123184SMichael Neuling return 0; 42669123184SMichael Neuling } 42769123184SMichael Neuling pagefault_enable(); 42869123184SMichael Neuling 42969123184SMichael Neuling target = branch_target(&instr); 43069123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 43169123184SMichael Neuling return target; 43269123184SMichael Neuling 43369123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 43469123184SMichael Neuling return target - (unsigned long)&instr + addr; 43569123184SMichael Neuling } 436d52f2dc4SMichael Neuling 437d52f2dc4SMichael Neuling /* Processing BHRB entries */ 438e51df2c1SAnton Blanchard static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 439d52f2dc4SMichael Neuling { 440d52f2dc4SMichael Neuling u64 val; 441d52f2dc4SMichael Neuling u64 addr; 442506e70d1SMichael Neuling int r_index, u_index, pred; 443d52f2dc4SMichael Neuling 444d52f2dc4SMichael Neuling r_index = 0; 445d52f2dc4SMichael Neuling u_index = 0; 446d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 447d52f2dc4SMichael Neuling /* Assembly read function */ 448506e70d1SMichael Neuling val = read_bhrb(r_index++); 449506e70d1SMichael Neuling if (!val) 450d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 451d52f2dc4SMichael Neuling break; 452506e70d1SMichael Neuling else { 453d52f2dc4SMichael Neuling addr = val & BHRB_EA; 454d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 455d52f2dc4SMichael Neuling 456506e70d1SMichael Neuling if (!addr) 457506e70d1SMichael Neuling /* invalid entry */ 458d52f2dc4SMichael Neuling continue; 459d52f2dc4SMichael Neuling 460bb19af81SMadhavan Srinivasan /* 461bb19af81SMadhavan Srinivasan * BHRB rolling buffer could very much contain the kernel 462bb19af81SMadhavan Srinivasan * addresses at this point. Check the privileges before 463bb19af81SMadhavan Srinivasan * exporting it to userspace (avoid exposure of regions 464bb19af81SMadhavan Srinivasan * where we could have speculative execution) 465bb19af81SMadhavan Srinivasan */ 466bb19af81SMadhavan Srinivasan if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) && 467bb19af81SMadhavan Srinivasan is_kernel_addr(addr)) 468bb19af81SMadhavan Srinivasan continue; 469bb19af81SMadhavan Srinivasan 470506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 471506e70d1SMichael Neuling * the most recent branch). 472506e70d1SMichael Neuling * There are two types of valid entries: 473506e70d1SMichael Neuling * 1) a target entry which is the to address of a 474506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 475506e70d1SMichael Neuling * entry read from the bhrb will be branch 476506e70d1SMichael Neuling * corresponding to this target (ie. the actual 477506e70d1SMichael Neuling * blr/bctr/btar instruction). 478506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 479506e70d1SMichael Neuling * target entry proceeds this, then this is the 480506e70d1SMichael Neuling * matching branch for that target. If this is not 481506e70d1SMichael Neuling * following a target entry, then this is a branch 482506e70d1SMichael Neuling * where the target is given as an immediate field 483506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 484506e70d1SMichael Neuling * In this case we need to read the instruction from 485506e70d1SMichael Neuling * memory to determine the target/to address. 486506e70d1SMichael Neuling */ 487d52f2dc4SMichael Neuling 488d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 489506e70d1SMichael Neuling /* Target branches use two entries 490506e70d1SMichael Neuling * (ie. computed gotos/XL form) 491506e70d1SMichael Neuling */ 492506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 493d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 494d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 495d52f2dc4SMichael Neuling 496506e70d1SMichael Neuling /* Get from address in next entry */ 497506e70d1SMichael Neuling val = read_bhrb(r_index++); 498506e70d1SMichael Neuling addr = val & BHRB_EA; 499506e70d1SMichael Neuling if (val & BHRB_TARGET) { 500506e70d1SMichael Neuling /* Shouldn't have two targets in a 501506e70d1SMichael Neuling row.. Reset index and try again */ 502506e70d1SMichael Neuling r_index--; 503506e70d1SMichael Neuling addr = 0; 504d52f2dc4SMichael Neuling } 505506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 506506e70d1SMichael Neuling } else { 507506e70d1SMichael Neuling /* Branches to immediate field 508506e70d1SMichael Neuling (ie I or B form) */ 509506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 51069123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 51169123184SMichael Neuling power_pmu_bhrb_to(addr); 512506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 513506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 514506e70d1SMichael Neuling } 515506e70d1SMichael Neuling u_index++; 516506e70d1SMichael Neuling 517d52f2dc4SMichael Neuling } 518d52f2dc4SMichael Neuling } 519d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 520d52f2dc4SMichael Neuling return; 521d52f2dc4SMichael Neuling } 522d52f2dc4SMichael Neuling 523330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) 524330a1eb7SMichael Ellerman { 525330a1eb7SMichael Ellerman /* 526330a1eb7SMichael Ellerman * This could be a per-PMU callback, but we'd rather avoid the cost. We 527330a1eb7SMichael Ellerman * check that the PMU supports EBB, meaning those that don't can still 528330a1eb7SMichael Ellerman * use bit 63 of the event code for something else if they wish. 529330a1eb7SMichael Ellerman */ 5304d9690ddSJoel Stanley return (ppmu->flags & PPMU_ARCH_207S) && 5318d7c55d0SMichael Ellerman ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 532330a1eb7SMichael Ellerman } 533330a1eb7SMichael Ellerman 534330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) 535330a1eb7SMichael Ellerman { 536330a1eb7SMichael Ellerman struct perf_event *leader = event->group_leader; 537330a1eb7SMichael Ellerman 538330a1eb7SMichael Ellerman /* Event and group leader must agree on EBB */ 539330a1eb7SMichael Ellerman if (is_ebb_event(leader) != is_ebb_event(event)) 540330a1eb7SMichael Ellerman return -EINVAL; 541330a1eb7SMichael Ellerman 542330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 543330a1eb7SMichael Ellerman if (!(event->attach_state & PERF_ATTACH_TASK)) 544330a1eb7SMichael Ellerman return -EINVAL; 545330a1eb7SMichael Ellerman 546330a1eb7SMichael Ellerman if (!leader->attr.pinned || !leader->attr.exclusive) 547330a1eb7SMichael Ellerman return -EINVAL; 548330a1eb7SMichael Ellerman 54958b5fb00SMichael Ellerman if (event->attr.freq || 55058b5fb00SMichael Ellerman event->attr.inherit || 55158b5fb00SMichael Ellerman event->attr.sample_type || 55258b5fb00SMichael Ellerman event->attr.sample_period || 55358b5fb00SMichael Ellerman event->attr.enable_on_exec) 554330a1eb7SMichael Ellerman return -EINVAL; 555330a1eb7SMichael Ellerman } 556330a1eb7SMichael Ellerman 557330a1eb7SMichael Ellerman return 0; 558330a1eb7SMichael Ellerman } 559330a1eb7SMichael Ellerman 560330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) 561330a1eb7SMichael Ellerman { 562330a1eb7SMichael Ellerman if (!is_ebb_event(event) || current->thread.used_ebb) 563330a1eb7SMichael Ellerman return; 564330a1eb7SMichael Ellerman 565330a1eb7SMichael Ellerman /* 566330a1eb7SMichael Ellerman * IFF this is the first time we've added an EBB event, set 567330a1eb7SMichael Ellerman * PMXE in the user MMCR0 so we can detect when it's cleared by 568330a1eb7SMichael Ellerman * userspace. We need this so that we can context switch while 569330a1eb7SMichael Ellerman * userspace is in the EBB handler (where PMXE is 0). 570330a1eb7SMichael Ellerman */ 571330a1eb7SMichael Ellerman current->thread.used_ebb = 1; 572330a1eb7SMichael Ellerman current->thread.mmcr0 |= MMCR0_PMXE; 573330a1eb7SMichael Ellerman } 574330a1eb7SMichael Ellerman 575330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) 576330a1eb7SMichael Ellerman { 577330a1eb7SMichael Ellerman if (!(mmcr0 & MMCR0_EBE)) 578330a1eb7SMichael Ellerman return; 579330a1eb7SMichael Ellerman 580330a1eb7SMichael Ellerman current->thread.siar = mfspr(SPRN_SIAR); 581330a1eb7SMichael Ellerman current->thread.sier = mfspr(SPRN_SIER); 582330a1eb7SMichael Ellerman current->thread.sdar = mfspr(SPRN_SDAR); 583330a1eb7SMichael Ellerman current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 584330a1eb7SMichael Ellerman current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 585330a1eb7SMichael Ellerman } 586330a1eb7SMichael Ellerman 5879de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 588330a1eb7SMichael Ellerman { 5899de5cb0fSMichael Ellerman unsigned long mmcr0 = cpuhw->mmcr[0]; 5909de5cb0fSMichael Ellerman 591330a1eb7SMichael Ellerman if (!ebb) 592330a1eb7SMichael Ellerman goto out; 593330a1eb7SMichael Ellerman 59476cb8a78SMichael Ellerman /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 59576cb8a78SMichael Ellerman mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 596330a1eb7SMichael Ellerman 597c2e37a26SMichael Ellerman /* 598c2e37a26SMichael Ellerman * Add any bits from the user MMCR0, FC or PMAO. This is compatible 599c2e37a26SMichael Ellerman * with pmao_restore_workaround() because we may add PMAO but we never 600c2e37a26SMichael Ellerman * clear it here. 601c2e37a26SMichael Ellerman */ 602330a1eb7SMichael Ellerman mmcr0 |= current->thread.mmcr0; 603330a1eb7SMichael Ellerman 604c2e37a26SMichael Ellerman /* 605c2e37a26SMichael Ellerman * Be careful not to set PMXE if userspace had it cleared. This is also 606c2e37a26SMichael Ellerman * compatible with pmao_restore_workaround() because it has already 607c2e37a26SMichael Ellerman * cleared PMXE and we leave PMAO alone. 608c2e37a26SMichael Ellerman */ 609330a1eb7SMichael Ellerman if (!(current->thread.mmcr0 & MMCR0_PMXE)) 610330a1eb7SMichael Ellerman mmcr0 &= ~MMCR0_PMXE; 611330a1eb7SMichael Ellerman 612330a1eb7SMichael Ellerman mtspr(SPRN_SIAR, current->thread.siar); 613330a1eb7SMichael Ellerman mtspr(SPRN_SIER, current->thread.sier); 614330a1eb7SMichael Ellerman mtspr(SPRN_SDAR, current->thread.sdar); 6159de5cb0fSMichael Ellerman 6169de5cb0fSMichael Ellerman /* 6179de5cb0fSMichael Ellerman * Merge the kernel & user values of MMCR2. The semantics we implement 6189de5cb0fSMichael Ellerman * are that the user MMCR2 can set bits, ie. cause counters to freeze, 6199de5cb0fSMichael Ellerman * but not clear bits. If a task wants to be able to clear bits, ie. 6209de5cb0fSMichael Ellerman * unfreeze counters, it should not set exclude_xxx in its events and 6219de5cb0fSMichael Ellerman * instead manage the MMCR2 entirely by itself. 6229de5cb0fSMichael Ellerman */ 6239de5cb0fSMichael Ellerman mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); 624330a1eb7SMichael Ellerman out: 625330a1eb7SMichael Ellerman return mmcr0; 626330a1eb7SMichael Ellerman } 627c2e37a26SMichael Ellerman 628c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) 629c2e37a26SMichael Ellerman { 630c2e37a26SMichael Ellerman unsigned pmcs[6]; 631c2e37a26SMichael Ellerman 632c2e37a26SMichael Ellerman if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 633c2e37a26SMichael Ellerman return; 634c2e37a26SMichael Ellerman 635c2e37a26SMichael Ellerman /* 636c2e37a26SMichael Ellerman * On POWER8E there is a hardware defect which affects the PMU context 637c2e37a26SMichael Ellerman * switch logic, ie. power_pmu_disable/enable(). 638c2e37a26SMichael Ellerman * 639c2e37a26SMichael Ellerman * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 640c2e37a26SMichael Ellerman * by the hardware. Sometime later the actual PMU exception is 641c2e37a26SMichael Ellerman * delivered. 642c2e37a26SMichael Ellerman * 643c2e37a26SMichael Ellerman * If we context switch, or simply disable/enable, the PMU prior to the 644c2e37a26SMichael Ellerman * exception arriving, the exception will be lost when we clear PMAO. 645c2e37a26SMichael Ellerman * 646c2e37a26SMichael Ellerman * When we reenable the PMU, we will write the saved MMCR0 with PMAO 647c2e37a26SMichael Ellerman * set, and this _should_ generate an exception. However because of the 648c2e37a26SMichael Ellerman * defect no exception is generated when we write PMAO, and we get 649c2e37a26SMichael Ellerman * stuck with no counters counting but no exception delivered. 650c2e37a26SMichael Ellerman * 651c2e37a26SMichael Ellerman * The workaround is to detect this case and tweak the hardware to 652c2e37a26SMichael Ellerman * create another pending PMU exception. 653c2e37a26SMichael Ellerman * 654c2e37a26SMichael Ellerman * We do that by setting up PMC6 (cycles) for an imminent overflow and 655c2e37a26SMichael Ellerman * enabling the PMU. That causes a new exception to be generated in the 656c2e37a26SMichael Ellerman * chip, but we don't take it yet because we have interrupts hard 657c2e37a26SMichael Ellerman * disabled. We then write back the PMU state as we want it to be seen 658c2e37a26SMichael Ellerman * by the exception handler. When we reenable interrupts the exception 659c2e37a26SMichael Ellerman * handler will be called and see the correct state. 660c2e37a26SMichael Ellerman * 661c2e37a26SMichael Ellerman * The logic is the same for EBB, except that the exception is gated by 662c2e37a26SMichael Ellerman * us having interrupts hard disabled as well as the fact that we are 663c2e37a26SMichael Ellerman * not in userspace. The exception is finally delivered when we return 664c2e37a26SMichael Ellerman * to userspace. 665c2e37a26SMichael Ellerman */ 666c2e37a26SMichael Ellerman 667c2e37a26SMichael Ellerman /* Only if PMAO is set and PMAO_SYNC is clear */ 668c2e37a26SMichael Ellerman if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 669c2e37a26SMichael Ellerman return; 670c2e37a26SMichael Ellerman 671c2e37a26SMichael Ellerman /* If we're doing EBB, only if BESCR[GE] is set */ 672c2e37a26SMichael Ellerman if (ebb && !(current->thread.bescr & BESCR_GE)) 673c2e37a26SMichael Ellerman return; 674c2e37a26SMichael Ellerman 675c2e37a26SMichael Ellerman /* 676c2e37a26SMichael Ellerman * We are already soft-disabled in power_pmu_enable(). We need to hard 67758bffb5bSMadhavan Srinivasan * disable to actually prevent the PMU exception from firing. 678c2e37a26SMichael Ellerman */ 679c2e37a26SMichael Ellerman hard_irq_disable(); 680c2e37a26SMichael Ellerman 681c2e37a26SMichael Ellerman /* 682c2e37a26SMichael Ellerman * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 683c2e37a26SMichael Ellerman * Using read/write_pmc() in a for loop adds 12 function calls and 684c2e37a26SMichael Ellerman * almost doubles our code size. 685c2e37a26SMichael Ellerman */ 686c2e37a26SMichael Ellerman pmcs[0] = mfspr(SPRN_PMC1); 687c2e37a26SMichael Ellerman pmcs[1] = mfspr(SPRN_PMC2); 688c2e37a26SMichael Ellerman pmcs[2] = mfspr(SPRN_PMC3); 689c2e37a26SMichael Ellerman pmcs[3] = mfspr(SPRN_PMC4); 690c2e37a26SMichael Ellerman pmcs[4] = mfspr(SPRN_PMC5); 691c2e37a26SMichael Ellerman pmcs[5] = mfspr(SPRN_PMC6); 692c2e37a26SMichael Ellerman 693c2e37a26SMichael Ellerman /* Ensure all freeze bits are unset */ 694c2e37a26SMichael Ellerman mtspr(SPRN_MMCR2, 0); 695c2e37a26SMichael Ellerman 696c2e37a26SMichael Ellerman /* Set up PMC6 to overflow in one cycle */ 697c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, 0x7FFFFFFE); 698c2e37a26SMichael Ellerman 699c2e37a26SMichael Ellerman /* Enable exceptions and unfreeze PMC6 */ 700c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 701c2e37a26SMichael Ellerman 702c2e37a26SMichael Ellerman /* Now we need to refreeze and restore the PMCs */ 703c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 704c2e37a26SMichael Ellerman 705c2e37a26SMichael Ellerman mtspr(SPRN_PMC1, pmcs[0]); 706c2e37a26SMichael Ellerman mtspr(SPRN_PMC2, pmcs[1]); 707c2e37a26SMichael Ellerman mtspr(SPRN_PMC3, pmcs[2]); 708c2e37a26SMichael Ellerman mtspr(SPRN_PMC4, pmcs[3]); 709c2e37a26SMichael Ellerman mtspr(SPRN_PMC5, pmcs[4]); 710c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, pmcs[5]); 711c2e37a26SMichael Ellerman } 712356d8ce3SMadhavan Srinivasan 713356d8ce3SMadhavan Srinivasan static bool use_ic(u64 event) 714356d8ce3SMadhavan Srinivasan { 715356d8ce3SMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_POWER9_DD1) && 716356d8ce3SMadhavan Srinivasan (event == 0x200f2 || event == 0x300f2)) 717356d8ce3SMadhavan Srinivasan return true; 718356d8ce3SMadhavan Srinivasan 719356d8ce3SMadhavan Srinivasan return false; 720356d8ce3SMadhavan Srinivasan } 721f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 722f2699491SMichael Ellerman 723f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 724f2699491SMichael Ellerman 725f2699491SMichael Ellerman /* 726f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 727f2699491SMichael Ellerman */ 728f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 729f2699491SMichael Ellerman { 730f2699491SMichael Ellerman unsigned long val; 731f2699491SMichael Ellerman 732f2699491SMichael Ellerman switch (idx) { 733f2699491SMichael Ellerman case 1: 734f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 735f2699491SMichael Ellerman break; 736f2699491SMichael Ellerman case 2: 737f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 738f2699491SMichael Ellerman break; 739f2699491SMichael Ellerman case 3: 740f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 741f2699491SMichael Ellerman break; 742f2699491SMichael Ellerman case 4: 743f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 744f2699491SMichael Ellerman break; 745f2699491SMichael Ellerman case 5: 746f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 747f2699491SMichael Ellerman break; 748f2699491SMichael Ellerman case 6: 749f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 750f2699491SMichael Ellerman break; 751f2699491SMichael Ellerman #ifdef CONFIG_PPC64 752f2699491SMichael Ellerman case 7: 753f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 754f2699491SMichael Ellerman break; 755f2699491SMichael Ellerman case 8: 756f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 757f2699491SMichael Ellerman break; 758f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 759f2699491SMichael Ellerman default: 760f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 761f2699491SMichael Ellerman val = 0; 762f2699491SMichael Ellerman } 763f2699491SMichael Ellerman return val; 764f2699491SMichael Ellerman } 765f2699491SMichael Ellerman 766f2699491SMichael Ellerman /* 767f2699491SMichael Ellerman * Write one PMC. 768f2699491SMichael Ellerman */ 769f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 770f2699491SMichael Ellerman { 771f2699491SMichael Ellerman switch (idx) { 772f2699491SMichael Ellerman case 1: 773f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 774f2699491SMichael Ellerman break; 775f2699491SMichael Ellerman case 2: 776f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 777f2699491SMichael Ellerman break; 778f2699491SMichael Ellerman case 3: 779f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 780f2699491SMichael Ellerman break; 781f2699491SMichael Ellerman case 4: 782f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 783f2699491SMichael Ellerman break; 784f2699491SMichael Ellerman case 5: 785f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 786f2699491SMichael Ellerman break; 787f2699491SMichael Ellerman case 6: 788f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 789f2699491SMichael Ellerman break; 790f2699491SMichael Ellerman #ifdef CONFIG_PPC64 791f2699491SMichael Ellerman case 7: 792f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 793f2699491SMichael Ellerman break; 794f2699491SMichael Ellerman case 8: 795f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 796f2699491SMichael Ellerman break; 797f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 798f2699491SMichael Ellerman default: 799f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 800f2699491SMichael Ellerman } 801f2699491SMichael Ellerman } 802f2699491SMichael Ellerman 8035f6d0380SAnshuman Khandual /* Called from sysrq_handle_showregs() */ 8045f6d0380SAnshuman Khandual void perf_event_print_debug(void) 8055f6d0380SAnshuman Khandual { 8065f6d0380SAnshuman Khandual unsigned long sdar, sier, flags; 8075f6d0380SAnshuman Khandual u32 pmcs[MAX_HWEVENTS]; 8085f6d0380SAnshuman Khandual int i; 8095f6d0380SAnshuman Khandual 8104917fcb5SRavi Bangoria if (!ppmu) { 8114917fcb5SRavi Bangoria pr_info("Performance monitor hardware not registered.\n"); 8124917fcb5SRavi Bangoria return; 8134917fcb5SRavi Bangoria } 8144917fcb5SRavi Bangoria 8155f6d0380SAnshuman Khandual if (!ppmu->n_counter) 8165f6d0380SAnshuman Khandual return; 8175f6d0380SAnshuman Khandual 8185f6d0380SAnshuman Khandual local_irq_save(flags); 8195f6d0380SAnshuman Khandual 8205f6d0380SAnshuman Khandual pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 8215f6d0380SAnshuman Khandual smp_processor_id(), ppmu->name, ppmu->n_counter); 8225f6d0380SAnshuman Khandual 8235f6d0380SAnshuman Khandual for (i = 0; i < ppmu->n_counter; i++) 8245f6d0380SAnshuman Khandual pmcs[i] = read_pmc(i + 1); 8255f6d0380SAnshuman Khandual 8265f6d0380SAnshuman Khandual for (; i < MAX_HWEVENTS; i++) 8275f6d0380SAnshuman Khandual pmcs[i] = 0xdeadbeef; 8285f6d0380SAnshuman Khandual 8295f6d0380SAnshuman Khandual pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 8305f6d0380SAnshuman Khandual pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 8315f6d0380SAnshuman Khandual 8325f6d0380SAnshuman Khandual if (ppmu->n_counter > 4) 8335f6d0380SAnshuman Khandual pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 8345f6d0380SAnshuman Khandual pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 8355f6d0380SAnshuman Khandual 8365f6d0380SAnshuman Khandual pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 8375f6d0380SAnshuman Khandual mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 8385f6d0380SAnshuman Khandual 8395f6d0380SAnshuman Khandual sdar = sier = 0; 8405f6d0380SAnshuman Khandual #ifdef CONFIG_PPC64 8415f6d0380SAnshuman Khandual sdar = mfspr(SPRN_SDAR); 8425f6d0380SAnshuman Khandual 8435f6d0380SAnshuman Khandual if (ppmu->flags & PPMU_HAS_SIER) 8445f6d0380SAnshuman Khandual sier = mfspr(SPRN_SIER); 8455f6d0380SAnshuman Khandual 8464d9690ddSJoel Stanley if (ppmu->flags & PPMU_ARCH_207S) { 8475f6d0380SAnshuman Khandual pr_info("MMCR2: %016lx EBBHR: %016lx\n", 8485f6d0380SAnshuman Khandual mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 8495f6d0380SAnshuman Khandual pr_info("EBBRR: %016lx BESCR: %016lx\n", 8505f6d0380SAnshuman Khandual mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 8515f6d0380SAnshuman Khandual } 8525f6d0380SAnshuman Khandual #endif 8535f6d0380SAnshuman Khandual pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 8545f6d0380SAnshuman Khandual mfspr(SPRN_SIAR), sdar, sier); 8555f6d0380SAnshuman Khandual 8565f6d0380SAnshuman Khandual local_irq_restore(flags); 8575f6d0380SAnshuman Khandual } 8585f6d0380SAnshuman Khandual 859f2699491SMichael Ellerman /* 860f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 861f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 862f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 863f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 864f2699491SMichael Ellerman */ 865f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 866f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 867f2699491SMichael Ellerman int n_ev) 868f2699491SMichael Ellerman { 869f2699491SMichael Ellerman unsigned long mask, value, nv; 870f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 871f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 872f2699491SMichael Ellerman int i, j; 873f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 874f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 875f2699491SMichael Ellerman 876f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 877f2699491SMichael Ellerman return -1; 878f2699491SMichael Ellerman 879f2699491SMichael Ellerman /* First see if the events will go on as-is */ 880f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 881f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 882f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 883f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 884f2699491SMichael Ellerman cpuhw->alternatives[i]); 885f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 886f2699491SMichael Ellerman } 887f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 888f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 889f2699491SMichael Ellerman return -1; 890f2699491SMichael Ellerman } 891f2699491SMichael Ellerman value = mask = 0; 892f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 893f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 894f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 895f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) != 0 || 896f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][0]) & 897f2699491SMichael Ellerman cpuhw->amasks[i][0]) != 0) 898f2699491SMichael Ellerman break; 899f2699491SMichael Ellerman value = nv; 900f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 901f2699491SMichael Ellerman } 902f2699491SMichael Ellerman if (i == n_ev) 903f2699491SMichael Ellerman return 0; /* all OK */ 904f2699491SMichael Ellerman 905f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 906f2699491SMichael Ellerman if (!ppmu->get_alternatives) 907f2699491SMichael Ellerman return -1; 908f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 909f2699491SMichael Ellerman choice[i] = 0; 910f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 911f2699491SMichael Ellerman cpuhw->alternatives[i]); 912f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 913f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 914f2699491SMichael Ellerman &cpuhw->amasks[i][j], 915f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 916f2699491SMichael Ellerman } 917f2699491SMichael Ellerman 918f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 919f2699491SMichael Ellerman i = 0; 920f2699491SMichael Ellerman j = -1; 921f2699491SMichael Ellerman value = mask = nv = 0; 922f2699491SMichael Ellerman while (i < n_ev) { 923f2699491SMichael Ellerman if (j >= 0) { 924f2699491SMichael Ellerman /* we're backtracking, restore context */ 925f2699491SMichael Ellerman value = svalues[i]; 926f2699491SMichael Ellerman mask = smasks[i]; 927f2699491SMichael Ellerman j = choice[i]; 928f2699491SMichael Ellerman } 929f2699491SMichael Ellerman /* 930f2699491SMichael Ellerman * See if any alternative k for event_id i, 931f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 932f2699491SMichael Ellerman */ 933f2699491SMichael Ellerman while (++j < n_alt[i]) { 934f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 935f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 936f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 937f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 938f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 939f2699491SMichael Ellerman break; 940f2699491SMichael Ellerman } 941f2699491SMichael Ellerman if (j >= n_alt[i]) { 942f2699491SMichael Ellerman /* 943f2699491SMichael Ellerman * No feasible alternative, backtrack 944f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 945f2699491SMichael Ellerman * alternatives from where we got up to. 946f2699491SMichael Ellerman */ 947f2699491SMichael Ellerman if (--i < 0) 948f2699491SMichael Ellerman return -1; 949f2699491SMichael Ellerman } else { 950f2699491SMichael Ellerman /* 951f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 952f2699491SMichael Ellerman * remember where we got up to with this event_id, 953f2699491SMichael Ellerman * go on to the next event_id, and start with 954f2699491SMichael Ellerman * the first alternative for it. 955f2699491SMichael Ellerman */ 956f2699491SMichael Ellerman choice[i] = j; 957f2699491SMichael Ellerman svalues[i] = value; 958f2699491SMichael Ellerman smasks[i] = mask; 959f2699491SMichael Ellerman value = nv; 960f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 961f2699491SMichael Ellerman ++i; 962f2699491SMichael Ellerman j = -1; 963f2699491SMichael Ellerman } 964f2699491SMichael Ellerman } 965f2699491SMichael Ellerman 966f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 967f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 968f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 969f2699491SMichael Ellerman return 0; 970f2699491SMichael Ellerman } 971f2699491SMichael Ellerman 972f2699491SMichael Ellerman /* 973f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 974f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 975f2699491SMichael Ellerman * added events. 976f2699491SMichael Ellerman */ 977f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 978f2699491SMichael Ellerman int n_prev, int n_new) 979f2699491SMichael Ellerman { 980f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 981f2699491SMichael Ellerman int i, n, first; 982f2699491SMichael Ellerman struct perf_event *event; 983f2699491SMichael Ellerman 9849de5cb0fSMichael Ellerman /* 9859de5cb0fSMichael Ellerman * If the PMU we're on supports per event exclude settings then we 9869de5cb0fSMichael Ellerman * don't need to do any of this logic. NB. This assumes no PMU has both 9879de5cb0fSMichael Ellerman * per event exclude and limited PMCs. 9889de5cb0fSMichael Ellerman */ 9899de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 9909de5cb0fSMichael Ellerman return 0; 9919de5cb0fSMichael Ellerman 992f2699491SMichael Ellerman n = n_prev + n_new; 993f2699491SMichael Ellerman if (n <= 1) 994f2699491SMichael Ellerman return 0; 995f2699491SMichael Ellerman 996f2699491SMichael Ellerman first = 1; 997f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 998f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 999f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 1000f2699491SMichael Ellerman continue; 1001f2699491SMichael Ellerman } 1002f2699491SMichael Ellerman event = ctrs[i]; 1003f2699491SMichael Ellerman if (first) { 1004f2699491SMichael Ellerman eu = event->attr.exclude_user; 1005f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 1006f2699491SMichael Ellerman eh = event->attr.exclude_hv; 1007f2699491SMichael Ellerman first = 0; 1008f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 1009f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 1010f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 1011f2699491SMichael Ellerman return -EAGAIN; 1012f2699491SMichael Ellerman } 1013f2699491SMichael Ellerman } 1014f2699491SMichael Ellerman 1015f2699491SMichael Ellerman if (eu || ek || eh) 1016f2699491SMichael Ellerman for (i = 0; i < n; ++i) 1017f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 1018f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 1019f2699491SMichael Ellerman 1020f2699491SMichael Ellerman return 0; 1021f2699491SMichael Ellerman } 1022f2699491SMichael Ellerman 1023f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 1024f2699491SMichael Ellerman { 1025f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 1026f2699491SMichael Ellerman 1027f2699491SMichael Ellerman /* 1028f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 1029f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 1030f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 1031f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 1032027dfac6SMichael Ellerman * number of events to rollback at once. If we detect a rollback 1033f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 1034f2699491SMichael Ellerman * counters. 1035f2699491SMichael Ellerman */ 1036f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 1037f2699491SMichael Ellerman delta = 0; 1038f2699491SMichael Ellerman 1039f2699491SMichael Ellerman return delta; 1040f2699491SMichael Ellerman } 1041f2699491SMichael Ellerman 1042f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 1043f2699491SMichael Ellerman { 1044f2699491SMichael Ellerman s64 val, delta, prev; 1045356d8ce3SMadhavan Srinivasan struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1046f2699491SMichael Ellerman 1047f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1048f2699491SMichael Ellerman return; 1049f2699491SMichael Ellerman 1050f2699491SMichael Ellerman if (!event->hw.idx) 1051f2699491SMichael Ellerman return; 1052330a1eb7SMichael Ellerman 1053330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 1054330a1eb7SMichael Ellerman val = read_pmc(event->hw.idx); 1055356d8ce3SMadhavan Srinivasan if (use_ic(event->attr.config)) { 1056356d8ce3SMadhavan Srinivasan val = mfspr(SPRN_IC); 1057356d8ce3SMadhavan Srinivasan if (val > cpuhw->ic_init) 1058356d8ce3SMadhavan Srinivasan val = val - cpuhw->ic_init; 1059356d8ce3SMadhavan Srinivasan else 1060356d8ce3SMadhavan Srinivasan val = val + (0 - cpuhw->ic_init); 1061356d8ce3SMadhavan Srinivasan } 1062330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, val); 1063330a1eb7SMichael Ellerman return; 1064330a1eb7SMichael Ellerman } 1065330a1eb7SMichael Ellerman 1066f2699491SMichael Ellerman /* 1067f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 1068f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 1069f2699491SMichael Ellerman * Therefore we treat them like NMIs. 1070f2699491SMichael Ellerman */ 1071f2699491SMichael Ellerman do { 1072f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1073f2699491SMichael Ellerman barrier(); 1074f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 1075356d8ce3SMadhavan Srinivasan if (use_ic(event->attr.config)) { 1076356d8ce3SMadhavan Srinivasan val = mfspr(SPRN_IC); 1077356d8ce3SMadhavan Srinivasan if (val > cpuhw->ic_init) 1078356d8ce3SMadhavan Srinivasan val = val - cpuhw->ic_init; 1079356d8ce3SMadhavan Srinivasan else 1080356d8ce3SMadhavan Srinivasan val = val + (0 - cpuhw->ic_init); 1081356d8ce3SMadhavan Srinivasan } 1082f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1083f2699491SMichael Ellerman if (!delta) 1084f2699491SMichael Ellerman return; 1085f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1086f2699491SMichael Ellerman 1087f2699491SMichael Ellerman local64_add(delta, &event->count); 1088f5602941SAnton Blanchard 1089f5602941SAnton Blanchard /* 1090f5602941SAnton Blanchard * A number of places program the PMC with (0x80000000 - period_left). 1091f5602941SAnton Blanchard * We never want period_left to be less than 1 because we will program 1092f5602941SAnton Blanchard * the PMC with a value >= 0x800000000 and an edge detected PMC will 1093f5602941SAnton Blanchard * roll around to 0 before taking an exception. We have seen this 1094f5602941SAnton Blanchard * on POWER8. 1095f5602941SAnton Blanchard * 1096f5602941SAnton Blanchard * To fix this, clamp the minimum value of period_left to 1. 1097f5602941SAnton Blanchard */ 1098f5602941SAnton Blanchard do { 1099f5602941SAnton Blanchard prev = local64_read(&event->hw.period_left); 1100f5602941SAnton Blanchard val = prev - delta; 1101f5602941SAnton Blanchard if (val < 1) 1102f5602941SAnton Blanchard val = 1; 1103f5602941SAnton Blanchard } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1104f2699491SMichael Ellerman } 1105f2699491SMichael Ellerman 1106f2699491SMichael Ellerman /* 1107f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 1108f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 1109f2699491SMichael Ellerman * us if `event' is using such a PMC. 1110f2699491SMichael Ellerman */ 1111f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 1112f2699491SMichael Ellerman { 1113f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1114f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 1115f2699491SMichael Ellerman } 1116f2699491SMichael Ellerman 1117f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1118f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1119f2699491SMichael Ellerman { 1120f2699491SMichael Ellerman struct perf_event *event; 1121f2699491SMichael Ellerman u64 val, prev, delta; 1122f2699491SMichael Ellerman int i; 1123f2699491SMichael Ellerman 1124f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1125f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1126f2699491SMichael Ellerman if (!event->hw.idx) 1127f2699491SMichael Ellerman continue; 1128f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1129f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1130f2699491SMichael Ellerman event->hw.idx = 0; 1131f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1132f2699491SMichael Ellerman if (delta) 1133f2699491SMichael Ellerman local64_add(delta, &event->count); 1134f2699491SMichael Ellerman } 1135f2699491SMichael Ellerman } 1136f2699491SMichael Ellerman 1137f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1138f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1139f2699491SMichael Ellerman { 1140f2699491SMichael Ellerman struct perf_event *event; 1141f2699491SMichael Ellerman u64 val, prev; 1142f2699491SMichael Ellerman int i; 1143f2699491SMichael Ellerman 1144f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1145f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1146f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 1147f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1148f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1149f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 1150f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1151f2699491SMichael Ellerman perf_event_update_userpage(event); 1152f2699491SMichael Ellerman } 1153f2699491SMichael Ellerman } 1154f2699491SMichael Ellerman 1155f2699491SMichael Ellerman /* 1156f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 1157f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 1158f2699491SMichael Ellerman * other events. We try to keep the values from the limited 1159f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 1160f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 1161f2699491SMichael Ellerman * the limited events as small and consistent as possible. 1162f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 1163f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 1164f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 1165f2699491SMichael Ellerman */ 1166f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1167f2699491SMichael Ellerman { 1168f2699491SMichael Ellerman unsigned long pmc5, pmc6; 1169f2699491SMichael Ellerman 1170f2699491SMichael Ellerman if (!cpuhw->n_limited) { 1171f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1172f2699491SMichael Ellerman return; 1173f2699491SMichael Ellerman } 1174f2699491SMichael Ellerman 1175f2699491SMichael Ellerman /* 1176f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 1177f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 1178f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 1179f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 1180f2699491SMichael Ellerman * interrupt enable bits turned off. 1181f2699491SMichael Ellerman */ 1182f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1183f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 1184f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1185f2699491SMichael Ellerman "i" (SPRN_MMCR0), 1186f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1187f2699491SMichael Ellerman 1188f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 1189f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 1190f2699491SMichael Ellerman else 1191f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 1192f2699491SMichael Ellerman 1193f2699491SMichael Ellerman /* 1194f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 1195f2699491SMichael Ellerman * enable bits, if necessary. 1196f2699491SMichael Ellerman */ 1197f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1198f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1199f2699491SMichael Ellerman } 1200f2699491SMichael Ellerman 1201f2699491SMichael Ellerman /* 1202f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 1203f2699491SMichael Ellerman * events to be added or removed. 1204f2699491SMichael Ellerman */ 1205f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 1206f2699491SMichael Ellerman { 1207f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1208330a1eb7SMichael Ellerman unsigned long flags, mmcr0, val; 1209f2699491SMichael Ellerman 1210f2699491SMichael Ellerman if (!ppmu) 1211f2699491SMichael Ellerman return; 1212f2699491SMichael Ellerman local_irq_save(flags); 121369111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1214f2699491SMichael Ellerman 1215f2699491SMichael Ellerman if (!cpuhw->disabled) { 1216f2699491SMichael Ellerman /* 1217f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 1218f2699491SMichael Ellerman */ 1219f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 1220f2699491SMichael Ellerman ppc_enable_pmcs(); 1221f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 1222f2699491SMichael Ellerman } 1223f2699491SMichael Ellerman 1224f2699491SMichael Ellerman /* 122576cb8a78SMichael Ellerman * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1226378a6ee9SMichael Ellerman */ 1227330a1eb7SMichael Ellerman val = mmcr0 = mfspr(SPRN_MMCR0); 1228378a6ee9SMichael Ellerman val |= MMCR0_FC; 122976cb8a78SMichael Ellerman val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 123076cb8a78SMichael Ellerman MMCR0_FC56); 1231378a6ee9SMichael Ellerman 1232378a6ee9SMichael Ellerman /* 1233378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 1234378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 1235378a6ee9SMichael Ellerman * before we return. 1236378a6ee9SMichael Ellerman */ 1237378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 1238378a6ee9SMichael Ellerman mb(); 1239e1ebd0e5SMichael Ellerman isync(); 1240378a6ee9SMichael Ellerman 1241378a6ee9SMichael Ellerman /* 1242f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 1243f2699491SMichael Ellerman */ 1244f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1245f2699491SMichael Ellerman mtspr(SPRN_MMCRA, 1246f2699491SMichael Ellerman cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1247f2699491SMichael Ellerman mb(); 1248e1ebd0e5SMichael Ellerman isync(); 1249f2699491SMichael Ellerman } 1250f2699491SMichael Ellerman 1251378a6ee9SMichael Ellerman cpuhw->disabled = 1; 1252378a6ee9SMichael Ellerman cpuhw->n_added = 0; 1253330a1eb7SMichael Ellerman 1254330a1eb7SMichael Ellerman ebb_switch_out(mmcr0); 1255e1ebd0e5SMichael Ellerman 1256e1ebd0e5SMichael Ellerman #ifdef CONFIG_PPC64 1257e1ebd0e5SMichael Ellerman /* 1258e1ebd0e5SMichael Ellerman * These are readable by userspace, may contain kernel 1259e1ebd0e5SMichael Ellerman * addresses and are not switched by context switch, so clear 1260e1ebd0e5SMichael Ellerman * them now to avoid leaking anything to userspace in general 1261e1ebd0e5SMichael Ellerman * including to another process. 1262e1ebd0e5SMichael Ellerman */ 1263e1ebd0e5SMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) { 1264e1ebd0e5SMichael Ellerman mtspr(SPRN_SDAR, 0); 1265e1ebd0e5SMichael Ellerman mtspr(SPRN_SIAR, 0); 1266e1ebd0e5SMichael Ellerman } 1267e1ebd0e5SMichael Ellerman #endif 1268f2699491SMichael Ellerman } 1269330a1eb7SMichael Ellerman 1270f2699491SMichael Ellerman local_irq_restore(flags); 1271f2699491SMichael Ellerman } 1272f2699491SMichael Ellerman 1273f2699491SMichael Ellerman /* 1274f2699491SMichael Ellerman * Re-enable all events if disable == 0. 1275f2699491SMichael Ellerman * If we were previously disabled and events were added, then 1276f2699491SMichael Ellerman * put the new config on the PMU. 1277f2699491SMichael Ellerman */ 1278f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 1279f2699491SMichael Ellerman { 1280f2699491SMichael Ellerman struct perf_event *event; 1281f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1282f2699491SMichael Ellerman unsigned long flags; 1283f2699491SMichael Ellerman long i; 1284330a1eb7SMichael Ellerman unsigned long val, mmcr0; 1285f2699491SMichael Ellerman s64 left; 1286f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 1287f2699491SMichael Ellerman int n_lim; 1288f2699491SMichael Ellerman int idx; 1289330a1eb7SMichael Ellerman bool ebb; 1290f2699491SMichael Ellerman 1291f2699491SMichael Ellerman if (!ppmu) 1292f2699491SMichael Ellerman return; 1293f2699491SMichael Ellerman local_irq_save(flags); 12940a48843dSMichael Ellerman 129569111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 12960a48843dSMichael Ellerman if (!cpuhw->disabled) 12970a48843dSMichael Ellerman goto out; 12980a48843dSMichael Ellerman 12994ea355b5SMichael Ellerman if (cpuhw->n_events == 0) { 13004ea355b5SMichael Ellerman ppc_set_pmu_inuse(0); 13014ea355b5SMichael Ellerman goto out; 13024ea355b5SMichael Ellerman } 13034ea355b5SMichael Ellerman 1304f2699491SMichael Ellerman cpuhw->disabled = 0; 1305f2699491SMichael Ellerman 1306f2699491SMichael Ellerman /* 1307330a1eb7SMichael Ellerman * EBB requires an exclusive group and all events must have the EBB 1308330a1eb7SMichael Ellerman * flag set, or not set, so we can just check a single event. Also we 1309330a1eb7SMichael Ellerman * know we have at least one event. 1310330a1eb7SMichael Ellerman */ 1311330a1eb7SMichael Ellerman ebb = is_ebb_event(cpuhw->event[0]); 1312330a1eb7SMichael Ellerman 1313330a1eb7SMichael Ellerman /* 1314f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 1315f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 1316f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 1317f2699491SMichael Ellerman * (possibly updated for removal of events). 1318f2699491SMichael Ellerman */ 1319f2699491SMichael Ellerman if (!cpuhw->n_added) { 1320f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1321f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1322f2699491SMichael Ellerman goto out_enable; 1323f2699491SMichael Ellerman } 1324f2699491SMichael Ellerman 1325f2699491SMichael Ellerman /* 132679a4cb28SMichael Ellerman * Clear all MMCR settings and recompute them for the new set of events. 1327f2699491SMichael Ellerman */ 132879a4cb28SMichael Ellerman memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 132979a4cb28SMichael Ellerman 1330f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 13318abd818fSMichael Ellerman cpuhw->mmcr, cpuhw->event)) { 1332f2699491SMichael Ellerman /* shouldn't ever get here */ 1333f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 1334f2699491SMichael Ellerman goto out; 1335f2699491SMichael Ellerman } 1336f2699491SMichael Ellerman 13379de5cb0fSMichael Ellerman if (!(ppmu->flags & PPMU_ARCH_207S)) { 1338f2699491SMichael Ellerman /* 13399de5cb0fSMichael Ellerman * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 13409de5cb0fSMichael Ellerman * bits for the first event. We have already checked that all 13419de5cb0fSMichael Ellerman * events have the same value for these bits as the first event. 1342f2699491SMichael Ellerman */ 1343f2699491SMichael Ellerman event = cpuhw->event[0]; 1344f2699491SMichael Ellerman if (event->attr.exclude_user) 1345f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCP; 1346f2699491SMichael Ellerman if (event->attr.exclude_kernel) 1347f2699491SMichael Ellerman cpuhw->mmcr[0] |= freeze_events_kernel; 1348f2699491SMichael Ellerman if (event->attr.exclude_hv) 1349f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCHV; 13509de5cb0fSMichael Ellerman } 1351f2699491SMichael Ellerman 1352f2699491SMichael Ellerman /* 1353f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 1354f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 1355f2699491SMichael Ellerman * Then unfreeze the events. 1356f2699491SMichael Ellerman */ 1357f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 1358f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1359f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1360f2699491SMichael Ellerman mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1361f2699491SMichael Ellerman | MMCR0_FC); 13629de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 13639de5cb0fSMichael Ellerman mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); 1364f2699491SMichael Ellerman 1365f2699491SMichael Ellerman /* 1366f2699491SMichael Ellerman * Read off any pre-existing events that need to move 1367f2699491SMichael Ellerman * to another PMC. 1368f2699491SMichael Ellerman */ 1369f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1370f2699491SMichael Ellerman event = cpuhw->event[i]; 1371f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1372f2699491SMichael Ellerman power_pmu_read(event); 1373f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1374f2699491SMichael Ellerman event->hw.idx = 0; 1375f2699491SMichael Ellerman } 1376f2699491SMichael Ellerman } 1377f2699491SMichael Ellerman 1378f2699491SMichael Ellerman /* 1379f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 1380f2699491SMichael Ellerman */ 1381f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 1382f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1383f2699491SMichael Ellerman event = cpuhw->event[i]; 1384f2699491SMichael Ellerman if (event->hw.idx) 1385f2699491SMichael Ellerman continue; 1386f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1387f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1388f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1389f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1390f2699491SMichael Ellerman ++n_lim; 1391f2699491SMichael Ellerman continue; 1392f2699491SMichael Ellerman } 1393330a1eb7SMichael Ellerman 1394330a1eb7SMichael Ellerman if (ebb) 1395330a1eb7SMichael Ellerman val = local64_read(&event->hw.prev_count); 1396330a1eb7SMichael Ellerman else { 1397f2699491SMichael Ellerman val = 0; 1398f2699491SMichael Ellerman if (event->hw.sample_period) { 1399f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1400f2699491SMichael Ellerman if (left < 0x80000000L) 1401f2699491SMichael Ellerman val = 0x80000000L - left; 1402f2699491SMichael Ellerman } 1403f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1404330a1eb7SMichael Ellerman } 1405330a1eb7SMichael Ellerman 1406f2699491SMichael Ellerman event->hw.idx = idx; 1407f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1408f2699491SMichael Ellerman val = 0; 1409f2699491SMichael Ellerman write_pmc(idx, val); 1410330a1eb7SMichael Ellerman 1411f2699491SMichael Ellerman perf_event_update_userpage(event); 1412f2699491SMichael Ellerman } 1413f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 1414f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 1415f2699491SMichael Ellerman 1416f2699491SMichael Ellerman out_enable: 1417c2e37a26SMichael Ellerman pmao_restore_workaround(ebb); 1418c2e37a26SMichael Ellerman 14199de5cb0fSMichael Ellerman mmcr0 = ebb_switch_in(ebb, cpuhw); 1420330a1eb7SMichael Ellerman 1421f2699491SMichael Ellerman mb(); 1422b4d6c06cSAnshuman Khandual if (cpuhw->bhrb_users) 1423b4d6c06cSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 1424b4d6c06cSAnshuman Khandual 1425330a1eb7SMichael Ellerman write_mmcr0(cpuhw, mmcr0); 1426f2699491SMichael Ellerman 1427f2699491SMichael Ellerman /* 1428f2699491SMichael Ellerman * Enable instruction sampling if necessary 1429f2699491SMichael Ellerman */ 1430f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1431f2699491SMichael Ellerman mb(); 1432f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 1433f2699491SMichael Ellerman } 1434f2699491SMichael Ellerman 1435f2699491SMichael Ellerman out: 14363925f46bSAnshuman Khandual 1437f2699491SMichael Ellerman local_irq_restore(flags); 1438f2699491SMichael Ellerman } 1439f2699491SMichael Ellerman 1440f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1441f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1442f2699491SMichael Ellerman unsigned int *flags) 1443f2699491SMichael Ellerman { 1444f2699491SMichael Ellerman int n = 0; 1445f2699491SMichael Ellerman struct perf_event *event; 1446f2699491SMichael Ellerman 14475aa04b3eSRavi Bangoria if (group->pmu->task_ctx_nr == perf_hw_context) { 1448f2699491SMichael Ellerman if (n >= max_count) 1449f2699491SMichael Ellerman return -1; 1450f2699491SMichael Ellerman ctrs[n] = group; 1451f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1452f2699491SMichael Ellerman events[n++] = group->hw.config; 1453f2699491SMichael Ellerman } 1454f2699491SMichael Ellerman list_for_each_entry(event, &group->sibling_list, group_entry) { 14555aa04b3eSRavi Bangoria if (event->pmu->task_ctx_nr == perf_hw_context && 1456f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1457f2699491SMichael Ellerman if (n >= max_count) 1458f2699491SMichael Ellerman return -1; 1459f2699491SMichael Ellerman ctrs[n] = event; 1460f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1461f2699491SMichael Ellerman events[n++] = event->hw.config; 1462f2699491SMichael Ellerman } 1463f2699491SMichael Ellerman } 1464f2699491SMichael Ellerman return n; 1465f2699491SMichael Ellerman } 1466f2699491SMichael Ellerman 1467f2699491SMichael Ellerman /* 1468f2699491SMichael Ellerman * Add a event to the PMU. 1469f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1470f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1471f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1472f2699491SMichael Ellerman */ 1473f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1474f2699491SMichael Ellerman { 1475f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1476f2699491SMichael Ellerman unsigned long flags; 1477f2699491SMichael Ellerman int n0; 1478f2699491SMichael Ellerman int ret = -EAGAIN; 1479f2699491SMichael Ellerman 1480f2699491SMichael Ellerman local_irq_save(flags); 1481f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1482f2699491SMichael Ellerman 1483f2699491SMichael Ellerman /* 1484f2699491SMichael Ellerman * Add the event to the list (if there is room) 1485f2699491SMichael Ellerman * and check whether the total set is still feasible. 1486f2699491SMichael Ellerman */ 148769111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1488f2699491SMichael Ellerman n0 = cpuhw->n_events; 1489f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1490f2699491SMichael Ellerman goto out; 1491f2699491SMichael Ellerman cpuhw->event[n0] = event; 1492f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1493f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1494f2699491SMichael Ellerman 1495f53d168cSsukadev@linux.vnet.ibm.com /* 1496f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1497f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1498f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1499f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1500f53d168cSsukadev@linux.vnet.ibm.com */ 1501f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1502f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1503f53d168cSsukadev@linux.vnet.ibm.com else 1504f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1505f2699491SMichael Ellerman 1506f2699491SMichael Ellerman /* 1507f2699491SMichael Ellerman * If group events scheduling transaction was started, 1508f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1509f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1510f2699491SMichael Ellerman */ 15118f3e5684SSukadev Bhattiprolu if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) 1512f2699491SMichael Ellerman goto nocheck; 1513f2699491SMichael Ellerman 1514f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1515f2699491SMichael Ellerman goto out; 1516f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1517f2699491SMichael Ellerman goto out; 1518f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1519f2699491SMichael Ellerman 1520f2699491SMichael Ellerman nocheck: 1521330a1eb7SMichael Ellerman ebb_event_add(event); 1522330a1eb7SMichael Ellerman 1523f2699491SMichael Ellerman ++cpuhw->n_events; 1524f2699491SMichael Ellerman ++cpuhw->n_added; 1525f2699491SMichael Ellerman 1526f2699491SMichael Ellerman ret = 0; 1527f2699491SMichael Ellerman out: 1528ff3d79dcSAnshuman Khandual if (has_branch_stack(event)) { 15293925f46bSAnshuman Khandual power_pmu_bhrb_enable(event); 1530ff3d79dcSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1531ff3d79dcSAnshuman Khandual event->attr.branch_sample_type); 1532ff3d79dcSAnshuman Khandual } 15333925f46bSAnshuman Khandual 1534356d8ce3SMadhavan Srinivasan /* 1535356d8ce3SMadhavan Srinivasan * Workaround for POWER9 DD1 to use the Instruction Counter 1536356d8ce3SMadhavan Srinivasan * register value for instruction counting 1537356d8ce3SMadhavan Srinivasan */ 1538356d8ce3SMadhavan Srinivasan if (use_ic(event->attr.config)) 1539356d8ce3SMadhavan Srinivasan cpuhw->ic_init = mfspr(SPRN_IC); 1540356d8ce3SMadhavan Srinivasan 1541f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1542f2699491SMichael Ellerman local_irq_restore(flags); 1543f2699491SMichael Ellerman return ret; 1544f2699491SMichael Ellerman } 1545f2699491SMichael Ellerman 1546f2699491SMichael Ellerman /* 1547f2699491SMichael Ellerman * Remove a event from the PMU. 1548f2699491SMichael Ellerman */ 1549f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1550f2699491SMichael Ellerman { 1551f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1552f2699491SMichael Ellerman long i; 1553f2699491SMichael Ellerman unsigned long flags; 1554f2699491SMichael Ellerman 1555f2699491SMichael Ellerman local_irq_save(flags); 1556f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1557f2699491SMichael Ellerman 1558f2699491SMichael Ellerman power_pmu_read(event); 1559f2699491SMichael Ellerman 156069111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1561f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1562f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1563f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1564f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1565f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1566f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1567f2699491SMichael Ellerman } 1568f2699491SMichael Ellerman --cpuhw->n_events; 1569f2699491SMichael Ellerman ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1570f2699491SMichael Ellerman if (event->hw.idx) { 1571f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1572f2699491SMichael Ellerman event->hw.idx = 0; 1573f2699491SMichael Ellerman } 1574f2699491SMichael Ellerman perf_event_update_userpage(event); 1575f2699491SMichael Ellerman break; 1576f2699491SMichael Ellerman } 1577f2699491SMichael Ellerman } 1578f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1579f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1580f2699491SMichael Ellerman break; 1581f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1582f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1583f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1584f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1585f2699491SMichael Ellerman } 1586f2699491SMichael Ellerman --cpuhw->n_limited; 1587f2699491SMichael Ellerman } 1588f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1589f2699491SMichael Ellerman /* disable exceptions if no events are running */ 1590f2699491SMichael Ellerman cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1591f2699491SMichael Ellerman } 1592f2699491SMichael Ellerman 15933925f46bSAnshuman Khandual if (has_branch_stack(event)) 15943925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 15953925f46bSAnshuman Khandual 1596f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1597f2699491SMichael Ellerman local_irq_restore(flags); 1598f2699491SMichael Ellerman } 1599f2699491SMichael Ellerman 1600f2699491SMichael Ellerman /* 1601f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1602f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1603f2699491SMichael Ellerman */ 1604f2699491SMichael Ellerman 1605f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1606f2699491SMichael Ellerman { 1607f2699491SMichael Ellerman unsigned long flags; 1608f2699491SMichael Ellerman s64 left; 1609f2699491SMichael Ellerman unsigned long val; 1610f2699491SMichael Ellerman 1611f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1612f2699491SMichael Ellerman return; 1613f2699491SMichael Ellerman 1614f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1615f2699491SMichael Ellerman return; 1616f2699491SMichael Ellerman 1617f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1618f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1619f2699491SMichael Ellerman 1620f2699491SMichael Ellerman local_irq_save(flags); 1621f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1622f2699491SMichael Ellerman 1623f2699491SMichael Ellerman event->hw.state = 0; 1624f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1625f2699491SMichael Ellerman 1626f2699491SMichael Ellerman val = 0; 1627f2699491SMichael Ellerman if (left < 0x80000000L) 1628f2699491SMichael Ellerman val = 0x80000000L - left; 1629f2699491SMichael Ellerman 1630f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1631f2699491SMichael Ellerman 1632f2699491SMichael Ellerman perf_event_update_userpage(event); 1633f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1634f2699491SMichael Ellerman local_irq_restore(flags); 1635f2699491SMichael Ellerman } 1636f2699491SMichael Ellerman 1637f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1638f2699491SMichael Ellerman { 1639f2699491SMichael Ellerman unsigned long flags; 1640f2699491SMichael Ellerman 1641f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1642f2699491SMichael Ellerman return; 1643f2699491SMichael Ellerman 1644f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1645f2699491SMichael Ellerman return; 1646f2699491SMichael Ellerman 1647f2699491SMichael Ellerman local_irq_save(flags); 1648f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1649f2699491SMichael Ellerman 1650f2699491SMichael Ellerman power_pmu_read(event); 1651f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1652f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1653f2699491SMichael Ellerman 1654f2699491SMichael Ellerman perf_event_update_userpage(event); 1655f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1656f2699491SMichael Ellerman local_irq_restore(flags); 1657f2699491SMichael Ellerman } 1658f2699491SMichael Ellerman 1659f2699491SMichael Ellerman /* 1660f2699491SMichael Ellerman * Start group events scheduling transaction 1661f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1662f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1663fbbe0701SSukadev Bhattiprolu * 1664fbbe0701SSukadev Bhattiprolu * We only support PERF_PMU_TXN_ADD transactions. Save the 1665fbbe0701SSukadev Bhattiprolu * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1666fbbe0701SSukadev Bhattiprolu * transactions. 1667f2699491SMichael Ellerman */ 1668fbbe0701SSukadev Bhattiprolu static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1669f2699491SMichael Ellerman { 167069111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1671f2699491SMichael Ellerman 1672fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1673fbbe0701SSukadev Bhattiprolu 1674fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = txn_flags; 1675fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1676fbbe0701SSukadev Bhattiprolu return; 1677fbbe0701SSukadev Bhattiprolu 1678f2699491SMichael Ellerman perf_pmu_disable(pmu); 1679f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1680f2699491SMichael Ellerman } 1681f2699491SMichael Ellerman 1682f2699491SMichael Ellerman /* 1683f2699491SMichael Ellerman * Stop group events scheduling transaction 1684f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1685f2699491SMichael Ellerman * schedulability test. 1686f2699491SMichael Ellerman */ 1687e51df2c1SAnton Blanchard static void power_pmu_cancel_txn(struct pmu *pmu) 1688f2699491SMichael Ellerman { 168969111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1690fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 1691fbbe0701SSukadev Bhattiprolu 1692fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1693fbbe0701SSukadev Bhattiprolu 1694fbbe0701SSukadev Bhattiprolu txn_flags = cpuhw->txn_flags; 1695fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1696fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1697fbbe0701SSukadev Bhattiprolu return; 1698f2699491SMichael Ellerman 1699f2699491SMichael Ellerman perf_pmu_enable(pmu); 1700f2699491SMichael Ellerman } 1701f2699491SMichael Ellerman 1702f2699491SMichael Ellerman /* 1703f2699491SMichael Ellerman * Commit group events scheduling transaction 1704f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1705f2699491SMichael Ellerman * Return 0 if success 1706f2699491SMichael Ellerman */ 1707e51df2c1SAnton Blanchard static int power_pmu_commit_txn(struct pmu *pmu) 1708f2699491SMichael Ellerman { 1709f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1710f2699491SMichael Ellerman long i, n; 1711f2699491SMichael Ellerman 1712f2699491SMichael Ellerman if (!ppmu) 1713f2699491SMichael Ellerman return -EAGAIN; 1714fbbe0701SSukadev Bhattiprolu 171569111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1716fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1717fbbe0701SSukadev Bhattiprolu 1718fbbe0701SSukadev Bhattiprolu if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 1719fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1720fbbe0701SSukadev Bhattiprolu return 0; 1721fbbe0701SSukadev Bhattiprolu } 1722fbbe0701SSukadev Bhattiprolu 1723f2699491SMichael Ellerman n = cpuhw->n_events; 1724f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1725f2699491SMichael Ellerman return -EAGAIN; 1726f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1727f2699491SMichael Ellerman if (i < 0) 1728f2699491SMichael Ellerman return -EAGAIN; 1729f2699491SMichael Ellerman 1730f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1731f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1732f2699491SMichael Ellerman 1733fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1734f2699491SMichael Ellerman perf_pmu_enable(pmu); 1735f2699491SMichael Ellerman return 0; 1736f2699491SMichael Ellerman } 1737f2699491SMichael Ellerman 1738f2699491SMichael Ellerman /* 1739f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1740f2699491SMichael Ellerman * or 0 if not. 1741f2699491SMichael Ellerman * A event can only go on a limited PMC if it counts something 1742f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1743f2699491SMichael Ellerman * doesn't exclude any processor mode. 1744f2699491SMichael Ellerman */ 1745f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1746f2699491SMichael Ellerman unsigned int flags) 1747f2699491SMichael Ellerman { 1748f2699491SMichael Ellerman int n; 1749f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1750f2699491SMichael Ellerman 1751f2699491SMichael Ellerman if (event->attr.exclude_user 1752f2699491SMichael Ellerman || event->attr.exclude_kernel 1753f2699491SMichael Ellerman || event->attr.exclude_hv 1754f2699491SMichael Ellerman || event->attr.sample_period) 1755f2699491SMichael Ellerman return 0; 1756f2699491SMichael Ellerman 1757f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1758f2699491SMichael Ellerman return 1; 1759f2699491SMichael Ellerman 1760f2699491SMichael Ellerman /* 1761f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1762f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1763f2699491SMichael Ellerman */ 1764f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1765f2699491SMichael Ellerman return 0; 1766f2699491SMichael Ellerman 1767f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1768f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1769f2699491SMichael Ellerman 1770f2699491SMichael Ellerman return n > 0; 1771f2699491SMichael Ellerman } 1772f2699491SMichael Ellerman 1773f2699491SMichael Ellerman /* 1774f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1775f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1776f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1777f2699491SMichael Ellerman */ 1778f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1779f2699491SMichael Ellerman { 1780f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1781f2699491SMichael Ellerman int n; 1782f2699491SMichael Ellerman 1783f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1784f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1785f2699491SMichael Ellerman if (!n) 1786f2699491SMichael Ellerman return 0; 1787f2699491SMichael Ellerman return alt[0]; 1788f2699491SMichael Ellerman } 1789f2699491SMichael Ellerman 1790f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1791f2699491SMichael Ellerman static atomic_t num_events; 1792f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1793f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1794f2699491SMichael Ellerman 1795f2699491SMichael Ellerman /* 1796f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1797f2699491SMichael Ellerman */ 1798f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1799f2699491SMichael Ellerman { 1800f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1801f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1802f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1803f2699491SMichael Ellerman release_pmc_hardware(); 1804f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1805f2699491SMichael Ellerman } 1806f2699491SMichael Ellerman } 1807f2699491SMichael Ellerman 1808f2699491SMichael Ellerman /* 1809f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1810f2699491SMichael Ellerman */ 1811f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1812f2699491SMichael Ellerman { 1813f2699491SMichael Ellerman unsigned long type, op, result; 1814f2699491SMichael Ellerman int ev; 1815f2699491SMichael Ellerman 1816f2699491SMichael Ellerman if (!ppmu->cache_events) 1817f2699491SMichael Ellerman return -EINVAL; 1818f2699491SMichael Ellerman 1819f2699491SMichael Ellerman /* unpack config */ 1820f2699491SMichael Ellerman type = config & 0xff; 1821f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1822f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1823f2699491SMichael Ellerman 1824f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1825f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1826f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1827f2699491SMichael Ellerman return -EINVAL; 1828f2699491SMichael Ellerman 1829f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1830f2699491SMichael Ellerman if (ev == 0) 1831f2699491SMichael Ellerman return -EOPNOTSUPP; 1832f2699491SMichael Ellerman if (ev == -1) 1833f2699491SMichael Ellerman return -EINVAL; 1834f2699491SMichael Ellerman *eventp = ev; 1835f2699491SMichael Ellerman return 0; 1836f2699491SMichael Ellerman } 1837f2699491SMichael Ellerman 1838f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1839f2699491SMichael Ellerman { 1840f2699491SMichael Ellerman u64 ev; 1841f2699491SMichael Ellerman unsigned long flags; 1842f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1843f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1844f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1845f2699491SMichael Ellerman int n; 1846f2699491SMichael Ellerman int err; 1847f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1848f2699491SMichael Ellerman 1849f2699491SMichael Ellerman if (!ppmu) 1850f2699491SMichael Ellerman return -ENOENT; 1851f2699491SMichael Ellerman 18523925f46bSAnshuman Khandual if (has_branch_stack(event)) { 18533925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 18544d9690ddSJoel Stanley if (!(ppmu->flags & PPMU_ARCH_207S)) 18555375871dSLinus Torvalds return -EOPNOTSUPP; 18563925f46bSAnshuman Khandual } 18575375871dSLinus Torvalds 1858f2699491SMichael Ellerman switch (event->attr.type) { 1859f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1860f2699491SMichael Ellerman ev = event->attr.config; 1861f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1862f2699491SMichael Ellerman return -EOPNOTSUPP; 1863f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1864f2699491SMichael Ellerman break; 1865f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1866f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1867f2699491SMichael Ellerman if (err) 1868f2699491SMichael Ellerman return err; 1869f2699491SMichael Ellerman break; 1870f2699491SMichael Ellerman case PERF_TYPE_RAW: 1871f2699491SMichael Ellerman ev = event->attr.config; 1872f2699491SMichael Ellerman break; 1873f2699491SMichael Ellerman default: 1874f2699491SMichael Ellerman return -ENOENT; 1875f2699491SMichael Ellerman } 1876f2699491SMichael Ellerman 1877f2699491SMichael Ellerman event->hw.config_base = ev; 1878f2699491SMichael Ellerman event->hw.idx = 0; 1879f2699491SMichael Ellerman 1880f2699491SMichael Ellerman /* 1881f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1882f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1883f2699491SMichael Ellerman * the user set it to. 1884f2699491SMichael Ellerman */ 1885f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1886f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1887f2699491SMichael Ellerman 1888f2699491SMichael Ellerman /* 1889f2699491SMichael Ellerman * If this is a per-task event, then we can use 1890f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1891f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1892f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1893f2699491SMichael Ellerman */ 1894f2699491SMichael Ellerman flags = 0; 1895f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1896f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1897f2699491SMichael Ellerman 1898f2699491SMichael Ellerman /* 1899f2699491SMichael Ellerman * If this machine has limited events, check whether this 1900f2699491SMichael Ellerman * event_id could go on a limited event. 1901f2699491SMichael Ellerman */ 1902f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1903f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1904f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1905f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1906f2699491SMichael Ellerman /* 1907f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1908f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1909f2699491SMichael Ellerman * alternative goes on a normal PMC. 1910f2699491SMichael Ellerman */ 1911f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1912f2699491SMichael Ellerman if (!ev) 1913f2699491SMichael Ellerman return -EINVAL; 1914f2699491SMichael Ellerman } 1915f2699491SMichael Ellerman } 1916f2699491SMichael Ellerman 1917330a1eb7SMichael Ellerman /* Extra checks for EBB */ 1918330a1eb7SMichael Ellerman err = ebb_event_check(event); 1919330a1eb7SMichael Ellerman if (err) 1920330a1eb7SMichael Ellerman return err; 1921330a1eb7SMichael Ellerman 1922f2699491SMichael Ellerman /* 1923f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1924f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1925f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1926f2699491SMichael Ellerman */ 1927f2699491SMichael Ellerman n = 0; 1928f2699491SMichael Ellerman if (event->group_leader != event) { 1929f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1930f2699491SMichael Ellerman ctrs, events, cflags); 1931f2699491SMichael Ellerman if (n < 0) 1932f2699491SMichael Ellerman return -EINVAL; 1933f2699491SMichael Ellerman } 1934f2699491SMichael Ellerman events[n] = ev; 1935f2699491SMichael Ellerman ctrs[n] = event; 1936f2699491SMichael Ellerman cflags[n] = flags; 1937f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1938f2699491SMichael Ellerman return -EINVAL; 1939f2699491SMichael Ellerman 1940f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1941f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 19423925f46bSAnshuman Khandual 19433925f46bSAnshuman Khandual if (has_branch_stack(event)) { 19443925f46bSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 19453925f46bSAnshuman Khandual event->attr.branch_sample_type); 19463925f46bSAnshuman Khandual 194768de8867SJan Stancek if (cpuhw->bhrb_filter == -1) { 194868de8867SJan Stancek put_cpu_var(cpu_hw_events); 19493925f46bSAnshuman Khandual return -EOPNOTSUPP; 19503925f46bSAnshuman Khandual } 195168de8867SJan Stancek } 19523925f46bSAnshuman Khandual 1953f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 1954f2699491SMichael Ellerman if (err) 1955f2699491SMichael Ellerman return -EINVAL; 1956f2699491SMichael Ellerman 1957f2699491SMichael Ellerman event->hw.config = events[n]; 1958f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 1959f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1960f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 1961f2699491SMichael Ellerman 1962f2699491SMichael Ellerman /* 1963330a1eb7SMichael Ellerman * For EBB events we just context switch the PMC value, we don't do any 1964330a1eb7SMichael Ellerman * of the sample_period logic. We use hw.prev_count for this. 1965330a1eb7SMichael Ellerman */ 1966330a1eb7SMichael Ellerman if (is_ebb_event(event)) 1967330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, 0); 1968330a1eb7SMichael Ellerman 1969330a1eb7SMichael Ellerman /* 1970f2699491SMichael Ellerman * See if we need to reserve the PMU. 1971f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 1972f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 1973f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 1974f2699491SMichael Ellerman */ 1975f2699491SMichael Ellerman err = 0; 1976f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 1977f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1978f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 1979f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 1980f2699491SMichael Ellerman err = -EBUSY; 1981f2699491SMichael Ellerman else 1982f2699491SMichael Ellerman atomic_inc(&num_events); 1983f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1984f2699491SMichael Ellerman } 1985f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 1986f2699491SMichael Ellerman 1987f2699491SMichael Ellerman return err; 1988f2699491SMichael Ellerman } 1989f2699491SMichael Ellerman 19905375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 19915375871dSLinus Torvalds { 19925375871dSLinus Torvalds return event->hw.idx; 19935375871dSLinus Torvalds } 19945375871dSLinus Torvalds 19951c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 19961c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 19971c53a270SSukadev Bhattiprolu { 19981c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 19991c53a270SSukadev Bhattiprolu 20001c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 20011c53a270SSukadev Bhattiprolu 20021c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 20031c53a270SSukadev Bhattiprolu } 20041c53a270SSukadev Bhattiprolu 2005e51df2c1SAnton Blanchard static struct pmu power_pmu = { 2006f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 2007f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 2008f2699491SMichael Ellerman .event_init = power_pmu_event_init, 2009f2699491SMichael Ellerman .add = power_pmu_add, 2010f2699491SMichael Ellerman .del = power_pmu_del, 2011f2699491SMichael Ellerman .start = power_pmu_start, 2012f2699491SMichael Ellerman .stop = power_pmu_stop, 2013f2699491SMichael Ellerman .read = power_pmu_read, 2014f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 2015f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 2016f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 20175375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 2018acba3c7eSPeter Zijlstra .sched_task = power_pmu_sched_task, 2019f2699491SMichael Ellerman }; 2020f2699491SMichael Ellerman 2021f2699491SMichael Ellerman /* 2022f2699491SMichael Ellerman * A counter has overflowed; update its count and record 2023f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 2024f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 2025f2699491SMichael Ellerman */ 2026f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 2027f2699491SMichael Ellerman struct pt_regs *regs) 2028f2699491SMichael Ellerman { 2029f2699491SMichael Ellerman u64 period = event->hw.sample_period; 2030f2699491SMichael Ellerman s64 prev, delta, left; 2031f2699491SMichael Ellerman int record = 0; 2032f2699491SMichael Ellerman 2033f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 2034f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 2035f2699491SMichael Ellerman return; 2036f2699491SMichael Ellerman } 2037f2699491SMichael Ellerman 2038f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 2039f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 2040f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 2041f2699491SMichael Ellerman local64_add(delta, &event->count); 2042f2699491SMichael Ellerman 2043f2699491SMichael Ellerman /* 2044f2699491SMichael Ellerman * See if the total period for this event has expired, 2045f2699491SMichael Ellerman * and update for the next period. 2046f2699491SMichael Ellerman */ 2047f2699491SMichael Ellerman val = 0; 2048f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 2049e13e895fSMichael Neuling if (delta == 0) 2050e13e895fSMichael Neuling left++; 2051f2699491SMichael Ellerman if (period) { 2052f2699491SMichael Ellerman if (left <= 0) { 2053f2699491SMichael Ellerman left += period; 2054f2699491SMichael Ellerman if (left <= 0) 2055f2699491SMichael Ellerman left = period; 2056e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 2057f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2058f2699491SMichael Ellerman } 2059f2699491SMichael Ellerman if (left < 0x80000000LL) 2060f2699491SMichael Ellerman val = 0x80000000LL - left; 2061f2699491SMichael Ellerman } 2062f2699491SMichael Ellerman 2063f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 2064f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 2065f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 2066f2699491SMichael Ellerman perf_event_update_userpage(event); 2067f2699491SMichael Ellerman 2068f2699491SMichael Ellerman /* 2069f2699491SMichael Ellerman * Finally record data if requested. 2070f2699491SMichael Ellerman */ 2071f2699491SMichael Ellerman if (record) { 2072f2699491SMichael Ellerman struct perf_sample_data data; 2073f2699491SMichael Ellerman 2074fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 2075f2699491SMichael Ellerman 2076fc7ce9c7SKan Liang if (event->attr.sample_type & 2077fc7ce9c7SKan Liang (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) 2078f2699491SMichael Ellerman perf_get_data_addr(regs, &data.addr); 2079f2699491SMichael Ellerman 20803925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 20813925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 208269111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 20833925f46bSAnshuman Khandual power_pmu_bhrb_read(cpuhw); 20843925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 20853925f46bSAnshuman Khandual } 20863925f46bSAnshuman Khandual 208779e96f8fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && 208879e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src) 208979e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); 209079e96f8fSMadhavan Srinivasan 2091170a315fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_WEIGHT && 2092170a315fSMadhavan Srinivasan ppmu->get_mem_weight) 2093170a315fSMadhavan Srinivasan ppmu->get_mem_weight(&data.weight); 2094170a315fSMadhavan Srinivasan 2095f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 2096f2699491SMichael Ellerman power_pmu_stop(event, 0); 2097f2699491SMichael Ellerman } 2098f2699491SMichael Ellerman } 2099f2699491SMichael Ellerman 2100f2699491SMichael Ellerman /* 2101f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 2102f2699491SMichael Ellerman * for an event_id. 2103f2699491SMichael Ellerman */ 2104f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 2105f2699491SMichael Ellerman { 2106f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 2107f2699491SMichael Ellerman 2108f2699491SMichael Ellerman if (flags) 2109f2699491SMichael Ellerman return flags; 2110f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 2111f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 2112f2699491SMichael Ellerman } 2113f2699491SMichael Ellerman 2114f2699491SMichael Ellerman /* 2115f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 2116f2699491SMichael Ellerman * for an event_id. 2117f2699491SMichael Ellerman */ 2118f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 2119f2699491SMichael Ellerman { 212033904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 2121f2699491SMichael Ellerman 2122e6878835Ssukadev@linux.vnet.ibm.com if (use_siar && siar_valid(regs)) 21231ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 2124e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 2125e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 212675382aa7SAnton Blanchard else 212775382aa7SAnton Blanchard return regs->nip; 2128f2699491SMichael Ellerman } 2129f2699491SMichael Ellerman 2130bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 2131f2699491SMichael Ellerman { 2132f2699491SMichael Ellerman /* 2133f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 2134f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 2135f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 2136f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 2137f2699491SMichael Ellerman * cycles from overflow. 2138f2699491SMichael Ellerman * 2139f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 2140f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 2141f2699491SMichael Ellerman * don't want to mistakenly reset them. 2142f2699491SMichael Ellerman */ 2143bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 2144bc09c219SMichael Neuling return true; 2145bc09c219SMichael Neuling 2146bc09c219SMichael Neuling return false; 2147bc09c219SMichael Neuling } 2148bc09c219SMichael Neuling 2149bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 2150bc09c219SMichael Neuling { 2151bc09c219SMichael Neuling if ((int)val < 0) 2152f2699491SMichael Ellerman return true; 2153f2699491SMichael Ellerman 2154f2699491SMichael Ellerman return false; 2155f2699491SMichael Ellerman } 2156f2699491SMichael Ellerman 2157f2699491SMichael Ellerman /* 2158f2699491SMichael Ellerman * Performance monitor interrupt stuff 2159f2699491SMichael Ellerman */ 2160f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs) 2161f2699491SMichael Ellerman { 2162bc09c219SMichael Neuling int i, j; 216369111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2164f2699491SMichael Ellerman struct perf_event *event; 2165bc09c219SMichael Neuling unsigned long val[8]; 2166bc09c219SMichael Neuling int found, active; 2167f2699491SMichael Ellerman int nmi; 2168f2699491SMichael Ellerman 2169f2699491SMichael Ellerman if (cpuhw->n_limited) 2170f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2171f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 2172f2699491SMichael Ellerman 2173f2699491SMichael Ellerman perf_read_regs(regs); 2174f2699491SMichael Ellerman 2175f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 2176f2699491SMichael Ellerman if (nmi) 2177f2699491SMichael Ellerman nmi_enter(); 2178f2699491SMichael Ellerman else 2179f2699491SMichael Ellerman irq_enter(); 2180f2699491SMichael Ellerman 2181bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 2182bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 2183bc09c219SMichael Neuling val[i] = read_pmc(i + 1); 2184bc09c219SMichael Neuling 2185bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 2186bc09c219SMichael Neuling found = 0; 2187bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 2188bc09c219SMichael Neuling if (!pmc_overflow(val[i])) 2189bc09c219SMichael Neuling continue; 2190bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 2191bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 2192bc09c219SMichael Neuling /* 2193bc09c219SMichael Neuling * We've found one that's overflowed. For active 2194bc09c219SMichael Neuling * counters we need to log this. For inactive 2195bc09c219SMichael Neuling * counters, we need to reset it anyway 2196bc09c219SMichael Neuling */ 2197bc09c219SMichael Neuling found = 1; 2198bc09c219SMichael Neuling active = 0; 2199bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 2200bc09c219SMichael Neuling event = cpuhw->event[j]; 2201bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 2202bc09c219SMichael Neuling active = 1; 2203bc09c219SMichael Neuling record_and_restart(event, val[i], regs); 2204bc09c219SMichael Neuling break; 2205bc09c219SMichael Neuling } 2206bc09c219SMichael Neuling } 2207bc09c219SMichael Neuling if (!active) 2208bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 2209bc09c219SMichael Neuling write_pmc(i + 1, 0); 2210bc09c219SMichael Neuling } 2211bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 2212bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 2213f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 2214f2699491SMichael Ellerman event = cpuhw->event[i]; 2215f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2216f2699491SMichael Ellerman continue; 2217bc09c219SMichael Neuling if (pmc_overflow_power7(val[event->hw.idx - 1])) { 2218bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 2219f2699491SMichael Ellerman found = 1; 2220bc09c219SMichael Neuling record_and_restart(event, 2221bc09c219SMichael Neuling val[event->hw.idx - 1], 2222bc09c219SMichael Neuling regs); 2223f2699491SMichael Ellerman } 2224f2699491SMichael Ellerman } 2225f2699491SMichael Ellerman } 22266772faa1SMichael Ellerman if (!found && !nmi && printk_ratelimit()) 2227bc09c219SMichael Neuling printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2228f2699491SMichael Ellerman 2229f2699491SMichael Ellerman /* 2230f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 2231f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2232f2699491SMichael Ellerman * and thus allow interrupts to occur again. 2233f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 2234f2699491SMichael Ellerman * we get back out of this interrupt. 2235f2699491SMichael Ellerman */ 2236f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 2237f2699491SMichael Ellerman 2238f2699491SMichael Ellerman if (nmi) 2239f2699491SMichael Ellerman nmi_exit(); 2240f2699491SMichael Ellerman else 2241f2699491SMichael Ellerman irq_exit(); 2242f2699491SMichael Ellerman } 2243f2699491SMichael Ellerman 22447c98bd72SDaniel Axtens static int power_pmu_prepare_cpu(unsigned int cpu) 2245f2699491SMichael Ellerman { 2246f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2247f2699491SMichael Ellerman 224857ecde42SThomas Gleixner if (ppmu) { 2249f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 2250f2699491SMichael Ellerman cpuhw->mmcr[0] = MMCR0_FC; 2251f2699491SMichael Ellerman } 225257ecde42SThomas Gleixner return 0; 2253f2699491SMichael Ellerman } 2254f2699491SMichael Ellerman 2255061d19f2SPaul Gortmaker int register_power_pmu(struct power_pmu *pmu) 2256f2699491SMichael Ellerman { 2257f2699491SMichael Ellerman if (ppmu) 2258f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 2259f2699491SMichael Ellerman 2260f2699491SMichael Ellerman ppmu = pmu; 2261f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 2262f2699491SMichael Ellerman pmu->name); 2263f2699491SMichael Ellerman 22641c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 22651c53a270SSukadev Bhattiprolu 2266f2699491SMichael Ellerman #ifdef MSR_HV 2267f2699491SMichael Ellerman /* 2268f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 2269f2699491SMichael Ellerman */ 2270f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 2271f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 2272f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 2273f2699491SMichael Ellerman 2274f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 227573c1b41eSThomas Gleixner cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", 227657ecde42SThomas Gleixner power_pmu_prepare_cpu, NULL); 2277f2699491SMichael Ellerman return 0; 2278f2699491SMichael Ellerman } 2279