1f2699491SMichael Ellerman /* 2f2699491SMichael Ellerman * Performance event support - powerpc architecture code 3f2699491SMichael Ellerman * 4f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5f2699491SMichael Ellerman * 6f2699491SMichael Ellerman * This program is free software; you can redistribute it and/or 7f2699491SMichael Ellerman * modify it under the terms of the GNU General Public License 8f2699491SMichael Ellerman * as published by the Free Software Foundation; either version 9f2699491SMichael Ellerman * 2 of the License, or (at your option) any later version. 10f2699491SMichael Ellerman */ 11f2699491SMichael Ellerman #include <linux/kernel.h> 12f2699491SMichael Ellerman #include <linux/sched.h> 13f2699491SMichael Ellerman #include <linux/perf_event.h> 14f2699491SMichael Ellerman #include <linux/percpu.h> 15f2699491SMichael Ellerman #include <linux/hardirq.h> 1669123184SMichael Neuling #include <linux/uaccess.h> 17f2699491SMichael Ellerman #include <asm/reg.h> 18f2699491SMichael Ellerman #include <asm/pmc.h> 19f2699491SMichael Ellerman #include <asm/machdep.h> 20f2699491SMichael Ellerman #include <asm/firmware.h> 21f2699491SMichael Ellerman #include <asm/ptrace.h> 2269123184SMichael Neuling #include <asm/code-patching.h> 23f2699491SMichael Ellerman 243925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 253925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 263925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 273925f46bSAnshuman Khandual #define BHRB_EA 0xFFFFFFFFFFFFFFFC 283925f46bSAnshuman Khandual 29f2699491SMichael Ellerman struct cpu_hw_events { 30f2699491SMichael Ellerman int n_events; 31f2699491SMichael Ellerman int n_percpu; 32f2699491SMichael Ellerman int disabled; 33f2699491SMichael Ellerman int n_added; 34f2699491SMichael Ellerman int n_limited; 35f2699491SMichael Ellerman u8 pmcs_enabled; 36f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 37f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 38f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 39f2699491SMichael Ellerman unsigned long mmcr[3]; 40f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 41f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 42f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 43f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 44f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 45f2699491SMichael Ellerman 46f2699491SMichael Ellerman unsigned int group_flag; 47f2699491SMichael Ellerman int n_txn_start; 483925f46bSAnshuman Khandual 493925f46bSAnshuman Khandual /* BHRB bits */ 503925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 513925f46bSAnshuman Khandual int bhrb_users; 523925f46bSAnshuman Khandual void *bhrb_context; 533925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 543925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 55f2699491SMichael Ellerman }; 563925f46bSAnshuman Khandual 57f2699491SMichael Ellerman DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 58f2699491SMichael Ellerman 59f2699491SMichael Ellerman struct power_pmu *ppmu; 60f2699491SMichael Ellerman 61f2699491SMichael Ellerman /* 62f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 63f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 64f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 65f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 66f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 67f2699491SMichael Ellerman */ 68f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 69f2699491SMichael Ellerman 70f2699491SMichael Ellerman /* 71f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 72f2699491SMichael Ellerman * and a few other names are different. 73f2699491SMichael Ellerman */ 74f2699491SMichael Ellerman #ifdef CONFIG_PPC32 75f2699491SMichael Ellerman 76f2699491SMichael Ellerman #define MMCR0_FCHV 0 77f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 787a7a41f9SMichael Ellerman #define MMCR0_FC56 0 79378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 80330a1eb7SMichael Ellerman #define MMCR0_EBE 0 81330a1eb7SMichael Ellerman #define MMCR0_PMCC 0 82330a1eb7SMichael Ellerman #define MMCR0_PMCC_U6 0 83f2699491SMichael Ellerman 84f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 85f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 86f2699491SMichael Ellerman 87f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 88f2699491SMichael Ellerman { 89f2699491SMichael Ellerman return 0; 90f2699491SMichael Ellerman } 91f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 92f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 93f2699491SMichael Ellerman { 94f2699491SMichael Ellerman return 0; 95f2699491SMichael Ellerman } 9675382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 9775382aa7SAnton Blanchard { 9875382aa7SAnton Blanchard regs->result = 0; 9975382aa7SAnton Blanchard } 100f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 101f2699491SMichael Ellerman { 102f2699491SMichael Ellerman return 0; 103f2699491SMichael Ellerman } 104f2699491SMichael Ellerman 105e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 106e6878835Ssukadev@linux.vnet.ibm.com { 107e6878835Ssukadev@linux.vnet.ibm.com return 1; 108e6878835Ssukadev@linux.vnet.ibm.com } 109e6878835Ssukadev@linux.vnet.ibm.com 110330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) { return false; } 111330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) { return 0; } 112330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) { } 113330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) { } 114330a1eb7SMichael Ellerman static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0) 115330a1eb7SMichael Ellerman { 116330a1eb7SMichael Ellerman return mmcr0; 117330a1eb7SMichael Ellerman } 118330a1eb7SMichael Ellerman 119d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 120d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 121d52f2dc4SMichael Neuling void power_pmu_flush_branch_stack(void) {} 122d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 123f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 124f2699491SMichael Ellerman 12533904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 12633904054SMichael Ellerman { 127cbda6aa1SMichael Ellerman return !!regs->result; 12833904054SMichael Ellerman } 12933904054SMichael Ellerman 130f2699491SMichael Ellerman /* 131f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 132f2699491SMichael Ellerman */ 133f2699491SMichael Ellerman #ifdef CONFIG_PPC64 134f2699491SMichael Ellerman 135f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 136f2699491SMichael Ellerman { 137f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 138f2699491SMichael Ellerman 1397a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 140f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 141f2699491SMichael Ellerman if (slot > 1) 142f2699491SMichael Ellerman return 4 * (slot - 1); 143f2699491SMichael Ellerman } 1447a786832SMichael Ellerman 145f2699491SMichael Ellerman return 0; 146f2699491SMichael Ellerman } 147f2699491SMichael Ellerman 148f2699491SMichael Ellerman /* 149f2699491SMichael Ellerman * The user wants a data address recorded. 150f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 151f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 152f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 15358a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 15458a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 155f2699491SMichael Ellerman */ 156f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 157f2699491SMichael Ellerman { 158f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 15958a032c3SMichael Ellerman bool sdar_valid; 16058a032c3SMichael Ellerman 16158a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 16258a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 16358a032c3SMichael Ellerman else { 164e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 165e6878835Ssukadev@linux.vnet.ibm.com 166e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 167e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 168e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 169e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 170e6878835Ssukadev@linux.vnet.ibm.com else 171e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 172f2699491SMichael Ellerman 17358a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 17458a032c3SMichael Ellerman } 17558a032c3SMichael Ellerman 17658a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 177f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 178f2699491SMichael Ellerman } 179f2699491SMichael Ellerman 1805682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 18168b30bb9SAnton Blanchard { 18268b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 18368b30bb9SAnton Blanchard 1848f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 1858f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 1868f61aa32SMichael Ellerman 18768b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 18868b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 18968b30bb9SAnton Blanchard 1905682c460SMichael Ellerman return !!(regs->dsisr & sihv); 19168b30bb9SAnton Blanchard } 19268b30bb9SAnton Blanchard 1935682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 19468b30bb9SAnton Blanchard { 19568b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 19668b30bb9SAnton Blanchard 1978f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 1988f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 1998f61aa32SMichael Ellerman 20068b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 20168b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 20268b30bb9SAnton Blanchard 2035682c460SMichael Ellerman return !!(regs->dsisr & sipr); 20468b30bb9SAnton Blanchard } 20568b30bb9SAnton Blanchard 2061ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 2071ce447b9SBenjamin Herrenschmidt { 2081ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 2091ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2101ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 2111ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2121ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2131ce447b9SBenjamin Herrenschmidt } 2141ce447b9SBenjamin Herrenschmidt 215f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 216f2699491SMichael Ellerman { 21733904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 218f2699491SMichael Ellerman 21975382aa7SAnton Blanchard if (!use_siar) 2201ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2211ce447b9SBenjamin Herrenschmidt 2221ce447b9SBenjamin Herrenschmidt /* 2231ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2241ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2251ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2261ce447b9SBenjamin Herrenschmidt * results 2271ce447b9SBenjamin Herrenschmidt */ 228cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 2291ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 2301ce447b9SBenjamin Herrenschmidt if (siar >= PAGE_OFFSET) 2311ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2321ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2331ce447b9SBenjamin Herrenschmidt } 234f2699491SMichael Ellerman 235f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 2365682c460SMichael Ellerman if (regs_sipr(regs)) 237f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 2385682c460SMichael Ellerman 2395682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 240f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 2415682c460SMichael Ellerman 242f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 243f2699491SMichael Ellerman } 244f2699491SMichael Ellerman 245f2699491SMichael Ellerman /* 246f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 247f2699491SMichael Ellerman * on each interrupt. 2488f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 24975382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 25075382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 251f2699491SMichael Ellerman */ 252f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 253f2699491SMichael Ellerman { 25475382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 25575382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 25675382aa7SAnton Blanchard int use_siar; 25775382aa7SAnton Blanchard 2585682c460SMichael Ellerman regs->dsisr = mmcra; 259860aad71SMichael Ellerman 260cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2618f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 2628f61aa32SMichael Ellerman 2638f61aa32SMichael Ellerman /* 2645c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 2655c093efaSAnton Blanchard * not valid. Use pt_regs. 2665c093efaSAnton Blanchard * 2675c093efaSAnton Blanchard * If it is a marked event use the SIAR. 2685c093efaSAnton Blanchard * 2695c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 2705c093efaSAnton Blanchard * pt_regs. 2715c093efaSAnton Blanchard * 2725c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 2735c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 2745c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 2755c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 2765c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 2775c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 2785c093efaSAnton Blanchard * interrupts off hence the userspace check. 2795c093efaSAnton Blanchard */ 28075382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 28175382aa7SAnton Blanchard use_siar = 0; 2825c093efaSAnton Blanchard else if (marked) 2835c093efaSAnton Blanchard use_siar = 1; 2845c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 2855c093efaSAnton Blanchard use_siar = 0; 286cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 28775382aa7SAnton Blanchard use_siar = 0; 28875382aa7SAnton Blanchard else 28975382aa7SAnton Blanchard use_siar = 1; 29075382aa7SAnton Blanchard 291cbda6aa1SMichael Ellerman regs->result = use_siar; 292f2699491SMichael Ellerman } 293f2699491SMichael Ellerman 294f2699491SMichael Ellerman /* 295f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 296f2699491SMichael Ellerman * it as an NMI. 297f2699491SMichael Ellerman */ 298f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 299f2699491SMichael Ellerman { 300f2699491SMichael Ellerman return !regs->softe; 301f2699491SMichael Ellerman } 302f2699491SMichael Ellerman 303e6878835Ssukadev@linux.vnet.ibm.com /* 304e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 305e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 306e6878835Ssukadev@linux.vnet.ibm.com * 307e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 308e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 309e6878835Ssukadev@linux.vnet.ibm.com */ 310e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 311e6878835Ssukadev@linux.vnet.ibm.com { 312e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 313e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 314e6878835Ssukadev@linux.vnet.ibm.com 31558a032c3SMichael Ellerman if (marked) { 31658a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 31758a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 31858a032c3SMichael Ellerman 31958a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 320e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 32158a032c3SMichael Ellerman } 322e6878835Ssukadev@linux.vnet.ibm.com 323e6878835Ssukadev@linux.vnet.ibm.com return 1; 324e6878835Ssukadev@linux.vnet.ibm.com } 325e6878835Ssukadev@linux.vnet.ibm.com 326d52f2dc4SMichael Neuling 327d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 328d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 329d52f2dc4SMichael Neuling { 330d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 331d52f2dc4SMichael Neuling } 332d52f2dc4SMichael Neuling 333d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 334d52f2dc4SMichael Neuling { 335d52f2dc4SMichael Neuling struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 336d52f2dc4SMichael Neuling 337d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 338d52f2dc4SMichael Neuling return; 339d52f2dc4SMichael Neuling 340d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 341d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 342d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 343d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 344d52f2dc4SMichael Neuling } 345d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 346d52f2dc4SMichael Neuling } 347d52f2dc4SMichael Neuling 348d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 349d52f2dc4SMichael Neuling { 350d52f2dc4SMichael Neuling struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 351d52f2dc4SMichael Neuling 352d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 353d52f2dc4SMichael Neuling return; 354d52f2dc4SMichael Neuling 355d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 356d52f2dc4SMichael Neuling WARN_ON_ONCE(cpuhw->bhrb_users < 0); 357d52f2dc4SMichael Neuling 358d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 359d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 360d52f2dc4SMichael Neuling * events are active on the PMU. 361d52f2dc4SMichael Neuling */ 362d52f2dc4SMichael Neuling 363d52f2dc4SMichael Neuling /* avoid stale pointer */ 364d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 365d52f2dc4SMichael Neuling } 366d52f2dc4SMichael Neuling } 367d52f2dc4SMichael Neuling 368d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 369d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 370d52f2dc4SMichael Neuling */ 371d52f2dc4SMichael Neuling void power_pmu_flush_branch_stack(void) 372d52f2dc4SMichael Neuling { 373d52f2dc4SMichael Neuling if (ppmu->bhrb_nr) 374d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 375d52f2dc4SMichael Neuling } 37669123184SMichael Neuling /* Calculate the to address for a branch */ 37769123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 37869123184SMichael Neuling { 37969123184SMichael Neuling unsigned int instr; 38069123184SMichael Neuling int ret; 38169123184SMichael Neuling __u64 target; 38269123184SMichael Neuling 38369123184SMichael Neuling if (is_kernel_addr(addr)) 38469123184SMichael Neuling return branch_target((unsigned int *)addr); 38569123184SMichael Neuling 38669123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 38769123184SMichael Neuling pagefault_disable(); 38869123184SMichael Neuling ret = __get_user_inatomic(instr, (unsigned int __user *)addr); 38969123184SMichael Neuling if (ret) { 39069123184SMichael Neuling pagefault_enable(); 39169123184SMichael Neuling return 0; 39269123184SMichael Neuling } 39369123184SMichael Neuling pagefault_enable(); 39469123184SMichael Neuling 39569123184SMichael Neuling target = branch_target(&instr); 39669123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 39769123184SMichael Neuling return target; 39869123184SMichael Neuling 39969123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 40069123184SMichael Neuling return target - (unsigned long)&instr + addr; 40169123184SMichael Neuling } 402d52f2dc4SMichael Neuling 403d52f2dc4SMichael Neuling /* Processing BHRB entries */ 404506e70d1SMichael Neuling void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 405d52f2dc4SMichael Neuling { 406d52f2dc4SMichael Neuling u64 val; 407d52f2dc4SMichael Neuling u64 addr; 408506e70d1SMichael Neuling int r_index, u_index, pred; 409d52f2dc4SMichael Neuling 410d52f2dc4SMichael Neuling r_index = 0; 411d52f2dc4SMichael Neuling u_index = 0; 412d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 413d52f2dc4SMichael Neuling /* Assembly read function */ 414506e70d1SMichael Neuling val = read_bhrb(r_index++); 415506e70d1SMichael Neuling if (!val) 416d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 417d52f2dc4SMichael Neuling break; 418506e70d1SMichael Neuling else { 419d52f2dc4SMichael Neuling addr = val & BHRB_EA; 420d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 421d52f2dc4SMichael Neuling 422506e70d1SMichael Neuling if (!addr) 423506e70d1SMichael Neuling /* invalid entry */ 424d52f2dc4SMichael Neuling continue; 425d52f2dc4SMichael Neuling 426506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 427506e70d1SMichael Neuling * the most recent branch). 428506e70d1SMichael Neuling * There are two types of valid entries: 429506e70d1SMichael Neuling * 1) a target entry which is the to address of a 430506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 431506e70d1SMichael Neuling * entry read from the bhrb will be branch 432506e70d1SMichael Neuling * corresponding to this target (ie. the actual 433506e70d1SMichael Neuling * blr/bctr/btar instruction). 434506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 435506e70d1SMichael Neuling * target entry proceeds this, then this is the 436506e70d1SMichael Neuling * matching branch for that target. If this is not 437506e70d1SMichael Neuling * following a target entry, then this is a branch 438506e70d1SMichael Neuling * where the target is given as an immediate field 439506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 440506e70d1SMichael Neuling * In this case we need to read the instruction from 441506e70d1SMichael Neuling * memory to determine the target/to address. 442506e70d1SMichael Neuling */ 443d52f2dc4SMichael Neuling 444d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 445506e70d1SMichael Neuling /* Target branches use two entries 446506e70d1SMichael Neuling * (ie. computed gotos/XL form) 447506e70d1SMichael Neuling */ 448506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 449d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 450d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 451d52f2dc4SMichael Neuling 452506e70d1SMichael Neuling /* Get from address in next entry */ 453506e70d1SMichael Neuling val = read_bhrb(r_index++); 454506e70d1SMichael Neuling addr = val & BHRB_EA; 455506e70d1SMichael Neuling if (val & BHRB_TARGET) { 456506e70d1SMichael Neuling /* Shouldn't have two targets in a 457506e70d1SMichael Neuling row.. Reset index and try again */ 458506e70d1SMichael Neuling r_index--; 459506e70d1SMichael Neuling addr = 0; 460d52f2dc4SMichael Neuling } 461506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 462506e70d1SMichael Neuling } else { 463506e70d1SMichael Neuling /* Branches to immediate field 464506e70d1SMichael Neuling (ie I or B form) */ 465506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 46669123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 46769123184SMichael Neuling power_pmu_bhrb_to(addr); 468506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 469506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 470506e70d1SMichael Neuling } 471506e70d1SMichael Neuling u_index++; 472506e70d1SMichael Neuling 473d52f2dc4SMichael Neuling } 474d52f2dc4SMichael Neuling } 475d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 476d52f2dc4SMichael Neuling return; 477d52f2dc4SMichael Neuling } 478d52f2dc4SMichael Neuling 479330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) 480330a1eb7SMichael Ellerman { 481330a1eb7SMichael Ellerman /* 482330a1eb7SMichael Ellerman * This could be a per-PMU callback, but we'd rather avoid the cost. We 483330a1eb7SMichael Ellerman * check that the PMU supports EBB, meaning those that don't can still 484330a1eb7SMichael Ellerman * use bit 63 of the event code for something else if they wish. 485330a1eb7SMichael Ellerman */ 486330a1eb7SMichael Ellerman return (ppmu->flags & PPMU_EBB) && 4878d7c55d0SMichael Ellerman ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 488330a1eb7SMichael Ellerman } 489330a1eb7SMichael Ellerman 490330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) 491330a1eb7SMichael Ellerman { 492330a1eb7SMichael Ellerman struct perf_event *leader = event->group_leader; 493330a1eb7SMichael Ellerman 494330a1eb7SMichael Ellerman /* Event and group leader must agree on EBB */ 495330a1eb7SMichael Ellerman if (is_ebb_event(leader) != is_ebb_event(event)) 496330a1eb7SMichael Ellerman return -EINVAL; 497330a1eb7SMichael Ellerman 498330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 499330a1eb7SMichael Ellerman if (!(event->attach_state & PERF_ATTACH_TASK)) 500330a1eb7SMichael Ellerman return -EINVAL; 501330a1eb7SMichael Ellerman 502330a1eb7SMichael Ellerman if (!leader->attr.pinned || !leader->attr.exclusive) 503330a1eb7SMichael Ellerman return -EINVAL; 504330a1eb7SMichael Ellerman 505330a1eb7SMichael Ellerman if (event->attr.inherit || event->attr.sample_period || 506330a1eb7SMichael Ellerman event->attr.enable_on_exec || event->attr.freq) 507330a1eb7SMichael Ellerman return -EINVAL; 508330a1eb7SMichael Ellerman } 509330a1eb7SMichael Ellerman 510330a1eb7SMichael Ellerman return 0; 511330a1eb7SMichael Ellerman } 512330a1eb7SMichael Ellerman 513330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) 514330a1eb7SMichael Ellerman { 515330a1eb7SMichael Ellerman if (!is_ebb_event(event) || current->thread.used_ebb) 516330a1eb7SMichael Ellerman return; 517330a1eb7SMichael Ellerman 518330a1eb7SMichael Ellerman /* 519330a1eb7SMichael Ellerman * IFF this is the first time we've added an EBB event, set 520330a1eb7SMichael Ellerman * PMXE in the user MMCR0 so we can detect when it's cleared by 521330a1eb7SMichael Ellerman * userspace. We need this so that we can context switch while 522330a1eb7SMichael Ellerman * userspace is in the EBB handler (where PMXE is 0). 523330a1eb7SMichael Ellerman */ 524330a1eb7SMichael Ellerman current->thread.used_ebb = 1; 525330a1eb7SMichael Ellerman current->thread.mmcr0 |= MMCR0_PMXE; 526330a1eb7SMichael Ellerman } 527330a1eb7SMichael Ellerman 528330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) 529330a1eb7SMichael Ellerman { 530330a1eb7SMichael Ellerman if (!(mmcr0 & MMCR0_EBE)) 531330a1eb7SMichael Ellerman return; 532330a1eb7SMichael Ellerman 533330a1eb7SMichael Ellerman current->thread.siar = mfspr(SPRN_SIAR); 534330a1eb7SMichael Ellerman current->thread.sier = mfspr(SPRN_SIER); 535330a1eb7SMichael Ellerman current->thread.sdar = mfspr(SPRN_SDAR); 536330a1eb7SMichael Ellerman current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 537330a1eb7SMichael Ellerman current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 538330a1eb7SMichael Ellerman } 539330a1eb7SMichael Ellerman 540330a1eb7SMichael Ellerman static unsigned long ebb_switch_in(bool ebb, unsigned long mmcr0) 541330a1eb7SMichael Ellerman { 542330a1eb7SMichael Ellerman if (!ebb) 543330a1eb7SMichael Ellerman goto out; 544330a1eb7SMichael Ellerman 545330a1eb7SMichael Ellerman /* Enable EBB and read/write to all 6 PMCs for userspace */ 546330a1eb7SMichael Ellerman mmcr0 |= MMCR0_EBE | MMCR0_PMCC_U6; 547330a1eb7SMichael Ellerman 548330a1eb7SMichael Ellerman /* Add any bits from the user reg, FC or PMAO */ 549330a1eb7SMichael Ellerman mmcr0 |= current->thread.mmcr0; 550330a1eb7SMichael Ellerman 551330a1eb7SMichael Ellerman /* Be careful not to set PMXE if userspace had it cleared */ 552330a1eb7SMichael Ellerman if (!(current->thread.mmcr0 & MMCR0_PMXE)) 553330a1eb7SMichael Ellerman mmcr0 &= ~MMCR0_PMXE; 554330a1eb7SMichael Ellerman 555330a1eb7SMichael Ellerman mtspr(SPRN_SIAR, current->thread.siar); 556330a1eb7SMichael Ellerman mtspr(SPRN_SIER, current->thread.sier); 557330a1eb7SMichael Ellerman mtspr(SPRN_SDAR, current->thread.sdar); 558330a1eb7SMichael Ellerman mtspr(SPRN_MMCR2, current->thread.mmcr2); 559330a1eb7SMichael Ellerman out: 560330a1eb7SMichael Ellerman return mmcr0; 561330a1eb7SMichael Ellerman } 562f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 563f2699491SMichael Ellerman 564f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 565f2699491SMichael Ellerman 566f2699491SMichael Ellerman void perf_event_print_debug(void) 567f2699491SMichael Ellerman { 568f2699491SMichael Ellerman } 569f2699491SMichael Ellerman 570f2699491SMichael Ellerman /* 571f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 572f2699491SMichael Ellerman */ 573f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 574f2699491SMichael Ellerman { 575f2699491SMichael Ellerman unsigned long val; 576f2699491SMichael Ellerman 577f2699491SMichael Ellerman switch (idx) { 578f2699491SMichael Ellerman case 1: 579f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 580f2699491SMichael Ellerman break; 581f2699491SMichael Ellerman case 2: 582f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 583f2699491SMichael Ellerman break; 584f2699491SMichael Ellerman case 3: 585f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 586f2699491SMichael Ellerman break; 587f2699491SMichael Ellerman case 4: 588f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 589f2699491SMichael Ellerman break; 590f2699491SMichael Ellerman case 5: 591f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 592f2699491SMichael Ellerman break; 593f2699491SMichael Ellerman case 6: 594f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 595f2699491SMichael Ellerman break; 596f2699491SMichael Ellerman #ifdef CONFIG_PPC64 597f2699491SMichael Ellerman case 7: 598f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 599f2699491SMichael Ellerman break; 600f2699491SMichael Ellerman case 8: 601f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 602f2699491SMichael Ellerman break; 603f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 604f2699491SMichael Ellerman default: 605f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 606f2699491SMichael Ellerman val = 0; 607f2699491SMichael Ellerman } 608f2699491SMichael Ellerman return val; 609f2699491SMichael Ellerman } 610f2699491SMichael Ellerman 611f2699491SMichael Ellerman /* 612f2699491SMichael Ellerman * Write one PMC. 613f2699491SMichael Ellerman */ 614f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 615f2699491SMichael Ellerman { 616f2699491SMichael Ellerman switch (idx) { 617f2699491SMichael Ellerman case 1: 618f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 619f2699491SMichael Ellerman break; 620f2699491SMichael Ellerman case 2: 621f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 622f2699491SMichael Ellerman break; 623f2699491SMichael Ellerman case 3: 624f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 625f2699491SMichael Ellerman break; 626f2699491SMichael Ellerman case 4: 627f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 628f2699491SMichael Ellerman break; 629f2699491SMichael Ellerman case 5: 630f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 631f2699491SMichael Ellerman break; 632f2699491SMichael Ellerman case 6: 633f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 634f2699491SMichael Ellerman break; 635f2699491SMichael Ellerman #ifdef CONFIG_PPC64 636f2699491SMichael Ellerman case 7: 637f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 638f2699491SMichael Ellerman break; 639f2699491SMichael Ellerman case 8: 640f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 641f2699491SMichael Ellerman break; 642f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 643f2699491SMichael Ellerman default: 644f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 645f2699491SMichael Ellerman } 646f2699491SMichael Ellerman } 647f2699491SMichael Ellerman 648f2699491SMichael Ellerman /* 649f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 650f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 651f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 652f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 653f2699491SMichael Ellerman */ 654f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 655f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 656f2699491SMichael Ellerman int n_ev) 657f2699491SMichael Ellerman { 658f2699491SMichael Ellerman unsigned long mask, value, nv; 659f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 660f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 661f2699491SMichael Ellerman int i, j; 662f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 663f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 664f2699491SMichael Ellerman 665f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 666f2699491SMichael Ellerman return -1; 667f2699491SMichael Ellerman 668f2699491SMichael Ellerman /* First see if the events will go on as-is */ 669f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 670f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 671f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 672f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 673f2699491SMichael Ellerman cpuhw->alternatives[i]); 674f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 675f2699491SMichael Ellerman } 676f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 677f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 678f2699491SMichael Ellerman return -1; 679f2699491SMichael Ellerman } 680f2699491SMichael Ellerman value = mask = 0; 681f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 682f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 683f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 684f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) != 0 || 685f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][0]) & 686f2699491SMichael Ellerman cpuhw->amasks[i][0]) != 0) 687f2699491SMichael Ellerman break; 688f2699491SMichael Ellerman value = nv; 689f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 690f2699491SMichael Ellerman } 691f2699491SMichael Ellerman if (i == n_ev) 692f2699491SMichael Ellerman return 0; /* all OK */ 693f2699491SMichael Ellerman 694f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 695f2699491SMichael Ellerman if (!ppmu->get_alternatives) 696f2699491SMichael Ellerman return -1; 697f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 698f2699491SMichael Ellerman choice[i] = 0; 699f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 700f2699491SMichael Ellerman cpuhw->alternatives[i]); 701f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 702f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 703f2699491SMichael Ellerman &cpuhw->amasks[i][j], 704f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 705f2699491SMichael Ellerman } 706f2699491SMichael Ellerman 707f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 708f2699491SMichael Ellerman i = 0; 709f2699491SMichael Ellerman j = -1; 710f2699491SMichael Ellerman value = mask = nv = 0; 711f2699491SMichael Ellerman while (i < n_ev) { 712f2699491SMichael Ellerman if (j >= 0) { 713f2699491SMichael Ellerman /* we're backtracking, restore context */ 714f2699491SMichael Ellerman value = svalues[i]; 715f2699491SMichael Ellerman mask = smasks[i]; 716f2699491SMichael Ellerman j = choice[i]; 717f2699491SMichael Ellerman } 718f2699491SMichael Ellerman /* 719f2699491SMichael Ellerman * See if any alternative k for event_id i, 720f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 721f2699491SMichael Ellerman */ 722f2699491SMichael Ellerman while (++j < n_alt[i]) { 723f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 724f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 725f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 726f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 727f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 728f2699491SMichael Ellerman break; 729f2699491SMichael Ellerman } 730f2699491SMichael Ellerman if (j >= n_alt[i]) { 731f2699491SMichael Ellerman /* 732f2699491SMichael Ellerman * No feasible alternative, backtrack 733f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 734f2699491SMichael Ellerman * alternatives from where we got up to. 735f2699491SMichael Ellerman */ 736f2699491SMichael Ellerman if (--i < 0) 737f2699491SMichael Ellerman return -1; 738f2699491SMichael Ellerman } else { 739f2699491SMichael Ellerman /* 740f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 741f2699491SMichael Ellerman * remember where we got up to with this event_id, 742f2699491SMichael Ellerman * go on to the next event_id, and start with 743f2699491SMichael Ellerman * the first alternative for it. 744f2699491SMichael Ellerman */ 745f2699491SMichael Ellerman choice[i] = j; 746f2699491SMichael Ellerman svalues[i] = value; 747f2699491SMichael Ellerman smasks[i] = mask; 748f2699491SMichael Ellerman value = nv; 749f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 750f2699491SMichael Ellerman ++i; 751f2699491SMichael Ellerman j = -1; 752f2699491SMichael Ellerman } 753f2699491SMichael Ellerman } 754f2699491SMichael Ellerman 755f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 756f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 757f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 758f2699491SMichael Ellerman return 0; 759f2699491SMichael Ellerman } 760f2699491SMichael Ellerman 761f2699491SMichael Ellerman /* 762f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 763f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 764f2699491SMichael Ellerman * added events. 765f2699491SMichael Ellerman */ 766f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 767f2699491SMichael Ellerman int n_prev, int n_new) 768f2699491SMichael Ellerman { 769f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 770f2699491SMichael Ellerman int i, n, first; 771f2699491SMichael Ellerman struct perf_event *event; 772f2699491SMichael Ellerman 773f2699491SMichael Ellerman n = n_prev + n_new; 774f2699491SMichael Ellerman if (n <= 1) 775f2699491SMichael Ellerman return 0; 776f2699491SMichael Ellerman 777f2699491SMichael Ellerman first = 1; 778f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 779f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 780f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 781f2699491SMichael Ellerman continue; 782f2699491SMichael Ellerman } 783f2699491SMichael Ellerman event = ctrs[i]; 784f2699491SMichael Ellerman if (first) { 785f2699491SMichael Ellerman eu = event->attr.exclude_user; 786f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 787f2699491SMichael Ellerman eh = event->attr.exclude_hv; 788f2699491SMichael Ellerman first = 0; 789f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 790f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 791f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 792f2699491SMichael Ellerman return -EAGAIN; 793f2699491SMichael Ellerman } 794f2699491SMichael Ellerman } 795f2699491SMichael Ellerman 796f2699491SMichael Ellerman if (eu || ek || eh) 797f2699491SMichael Ellerman for (i = 0; i < n; ++i) 798f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 799f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 800f2699491SMichael Ellerman 801f2699491SMichael Ellerman return 0; 802f2699491SMichael Ellerman } 803f2699491SMichael Ellerman 804f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 805f2699491SMichael Ellerman { 806f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 807f2699491SMichael Ellerman 808f2699491SMichael Ellerman /* 809f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 810f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 811f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 812f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 813f2699491SMichael Ellerman * number of events to rollback at once. If we dectect a rollback 814f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 815f2699491SMichael Ellerman * counters. 816f2699491SMichael Ellerman */ 817f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 818f2699491SMichael Ellerman delta = 0; 819f2699491SMichael Ellerman 820f2699491SMichael Ellerman return delta; 821f2699491SMichael Ellerman } 822f2699491SMichael Ellerman 823f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 824f2699491SMichael Ellerman { 825f2699491SMichael Ellerman s64 val, delta, prev; 826f2699491SMichael Ellerman 827f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 828f2699491SMichael Ellerman return; 829f2699491SMichael Ellerman 830f2699491SMichael Ellerman if (!event->hw.idx) 831f2699491SMichael Ellerman return; 832330a1eb7SMichael Ellerman 833330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 834330a1eb7SMichael Ellerman val = read_pmc(event->hw.idx); 835330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, val); 836330a1eb7SMichael Ellerman return; 837330a1eb7SMichael Ellerman } 838330a1eb7SMichael Ellerman 839f2699491SMichael Ellerman /* 840f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 841f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 842f2699491SMichael Ellerman * Therefore we treat them like NMIs. 843f2699491SMichael Ellerman */ 844f2699491SMichael Ellerman do { 845f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 846f2699491SMichael Ellerman barrier(); 847f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 848f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 849f2699491SMichael Ellerman if (!delta) 850f2699491SMichael Ellerman return; 851f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 852f2699491SMichael Ellerman 853f2699491SMichael Ellerman local64_add(delta, &event->count); 854f2699491SMichael Ellerman local64_sub(delta, &event->hw.period_left); 855f2699491SMichael Ellerman } 856f2699491SMichael Ellerman 857f2699491SMichael Ellerman /* 858f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 859f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 860f2699491SMichael Ellerman * us if `event' is using such a PMC. 861f2699491SMichael Ellerman */ 862f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 863f2699491SMichael Ellerman { 864f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 865f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 866f2699491SMichael Ellerman } 867f2699491SMichael Ellerman 868f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 869f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 870f2699491SMichael Ellerman { 871f2699491SMichael Ellerman struct perf_event *event; 872f2699491SMichael Ellerman u64 val, prev, delta; 873f2699491SMichael Ellerman int i; 874f2699491SMichael Ellerman 875f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 876f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 877f2699491SMichael Ellerman if (!event->hw.idx) 878f2699491SMichael Ellerman continue; 879f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 880f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 881f2699491SMichael Ellerman event->hw.idx = 0; 882f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 883f2699491SMichael Ellerman if (delta) 884f2699491SMichael Ellerman local64_add(delta, &event->count); 885f2699491SMichael Ellerman } 886f2699491SMichael Ellerman } 887f2699491SMichael Ellerman 888f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 889f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 890f2699491SMichael Ellerman { 891f2699491SMichael Ellerman struct perf_event *event; 892f2699491SMichael Ellerman u64 val, prev; 893f2699491SMichael Ellerman int i; 894f2699491SMichael Ellerman 895f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 896f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 897f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 898f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 899f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 900f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 901f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 902f2699491SMichael Ellerman perf_event_update_userpage(event); 903f2699491SMichael Ellerman } 904f2699491SMichael Ellerman } 905f2699491SMichael Ellerman 906f2699491SMichael Ellerman /* 907f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 908f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 909f2699491SMichael Ellerman * other events. We try to keep the values from the limited 910f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 911f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 912f2699491SMichael Ellerman * the limited events as small and consistent as possible. 913f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 914f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 915f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 916f2699491SMichael Ellerman */ 917f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 918f2699491SMichael Ellerman { 919f2699491SMichael Ellerman unsigned long pmc5, pmc6; 920f2699491SMichael Ellerman 921f2699491SMichael Ellerman if (!cpuhw->n_limited) { 922f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 923f2699491SMichael Ellerman return; 924f2699491SMichael Ellerman } 925f2699491SMichael Ellerman 926f2699491SMichael Ellerman /* 927f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 928f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 929f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 930f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 931f2699491SMichael Ellerman * interrupt enable bits turned off. 932f2699491SMichael Ellerman */ 933f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 934f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 935f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 936f2699491SMichael Ellerman "i" (SPRN_MMCR0), 937f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 938f2699491SMichael Ellerman 939f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 940f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 941f2699491SMichael Ellerman else 942f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 943f2699491SMichael Ellerman 944f2699491SMichael Ellerman /* 945f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 946f2699491SMichael Ellerman * enable bits, if necessary. 947f2699491SMichael Ellerman */ 948f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 949f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 950f2699491SMichael Ellerman } 951f2699491SMichael Ellerman 952f2699491SMichael Ellerman /* 953f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 954f2699491SMichael Ellerman * events to be added or removed. 955f2699491SMichael Ellerman */ 956f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 957f2699491SMichael Ellerman { 958f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 959330a1eb7SMichael Ellerman unsigned long flags, mmcr0, val; 960f2699491SMichael Ellerman 961f2699491SMichael Ellerman if (!ppmu) 962f2699491SMichael Ellerman return; 963f2699491SMichael Ellerman local_irq_save(flags); 964f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 965f2699491SMichael Ellerman 966f2699491SMichael Ellerman if (!cpuhw->disabled) { 967f2699491SMichael Ellerman /* 968f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 969f2699491SMichael Ellerman */ 970f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 971f2699491SMichael Ellerman ppc_enable_pmcs(); 972f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 973f2699491SMichael Ellerman } 974f2699491SMichael Ellerman 975f2699491SMichael Ellerman /* 976330a1eb7SMichael Ellerman * Set the 'freeze counters' bit, clear EBE/PMCC/PMAO/FC56. 977378a6ee9SMichael Ellerman */ 978330a1eb7SMichael Ellerman val = mmcr0 = mfspr(SPRN_MMCR0); 979378a6ee9SMichael Ellerman val |= MMCR0_FC; 980330a1eb7SMichael Ellerman val &= ~(MMCR0_EBE | MMCR0_PMCC | MMCR0_PMAO | MMCR0_FC56); 981378a6ee9SMichael Ellerman 982378a6ee9SMichael Ellerman /* 983378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 984378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 985378a6ee9SMichael Ellerman * before we return. 986378a6ee9SMichael Ellerman */ 987378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 988378a6ee9SMichael Ellerman mb(); 989378a6ee9SMichael Ellerman 990378a6ee9SMichael Ellerman /* 991f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 992f2699491SMichael Ellerman */ 993f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 994f2699491SMichael Ellerman mtspr(SPRN_MMCRA, 995f2699491SMichael Ellerman cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 996f2699491SMichael Ellerman mb(); 997f2699491SMichael Ellerman } 998f2699491SMichael Ellerman 999378a6ee9SMichael Ellerman cpuhw->disabled = 1; 1000378a6ee9SMichael Ellerman cpuhw->n_added = 0; 1001330a1eb7SMichael Ellerman 1002330a1eb7SMichael Ellerman ebb_switch_out(mmcr0); 1003f2699491SMichael Ellerman } 1004330a1eb7SMichael Ellerman 1005f2699491SMichael Ellerman local_irq_restore(flags); 1006f2699491SMichael Ellerman } 1007f2699491SMichael Ellerman 1008f2699491SMichael Ellerman /* 1009f2699491SMichael Ellerman * Re-enable all events if disable == 0. 1010f2699491SMichael Ellerman * If we were previously disabled and events were added, then 1011f2699491SMichael Ellerman * put the new config on the PMU. 1012f2699491SMichael Ellerman */ 1013f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 1014f2699491SMichael Ellerman { 1015f2699491SMichael Ellerman struct perf_event *event; 1016f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1017f2699491SMichael Ellerman unsigned long flags; 1018f2699491SMichael Ellerman long i; 1019330a1eb7SMichael Ellerman unsigned long val, mmcr0; 1020f2699491SMichael Ellerman s64 left; 1021f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 1022f2699491SMichael Ellerman int n_lim; 1023f2699491SMichael Ellerman int idx; 1024330a1eb7SMichael Ellerman bool ebb; 1025f2699491SMichael Ellerman 1026f2699491SMichael Ellerman if (!ppmu) 1027f2699491SMichael Ellerman return; 1028f2699491SMichael Ellerman local_irq_save(flags); 10290a48843dSMichael Ellerman 1030f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 10310a48843dSMichael Ellerman if (!cpuhw->disabled) 10320a48843dSMichael Ellerman goto out; 10330a48843dSMichael Ellerman 10344ea355b5SMichael Ellerman if (cpuhw->n_events == 0) { 10354ea355b5SMichael Ellerman ppc_set_pmu_inuse(0); 10364ea355b5SMichael Ellerman goto out; 10374ea355b5SMichael Ellerman } 10384ea355b5SMichael Ellerman 1039f2699491SMichael Ellerman cpuhw->disabled = 0; 1040f2699491SMichael Ellerman 1041f2699491SMichael Ellerman /* 1042330a1eb7SMichael Ellerman * EBB requires an exclusive group and all events must have the EBB 1043330a1eb7SMichael Ellerman * flag set, or not set, so we can just check a single event. Also we 1044330a1eb7SMichael Ellerman * know we have at least one event. 1045330a1eb7SMichael Ellerman */ 1046330a1eb7SMichael Ellerman ebb = is_ebb_event(cpuhw->event[0]); 1047330a1eb7SMichael Ellerman 1048330a1eb7SMichael Ellerman /* 1049f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 1050f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 1051f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 1052f2699491SMichael Ellerman * (possibly updated for removal of events). 1053f2699491SMichael Ellerman */ 1054f2699491SMichael Ellerman if (!cpuhw->n_added) { 1055f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1056f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1057f2699491SMichael Ellerman goto out_enable; 1058f2699491SMichael Ellerman } 1059f2699491SMichael Ellerman 1060f2699491SMichael Ellerman /* 1061f2699491SMichael Ellerman * Compute MMCR* values for the new set of events 1062f2699491SMichael Ellerman */ 1063f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 1064f2699491SMichael Ellerman cpuhw->mmcr)) { 1065f2699491SMichael Ellerman /* shouldn't ever get here */ 1066f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 1067f2699491SMichael Ellerman goto out; 1068f2699491SMichael Ellerman } 1069f2699491SMichael Ellerman 1070f2699491SMichael Ellerman /* 1071f2699491SMichael Ellerman * Add in MMCR0 freeze bits corresponding to the 1072f2699491SMichael Ellerman * attr.exclude_* bits for the first event. 1073f2699491SMichael Ellerman * We have already checked that all events have the 1074f2699491SMichael Ellerman * same values for these bits as the first event. 1075f2699491SMichael Ellerman */ 1076f2699491SMichael Ellerman event = cpuhw->event[0]; 1077f2699491SMichael Ellerman if (event->attr.exclude_user) 1078f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCP; 1079f2699491SMichael Ellerman if (event->attr.exclude_kernel) 1080f2699491SMichael Ellerman cpuhw->mmcr[0] |= freeze_events_kernel; 1081f2699491SMichael Ellerman if (event->attr.exclude_hv) 1082f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCHV; 1083f2699491SMichael Ellerman 1084f2699491SMichael Ellerman /* 1085f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 1086f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 1087f2699491SMichael Ellerman * Then unfreeze the events. 1088f2699491SMichael Ellerman */ 1089f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 1090f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1091f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1092f2699491SMichael Ellerman mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1093f2699491SMichael Ellerman | MMCR0_FC); 1094f2699491SMichael Ellerman 1095f2699491SMichael Ellerman /* 1096f2699491SMichael Ellerman * Read off any pre-existing events that need to move 1097f2699491SMichael Ellerman * to another PMC. 1098f2699491SMichael Ellerman */ 1099f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1100f2699491SMichael Ellerman event = cpuhw->event[i]; 1101f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1102f2699491SMichael Ellerman power_pmu_read(event); 1103f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1104f2699491SMichael Ellerman event->hw.idx = 0; 1105f2699491SMichael Ellerman } 1106f2699491SMichael Ellerman } 1107f2699491SMichael Ellerman 1108f2699491SMichael Ellerman /* 1109f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 1110f2699491SMichael Ellerman */ 1111f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 1112f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1113f2699491SMichael Ellerman event = cpuhw->event[i]; 1114f2699491SMichael Ellerman if (event->hw.idx) 1115f2699491SMichael Ellerman continue; 1116f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1117f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1118f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1119f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1120f2699491SMichael Ellerman ++n_lim; 1121f2699491SMichael Ellerman continue; 1122f2699491SMichael Ellerman } 1123330a1eb7SMichael Ellerman 1124330a1eb7SMichael Ellerman if (ebb) 1125330a1eb7SMichael Ellerman val = local64_read(&event->hw.prev_count); 1126330a1eb7SMichael Ellerman else { 1127f2699491SMichael Ellerman val = 0; 1128f2699491SMichael Ellerman if (event->hw.sample_period) { 1129f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1130f2699491SMichael Ellerman if (left < 0x80000000L) 1131f2699491SMichael Ellerman val = 0x80000000L - left; 1132f2699491SMichael Ellerman } 1133f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1134330a1eb7SMichael Ellerman } 1135330a1eb7SMichael Ellerman 1136f2699491SMichael Ellerman event->hw.idx = idx; 1137f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1138f2699491SMichael Ellerman val = 0; 1139f2699491SMichael Ellerman write_pmc(idx, val); 1140330a1eb7SMichael Ellerman 1141f2699491SMichael Ellerman perf_event_update_userpage(event); 1142f2699491SMichael Ellerman } 1143f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 1144f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 1145f2699491SMichael Ellerman 1146f2699491SMichael Ellerman out_enable: 1147330a1eb7SMichael Ellerman mmcr0 = ebb_switch_in(ebb, cpuhw->mmcr[0]); 1148330a1eb7SMichael Ellerman 1149f2699491SMichael Ellerman mb(); 1150330a1eb7SMichael Ellerman write_mmcr0(cpuhw, mmcr0); 1151f2699491SMichael Ellerman 1152f2699491SMichael Ellerman /* 1153f2699491SMichael Ellerman * Enable instruction sampling if necessary 1154f2699491SMichael Ellerman */ 1155f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1156f2699491SMichael Ellerman mb(); 1157f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 1158f2699491SMichael Ellerman } 1159f2699491SMichael Ellerman 1160f2699491SMichael Ellerman out: 11613925f46bSAnshuman Khandual if (cpuhw->bhrb_users) 11623925f46bSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 11633925f46bSAnshuman Khandual 1164f2699491SMichael Ellerman local_irq_restore(flags); 1165f2699491SMichael Ellerman } 1166f2699491SMichael Ellerman 1167f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1168f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1169f2699491SMichael Ellerman unsigned int *flags) 1170f2699491SMichael Ellerman { 1171f2699491SMichael Ellerman int n = 0; 1172f2699491SMichael Ellerman struct perf_event *event; 1173f2699491SMichael Ellerman 1174f2699491SMichael Ellerman if (!is_software_event(group)) { 1175f2699491SMichael Ellerman if (n >= max_count) 1176f2699491SMichael Ellerman return -1; 1177f2699491SMichael Ellerman ctrs[n] = group; 1178f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1179f2699491SMichael Ellerman events[n++] = group->hw.config; 1180f2699491SMichael Ellerman } 1181f2699491SMichael Ellerman list_for_each_entry(event, &group->sibling_list, group_entry) { 1182f2699491SMichael Ellerman if (!is_software_event(event) && 1183f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1184f2699491SMichael Ellerman if (n >= max_count) 1185f2699491SMichael Ellerman return -1; 1186f2699491SMichael Ellerman ctrs[n] = event; 1187f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1188f2699491SMichael Ellerman events[n++] = event->hw.config; 1189f2699491SMichael Ellerman } 1190f2699491SMichael Ellerman } 1191f2699491SMichael Ellerman return n; 1192f2699491SMichael Ellerman } 1193f2699491SMichael Ellerman 1194f2699491SMichael Ellerman /* 1195f2699491SMichael Ellerman * Add a event to the PMU. 1196f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1197f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1198f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1199f2699491SMichael Ellerman */ 1200f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1201f2699491SMichael Ellerman { 1202f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1203f2699491SMichael Ellerman unsigned long flags; 1204f2699491SMichael Ellerman int n0; 1205f2699491SMichael Ellerman int ret = -EAGAIN; 1206f2699491SMichael Ellerman 1207f2699491SMichael Ellerman local_irq_save(flags); 1208f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1209f2699491SMichael Ellerman 1210f2699491SMichael Ellerman /* 1211f2699491SMichael Ellerman * Add the event to the list (if there is room) 1212f2699491SMichael Ellerman * and check whether the total set is still feasible. 1213f2699491SMichael Ellerman */ 1214f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1215f2699491SMichael Ellerman n0 = cpuhw->n_events; 1216f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1217f2699491SMichael Ellerman goto out; 1218f2699491SMichael Ellerman cpuhw->event[n0] = event; 1219f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1220f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1221f2699491SMichael Ellerman 1222f53d168cSsukadev@linux.vnet.ibm.com /* 1223f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1224f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1225f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1226f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1227f53d168cSsukadev@linux.vnet.ibm.com */ 1228f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1229f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1230f53d168cSsukadev@linux.vnet.ibm.com else 1231f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1232f2699491SMichael Ellerman 1233f2699491SMichael Ellerman /* 1234f2699491SMichael Ellerman * If group events scheduling transaction was started, 1235f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1236f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1237f2699491SMichael Ellerman */ 1238f2699491SMichael Ellerman if (cpuhw->group_flag & PERF_EVENT_TXN) 1239f2699491SMichael Ellerman goto nocheck; 1240f2699491SMichael Ellerman 1241f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1242f2699491SMichael Ellerman goto out; 1243f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1244f2699491SMichael Ellerman goto out; 1245f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1246f2699491SMichael Ellerman 1247f2699491SMichael Ellerman nocheck: 1248330a1eb7SMichael Ellerman ebb_event_add(event); 1249330a1eb7SMichael Ellerman 1250f2699491SMichael Ellerman ++cpuhw->n_events; 1251f2699491SMichael Ellerman ++cpuhw->n_added; 1252f2699491SMichael Ellerman 1253f2699491SMichael Ellerman ret = 0; 1254f2699491SMichael Ellerman out: 1255ff3d79dcSAnshuman Khandual if (has_branch_stack(event)) { 12563925f46bSAnshuman Khandual power_pmu_bhrb_enable(event); 1257ff3d79dcSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1258ff3d79dcSAnshuman Khandual event->attr.branch_sample_type); 1259ff3d79dcSAnshuman Khandual } 12603925f46bSAnshuman Khandual 1261f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1262f2699491SMichael Ellerman local_irq_restore(flags); 1263f2699491SMichael Ellerman return ret; 1264f2699491SMichael Ellerman } 1265f2699491SMichael Ellerman 1266f2699491SMichael Ellerman /* 1267f2699491SMichael Ellerman * Remove a event from the PMU. 1268f2699491SMichael Ellerman */ 1269f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1270f2699491SMichael Ellerman { 1271f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1272f2699491SMichael Ellerman long i; 1273f2699491SMichael Ellerman unsigned long flags; 1274f2699491SMichael Ellerman 1275f2699491SMichael Ellerman local_irq_save(flags); 1276f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1277f2699491SMichael Ellerman 1278f2699491SMichael Ellerman power_pmu_read(event); 1279f2699491SMichael Ellerman 1280f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1281f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1282f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1283f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1284f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1285f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1286f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1287f2699491SMichael Ellerman } 1288f2699491SMichael Ellerman --cpuhw->n_events; 1289f2699491SMichael Ellerman ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1290f2699491SMichael Ellerman if (event->hw.idx) { 1291f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1292f2699491SMichael Ellerman event->hw.idx = 0; 1293f2699491SMichael Ellerman } 1294f2699491SMichael Ellerman perf_event_update_userpage(event); 1295f2699491SMichael Ellerman break; 1296f2699491SMichael Ellerman } 1297f2699491SMichael Ellerman } 1298f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1299f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1300f2699491SMichael Ellerman break; 1301f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1302f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1303f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1304f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1305f2699491SMichael Ellerman } 1306f2699491SMichael Ellerman --cpuhw->n_limited; 1307f2699491SMichael Ellerman } 1308f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1309f2699491SMichael Ellerman /* disable exceptions if no events are running */ 1310f2699491SMichael Ellerman cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1311f2699491SMichael Ellerman } 1312f2699491SMichael Ellerman 13133925f46bSAnshuman Khandual if (has_branch_stack(event)) 13143925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 13153925f46bSAnshuman Khandual 1316f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1317f2699491SMichael Ellerman local_irq_restore(flags); 1318f2699491SMichael Ellerman } 1319f2699491SMichael Ellerman 1320f2699491SMichael Ellerman /* 1321f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1322f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1323f2699491SMichael Ellerman */ 1324f2699491SMichael Ellerman 1325f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1326f2699491SMichael Ellerman { 1327f2699491SMichael Ellerman unsigned long flags; 1328f2699491SMichael Ellerman s64 left; 1329f2699491SMichael Ellerman unsigned long val; 1330f2699491SMichael Ellerman 1331f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1332f2699491SMichael Ellerman return; 1333f2699491SMichael Ellerman 1334f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1335f2699491SMichael Ellerman return; 1336f2699491SMichael Ellerman 1337f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1338f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1339f2699491SMichael Ellerman 1340f2699491SMichael Ellerman local_irq_save(flags); 1341f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1342f2699491SMichael Ellerman 1343f2699491SMichael Ellerman event->hw.state = 0; 1344f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1345f2699491SMichael Ellerman 1346f2699491SMichael Ellerman val = 0; 1347f2699491SMichael Ellerman if (left < 0x80000000L) 1348f2699491SMichael Ellerman val = 0x80000000L - left; 1349f2699491SMichael Ellerman 1350f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1351f2699491SMichael Ellerman 1352f2699491SMichael Ellerman perf_event_update_userpage(event); 1353f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1354f2699491SMichael Ellerman local_irq_restore(flags); 1355f2699491SMichael Ellerman } 1356f2699491SMichael Ellerman 1357f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1358f2699491SMichael Ellerman { 1359f2699491SMichael Ellerman unsigned long flags; 1360f2699491SMichael Ellerman 1361f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1362f2699491SMichael Ellerman return; 1363f2699491SMichael Ellerman 1364f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1365f2699491SMichael Ellerman return; 1366f2699491SMichael Ellerman 1367f2699491SMichael Ellerman local_irq_save(flags); 1368f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1369f2699491SMichael Ellerman 1370f2699491SMichael Ellerman power_pmu_read(event); 1371f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1372f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1373f2699491SMichael Ellerman 1374f2699491SMichael Ellerman perf_event_update_userpage(event); 1375f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1376f2699491SMichael Ellerman local_irq_restore(flags); 1377f2699491SMichael Ellerman } 1378f2699491SMichael Ellerman 1379f2699491SMichael Ellerman /* 1380f2699491SMichael Ellerman * Start group events scheduling transaction 1381f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1382f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1383f2699491SMichael Ellerman */ 1384f2699491SMichael Ellerman void power_pmu_start_txn(struct pmu *pmu) 1385f2699491SMichael Ellerman { 1386f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1387f2699491SMichael Ellerman 1388f2699491SMichael Ellerman perf_pmu_disable(pmu); 1389f2699491SMichael Ellerman cpuhw->group_flag |= PERF_EVENT_TXN; 1390f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1391f2699491SMichael Ellerman } 1392f2699491SMichael Ellerman 1393f2699491SMichael Ellerman /* 1394f2699491SMichael Ellerman * Stop group events scheduling transaction 1395f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1396f2699491SMichael Ellerman * schedulability test. 1397f2699491SMichael Ellerman */ 1398f2699491SMichael Ellerman void power_pmu_cancel_txn(struct pmu *pmu) 1399f2699491SMichael Ellerman { 1400f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1401f2699491SMichael Ellerman 1402f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1403f2699491SMichael Ellerman perf_pmu_enable(pmu); 1404f2699491SMichael Ellerman } 1405f2699491SMichael Ellerman 1406f2699491SMichael Ellerman /* 1407f2699491SMichael Ellerman * Commit group events scheduling transaction 1408f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1409f2699491SMichael Ellerman * Return 0 if success 1410f2699491SMichael Ellerman */ 1411f2699491SMichael Ellerman int power_pmu_commit_txn(struct pmu *pmu) 1412f2699491SMichael Ellerman { 1413f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1414f2699491SMichael Ellerman long i, n; 1415f2699491SMichael Ellerman 1416f2699491SMichael Ellerman if (!ppmu) 1417f2699491SMichael Ellerman return -EAGAIN; 1418f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1419f2699491SMichael Ellerman n = cpuhw->n_events; 1420f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1421f2699491SMichael Ellerman return -EAGAIN; 1422f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1423f2699491SMichael Ellerman if (i < 0) 1424f2699491SMichael Ellerman return -EAGAIN; 1425f2699491SMichael Ellerman 1426f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1427f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1428f2699491SMichael Ellerman 1429f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1430f2699491SMichael Ellerman perf_pmu_enable(pmu); 1431f2699491SMichael Ellerman return 0; 1432f2699491SMichael Ellerman } 1433f2699491SMichael Ellerman 1434f2699491SMichael Ellerman /* 1435f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1436f2699491SMichael Ellerman * or 0 if not. 1437f2699491SMichael Ellerman * A event can only go on a limited PMC if it counts something 1438f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1439f2699491SMichael Ellerman * doesn't exclude any processor mode. 1440f2699491SMichael Ellerman */ 1441f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1442f2699491SMichael Ellerman unsigned int flags) 1443f2699491SMichael Ellerman { 1444f2699491SMichael Ellerman int n; 1445f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1446f2699491SMichael Ellerman 1447f2699491SMichael Ellerman if (event->attr.exclude_user 1448f2699491SMichael Ellerman || event->attr.exclude_kernel 1449f2699491SMichael Ellerman || event->attr.exclude_hv 1450f2699491SMichael Ellerman || event->attr.sample_period) 1451f2699491SMichael Ellerman return 0; 1452f2699491SMichael Ellerman 1453f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1454f2699491SMichael Ellerman return 1; 1455f2699491SMichael Ellerman 1456f2699491SMichael Ellerman /* 1457f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1458f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1459f2699491SMichael Ellerman */ 1460f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1461f2699491SMichael Ellerman return 0; 1462f2699491SMichael Ellerman 1463f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1464f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1465f2699491SMichael Ellerman 1466f2699491SMichael Ellerman return n > 0; 1467f2699491SMichael Ellerman } 1468f2699491SMichael Ellerman 1469f2699491SMichael Ellerman /* 1470f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1471f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1472f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1473f2699491SMichael Ellerman */ 1474f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1475f2699491SMichael Ellerman { 1476f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1477f2699491SMichael Ellerman int n; 1478f2699491SMichael Ellerman 1479f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1480f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1481f2699491SMichael Ellerman if (!n) 1482f2699491SMichael Ellerman return 0; 1483f2699491SMichael Ellerman return alt[0]; 1484f2699491SMichael Ellerman } 1485f2699491SMichael Ellerman 1486f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1487f2699491SMichael Ellerman static atomic_t num_events; 1488f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1489f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1490f2699491SMichael Ellerman 1491f2699491SMichael Ellerman /* 1492f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1493f2699491SMichael Ellerman */ 1494f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1495f2699491SMichael Ellerman { 1496f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1497f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1498f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1499f2699491SMichael Ellerman release_pmc_hardware(); 1500f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1501f2699491SMichael Ellerman } 1502f2699491SMichael Ellerman } 1503f2699491SMichael Ellerman 1504f2699491SMichael Ellerman /* 1505f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1506f2699491SMichael Ellerman */ 1507f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1508f2699491SMichael Ellerman { 1509f2699491SMichael Ellerman unsigned long type, op, result; 1510f2699491SMichael Ellerman int ev; 1511f2699491SMichael Ellerman 1512f2699491SMichael Ellerman if (!ppmu->cache_events) 1513f2699491SMichael Ellerman return -EINVAL; 1514f2699491SMichael Ellerman 1515f2699491SMichael Ellerman /* unpack config */ 1516f2699491SMichael Ellerman type = config & 0xff; 1517f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1518f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1519f2699491SMichael Ellerman 1520f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1521f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1522f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1523f2699491SMichael Ellerman return -EINVAL; 1524f2699491SMichael Ellerman 1525f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1526f2699491SMichael Ellerman if (ev == 0) 1527f2699491SMichael Ellerman return -EOPNOTSUPP; 1528f2699491SMichael Ellerman if (ev == -1) 1529f2699491SMichael Ellerman return -EINVAL; 1530f2699491SMichael Ellerman *eventp = ev; 1531f2699491SMichael Ellerman return 0; 1532f2699491SMichael Ellerman } 1533f2699491SMichael Ellerman 1534f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1535f2699491SMichael Ellerman { 1536f2699491SMichael Ellerman u64 ev; 1537f2699491SMichael Ellerman unsigned long flags; 1538f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1539f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1540f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1541f2699491SMichael Ellerman int n; 1542f2699491SMichael Ellerman int err; 1543f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1544f2699491SMichael Ellerman 1545f2699491SMichael Ellerman if (!ppmu) 1546f2699491SMichael Ellerman return -ENOENT; 1547f2699491SMichael Ellerman 15483925f46bSAnshuman Khandual if (has_branch_stack(event)) { 15493925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 15503925f46bSAnshuman Khandual if (!(ppmu->flags & PPMU_BHRB)) 15515375871dSLinus Torvalds return -EOPNOTSUPP; 15523925f46bSAnshuman Khandual } 15535375871dSLinus Torvalds 1554f2699491SMichael Ellerman switch (event->attr.type) { 1555f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1556f2699491SMichael Ellerman ev = event->attr.config; 1557f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1558f2699491SMichael Ellerman return -EOPNOTSUPP; 1559f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1560f2699491SMichael Ellerman break; 1561f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1562f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1563f2699491SMichael Ellerman if (err) 1564f2699491SMichael Ellerman return err; 1565f2699491SMichael Ellerman break; 1566f2699491SMichael Ellerman case PERF_TYPE_RAW: 1567f2699491SMichael Ellerman ev = event->attr.config; 1568f2699491SMichael Ellerman break; 1569f2699491SMichael Ellerman default: 1570f2699491SMichael Ellerman return -ENOENT; 1571f2699491SMichael Ellerman } 1572f2699491SMichael Ellerman 1573f2699491SMichael Ellerman event->hw.config_base = ev; 1574f2699491SMichael Ellerman event->hw.idx = 0; 1575f2699491SMichael Ellerman 1576f2699491SMichael Ellerman /* 1577f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1578f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1579f2699491SMichael Ellerman * the user set it to. 1580f2699491SMichael Ellerman */ 1581f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1582f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1583f2699491SMichael Ellerman 1584f2699491SMichael Ellerman /* 1585f2699491SMichael Ellerman * If this is a per-task event, then we can use 1586f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1587f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1588f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1589f2699491SMichael Ellerman */ 1590f2699491SMichael Ellerman flags = 0; 1591f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1592f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1593f2699491SMichael Ellerman 1594f2699491SMichael Ellerman /* 1595f2699491SMichael Ellerman * If this machine has limited events, check whether this 1596f2699491SMichael Ellerman * event_id could go on a limited event. 1597f2699491SMichael Ellerman */ 1598f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1599f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1600f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1601f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1602f2699491SMichael Ellerman /* 1603f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1604f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1605f2699491SMichael Ellerman * alternative goes on a normal PMC. 1606f2699491SMichael Ellerman */ 1607f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1608f2699491SMichael Ellerman if (!ev) 1609f2699491SMichael Ellerman return -EINVAL; 1610f2699491SMichael Ellerman } 1611f2699491SMichael Ellerman } 1612f2699491SMichael Ellerman 1613330a1eb7SMichael Ellerman /* Extra checks for EBB */ 1614330a1eb7SMichael Ellerman err = ebb_event_check(event); 1615330a1eb7SMichael Ellerman if (err) 1616330a1eb7SMichael Ellerman return err; 1617330a1eb7SMichael Ellerman 1618f2699491SMichael Ellerman /* 1619f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1620f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1621f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1622f2699491SMichael Ellerman */ 1623f2699491SMichael Ellerman n = 0; 1624f2699491SMichael Ellerman if (event->group_leader != event) { 1625f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1626f2699491SMichael Ellerman ctrs, events, cflags); 1627f2699491SMichael Ellerman if (n < 0) 1628f2699491SMichael Ellerman return -EINVAL; 1629f2699491SMichael Ellerman } 1630f2699491SMichael Ellerman events[n] = ev; 1631f2699491SMichael Ellerman ctrs[n] = event; 1632f2699491SMichael Ellerman cflags[n] = flags; 1633f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1634f2699491SMichael Ellerman return -EINVAL; 1635f2699491SMichael Ellerman 1636f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1637f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 16383925f46bSAnshuman Khandual 16393925f46bSAnshuman Khandual if (has_branch_stack(event)) { 16403925f46bSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 16413925f46bSAnshuman Khandual event->attr.branch_sample_type); 16423925f46bSAnshuman Khandual 16433925f46bSAnshuman Khandual if(cpuhw->bhrb_filter == -1) 16443925f46bSAnshuman Khandual return -EOPNOTSUPP; 16453925f46bSAnshuman Khandual } 16463925f46bSAnshuman Khandual 1647f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 1648f2699491SMichael Ellerman if (err) 1649f2699491SMichael Ellerman return -EINVAL; 1650f2699491SMichael Ellerman 1651f2699491SMichael Ellerman event->hw.config = events[n]; 1652f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 1653f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1654f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 1655f2699491SMichael Ellerman 1656f2699491SMichael Ellerman /* 1657330a1eb7SMichael Ellerman * For EBB events we just context switch the PMC value, we don't do any 1658330a1eb7SMichael Ellerman * of the sample_period logic. We use hw.prev_count for this. 1659330a1eb7SMichael Ellerman */ 1660330a1eb7SMichael Ellerman if (is_ebb_event(event)) 1661330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, 0); 1662330a1eb7SMichael Ellerman 1663330a1eb7SMichael Ellerman /* 1664f2699491SMichael Ellerman * See if we need to reserve the PMU. 1665f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 1666f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 1667f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 1668f2699491SMichael Ellerman */ 1669f2699491SMichael Ellerman err = 0; 1670f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 1671f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1672f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 1673f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 1674f2699491SMichael Ellerman err = -EBUSY; 1675f2699491SMichael Ellerman else 1676f2699491SMichael Ellerman atomic_inc(&num_events); 1677f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1678f2699491SMichael Ellerman } 1679f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 1680f2699491SMichael Ellerman 1681f2699491SMichael Ellerman return err; 1682f2699491SMichael Ellerman } 1683f2699491SMichael Ellerman 16845375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 16855375871dSLinus Torvalds { 16865375871dSLinus Torvalds return event->hw.idx; 16875375871dSLinus Torvalds } 16885375871dSLinus Torvalds 16891c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 16901c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 16911c53a270SSukadev Bhattiprolu { 16921c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 16931c53a270SSukadev Bhattiprolu 16941c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 16951c53a270SSukadev Bhattiprolu 16961c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 16971c53a270SSukadev Bhattiprolu } 16981c53a270SSukadev Bhattiprolu 1699f2699491SMichael Ellerman struct pmu power_pmu = { 1700f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 1701f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 1702f2699491SMichael Ellerman .event_init = power_pmu_event_init, 1703f2699491SMichael Ellerman .add = power_pmu_add, 1704f2699491SMichael Ellerman .del = power_pmu_del, 1705f2699491SMichael Ellerman .start = power_pmu_start, 1706f2699491SMichael Ellerman .stop = power_pmu_stop, 1707f2699491SMichael Ellerman .read = power_pmu_read, 1708f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 1709f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 1710f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 17115375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 17123925f46bSAnshuman Khandual .flush_branch_stack = power_pmu_flush_branch_stack, 1713f2699491SMichael Ellerman }; 1714f2699491SMichael Ellerman 1715f2699491SMichael Ellerman /* 1716f2699491SMichael Ellerman * A counter has overflowed; update its count and record 1717f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 1718f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 1719f2699491SMichael Ellerman */ 1720f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 1721f2699491SMichael Ellerman struct pt_regs *regs) 1722f2699491SMichael Ellerman { 1723f2699491SMichael Ellerman u64 period = event->hw.sample_period; 1724f2699491SMichael Ellerman s64 prev, delta, left; 1725f2699491SMichael Ellerman int record = 0; 1726f2699491SMichael Ellerman 1727f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 1728f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1729f2699491SMichael Ellerman return; 1730f2699491SMichael Ellerman } 1731f2699491SMichael Ellerman 1732f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 1733f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1734f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1735f2699491SMichael Ellerman local64_add(delta, &event->count); 1736f2699491SMichael Ellerman 1737f2699491SMichael Ellerman /* 1738f2699491SMichael Ellerman * See if the total period for this event has expired, 1739f2699491SMichael Ellerman * and update for the next period. 1740f2699491SMichael Ellerman */ 1741f2699491SMichael Ellerman val = 0; 1742f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 1743e13e895fSMichael Neuling if (delta == 0) 1744e13e895fSMichael Neuling left++; 1745f2699491SMichael Ellerman if (period) { 1746f2699491SMichael Ellerman if (left <= 0) { 1747f2699491SMichael Ellerman left += period; 1748f2699491SMichael Ellerman if (left <= 0) 1749f2699491SMichael Ellerman left = period; 1750e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 1751f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1752f2699491SMichael Ellerman } 1753f2699491SMichael Ellerman if (left < 0x80000000LL) 1754f2699491SMichael Ellerman val = 0x80000000LL - left; 1755f2699491SMichael Ellerman } 1756f2699491SMichael Ellerman 1757f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1758f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1759f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 1760f2699491SMichael Ellerman perf_event_update_userpage(event); 1761f2699491SMichael Ellerman 1762f2699491SMichael Ellerman /* 1763f2699491SMichael Ellerman * Finally record data if requested. 1764f2699491SMichael Ellerman */ 1765f2699491SMichael Ellerman if (record) { 1766f2699491SMichael Ellerman struct perf_sample_data data; 1767f2699491SMichael Ellerman 1768fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 1769f2699491SMichael Ellerman 1770f2699491SMichael Ellerman if (event->attr.sample_type & PERF_SAMPLE_ADDR) 1771f2699491SMichael Ellerman perf_get_data_addr(regs, &data.addr); 1772f2699491SMichael Ellerman 17733925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 17743925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 17753925f46bSAnshuman Khandual cpuhw = &__get_cpu_var(cpu_hw_events); 17763925f46bSAnshuman Khandual power_pmu_bhrb_read(cpuhw); 17773925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 17783925f46bSAnshuman Khandual } 17793925f46bSAnshuman Khandual 1780f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 1781f2699491SMichael Ellerman power_pmu_stop(event, 0); 1782f2699491SMichael Ellerman } 1783f2699491SMichael Ellerman } 1784f2699491SMichael Ellerman 1785f2699491SMichael Ellerman /* 1786f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 1787f2699491SMichael Ellerman * for an event_id. 1788f2699491SMichael Ellerman */ 1789f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 1790f2699491SMichael Ellerman { 1791f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 1792f2699491SMichael Ellerman 1793f2699491SMichael Ellerman if (flags) 1794f2699491SMichael Ellerman return flags; 1795f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 1796f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 1797f2699491SMichael Ellerman } 1798f2699491SMichael Ellerman 1799f2699491SMichael Ellerman /* 1800f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 1801f2699491SMichael Ellerman * for an event_id. 1802f2699491SMichael Ellerman */ 1803f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 1804f2699491SMichael Ellerman { 180533904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 1806f2699491SMichael Ellerman 1807e6878835Ssukadev@linux.vnet.ibm.com if (use_siar && siar_valid(regs)) 18081ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 1809e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 1810e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 181175382aa7SAnton Blanchard else 181275382aa7SAnton Blanchard return regs->nip; 1813f2699491SMichael Ellerman } 1814f2699491SMichael Ellerman 1815bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 1816f2699491SMichael Ellerman { 1817f2699491SMichael Ellerman /* 1818f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 1819f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 1820f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 1821f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 1822f2699491SMichael Ellerman * cycles from overflow. 1823f2699491SMichael Ellerman * 1824f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 1825f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 1826f2699491SMichael Ellerman * don't want to mistakenly reset them. 1827f2699491SMichael Ellerman */ 1828bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 1829bc09c219SMichael Neuling return true; 1830bc09c219SMichael Neuling 1831bc09c219SMichael Neuling return false; 1832bc09c219SMichael Neuling } 1833bc09c219SMichael Neuling 1834bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 1835bc09c219SMichael Neuling { 1836bc09c219SMichael Neuling if ((int)val < 0) 1837f2699491SMichael Ellerman return true; 1838f2699491SMichael Ellerman 1839f2699491SMichael Ellerman return false; 1840f2699491SMichael Ellerman } 1841f2699491SMichael Ellerman 1842f2699491SMichael Ellerman /* 1843f2699491SMichael Ellerman * Performance monitor interrupt stuff 1844f2699491SMichael Ellerman */ 1845f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs) 1846f2699491SMichael Ellerman { 1847bc09c219SMichael Neuling int i, j; 1848f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1849f2699491SMichael Ellerman struct perf_event *event; 1850bc09c219SMichael Neuling unsigned long val[8]; 1851bc09c219SMichael Neuling int found, active; 1852f2699491SMichael Ellerman int nmi; 1853f2699491SMichael Ellerman 1854f2699491SMichael Ellerman if (cpuhw->n_limited) 1855f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 1856f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 1857f2699491SMichael Ellerman 1858f2699491SMichael Ellerman perf_read_regs(regs); 1859f2699491SMichael Ellerman 1860f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 1861f2699491SMichael Ellerman if (nmi) 1862f2699491SMichael Ellerman nmi_enter(); 1863f2699491SMichael Ellerman else 1864f2699491SMichael Ellerman irq_enter(); 1865f2699491SMichael Ellerman 1866bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 1867bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 1868bc09c219SMichael Neuling val[i] = read_pmc(i + 1); 1869bc09c219SMichael Neuling 1870bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 1871bc09c219SMichael Neuling found = 0; 1872bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 1873bc09c219SMichael Neuling if (!pmc_overflow(val[i])) 1874bc09c219SMichael Neuling continue; 1875bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 1876bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 1877bc09c219SMichael Neuling /* 1878bc09c219SMichael Neuling * We've found one that's overflowed. For active 1879bc09c219SMichael Neuling * counters we need to log this. For inactive 1880bc09c219SMichael Neuling * counters, we need to reset it anyway 1881bc09c219SMichael Neuling */ 1882bc09c219SMichael Neuling found = 1; 1883bc09c219SMichael Neuling active = 0; 1884bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 1885bc09c219SMichael Neuling event = cpuhw->event[j]; 1886bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 1887bc09c219SMichael Neuling active = 1; 1888bc09c219SMichael Neuling record_and_restart(event, val[i], regs); 1889bc09c219SMichael Neuling break; 1890bc09c219SMichael Neuling } 1891bc09c219SMichael Neuling } 1892bc09c219SMichael Neuling if (!active) 1893bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 1894bc09c219SMichael Neuling write_pmc(i + 1, 0); 1895bc09c219SMichael Neuling } 1896bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 1897bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 1898f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1899f2699491SMichael Ellerman event = cpuhw->event[i]; 1900f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 1901f2699491SMichael Ellerman continue; 1902bc09c219SMichael Neuling if (pmc_overflow_power7(val[event->hw.idx - 1])) { 1903bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 1904f2699491SMichael Ellerman found = 1; 1905bc09c219SMichael Neuling record_and_restart(event, 1906bc09c219SMichael Neuling val[event->hw.idx - 1], 1907bc09c219SMichael Neuling regs); 1908f2699491SMichael Ellerman } 1909f2699491SMichael Ellerman } 1910f2699491SMichael Ellerman } 19116772faa1SMichael Ellerman if (!found && !nmi && printk_ratelimit()) 1912bc09c219SMichael Neuling printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 1913f2699491SMichael Ellerman 1914f2699491SMichael Ellerman /* 1915f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 1916f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 1917f2699491SMichael Ellerman * and thus allow interrupts to occur again. 1918f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 1919f2699491SMichael Ellerman * we get back out of this interrupt. 1920f2699491SMichael Ellerman */ 1921f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 1922f2699491SMichael Ellerman 1923f2699491SMichael Ellerman if (nmi) 1924f2699491SMichael Ellerman nmi_exit(); 1925f2699491SMichael Ellerman else 1926f2699491SMichael Ellerman irq_exit(); 1927f2699491SMichael Ellerman } 1928f2699491SMichael Ellerman 1929f2699491SMichael Ellerman static void power_pmu_setup(int cpu) 1930f2699491SMichael Ellerman { 1931f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 1932f2699491SMichael Ellerman 1933f2699491SMichael Ellerman if (!ppmu) 1934f2699491SMichael Ellerman return; 1935f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 1936f2699491SMichael Ellerman cpuhw->mmcr[0] = MMCR0_FC; 1937f2699491SMichael Ellerman } 1938f2699491SMichael Ellerman 1939061d19f2SPaul Gortmaker static int 1940f2699491SMichael Ellerman power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) 1941f2699491SMichael Ellerman { 1942f2699491SMichael Ellerman unsigned int cpu = (long)hcpu; 1943f2699491SMichael Ellerman 1944f2699491SMichael Ellerman switch (action & ~CPU_TASKS_FROZEN) { 1945f2699491SMichael Ellerman case CPU_UP_PREPARE: 1946f2699491SMichael Ellerman power_pmu_setup(cpu); 1947f2699491SMichael Ellerman break; 1948f2699491SMichael Ellerman 1949f2699491SMichael Ellerman default: 1950f2699491SMichael Ellerman break; 1951f2699491SMichael Ellerman } 1952f2699491SMichael Ellerman 1953f2699491SMichael Ellerman return NOTIFY_OK; 1954f2699491SMichael Ellerman } 1955f2699491SMichael Ellerman 1956061d19f2SPaul Gortmaker int register_power_pmu(struct power_pmu *pmu) 1957f2699491SMichael Ellerman { 1958f2699491SMichael Ellerman if (ppmu) 1959f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 1960f2699491SMichael Ellerman 1961f2699491SMichael Ellerman ppmu = pmu; 1962f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 1963f2699491SMichael Ellerman pmu->name); 1964f2699491SMichael Ellerman 19651c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 19661c53a270SSukadev Bhattiprolu 1967f2699491SMichael Ellerman #ifdef MSR_HV 1968f2699491SMichael Ellerman /* 1969f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 1970f2699491SMichael Ellerman */ 1971f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 1972f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 1973f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 1974f2699491SMichael Ellerman 1975f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 1976f2699491SMichael Ellerman perf_cpu_notifier(power_pmu_notifier); 1977f2699491SMichael Ellerman 1978f2699491SMichael Ellerman return 0; 1979f2699491SMichael Ellerman } 1980