1f2699491SMichael Ellerman /* 2f2699491SMichael Ellerman * Performance event support - powerpc architecture code 3f2699491SMichael Ellerman * 4f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5f2699491SMichael Ellerman * 6f2699491SMichael Ellerman * This program is free software; you can redistribute it and/or 7f2699491SMichael Ellerman * modify it under the terms of the GNU General Public License 8f2699491SMichael Ellerman * as published by the Free Software Foundation; either version 9f2699491SMichael Ellerman * 2 of the License, or (at your option) any later version. 10f2699491SMichael Ellerman */ 11f2699491SMichael Ellerman #include <linux/kernel.h> 12f2699491SMichael Ellerman #include <linux/sched.h> 13f2699491SMichael Ellerman #include <linux/perf_event.h> 14f2699491SMichael Ellerman #include <linux/percpu.h> 15f2699491SMichael Ellerman #include <linux/hardirq.h> 16f2699491SMichael Ellerman #include <asm/reg.h> 17f2699491SMichael Ellerman #include <asm/pmc.h> 18f2699491SMichael Ellerman #include <asm/machdep.h> 19f2699491SMichael Ellerman #include <asm/firmware.h> 20f2699491SMichael Ellerman #include <asm/ptrace.h> 21f2699491SMichael Ellerman 22f2699491SMichael Ellerman struct cpu_hw_events { 23f2699491SMichael Ellerman int n_events; 24f2699491SMichael Ellerman int n_percpu; 25f2699491SMichael Ellerman int disabled; 26f2699491SMichael Ellerman int n_added; 27f2699491SMichael Ellerman int n_limited; 28f2699491SMichael Ellerman u8 pmcs_enabled; 29f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 30f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 31f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 32f2699491SMichael Ellerman unsigned long mmcr[3]; 33f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 34f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 35f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 36f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 37f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 38f2699491SMichael Ellerman 39f2699491SMichael Ellerman unsigned int group_flag; 40f2699491SMichael Ellerman int n_txn_start; 41f2699491SMichael Ellerman }; 42f2699491SMichael Ellerman DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 43f2699491SMichael Ellerman 44f2699491SMichael Ellerman struct power_pmu *ppmu; 45f2699491SMichael Ellerman 46f2699491SMichael Ellerman /* 47f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 48f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 49f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 50f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 51f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 52f2699491SMichael Ellerman */ 53f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 54f2699491SMichael Ellerman 55f2699491SMichael Ellerman /* 56f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 57f2699491SMichael Ellerman * and a few other names are different. 58f2699491SMichael Ellerman */ 59f2699491SMichael Ellerman #ifdef CONFIG_PPC32 60f2699491SMichael Ellerman 61f2699491SMichael Ellerman #define MMCR0_FCHV 0 62f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 63f2699491SMichael Ellerman 64f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 65f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 66f2699491SMichael Ellerman 67f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 68f2699491SMichael Ellerman { 69f2699491SMichael Ellerman return 0; 70f2699491SMichael Ellerman } 71f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 72f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 73f2699491SMichael Ellerman { 74f2699491SMichael Ellerman return 0; 75f2699491SMichael Ellerman } 7675382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 7775382aa7SAnton Blanchard { 7875382aa7SAnton Blanchard regs->result = 0; 7975382aa7SAnton Blanchard } 80f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 81f2699491SMichael Ellerman { 82f2699491SMichael Ellerman return 0; 83f2699491SMichael Ellerman } 84f2699491SMichael Ellerman 85f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 86f2699491SMichael Ellerman 87f2699491SMichael Ellerman /* 88f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 89f2699491SMichael Ellerman */ 90f2699491SMichael Ellerman #ifdef CONFIG_PPC64 91f2699491SMichael Ellerman 92f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 93f2699491SMichael Ellerman { 94f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 95f2699491SMichael Ellerman 96f2699491SMichael Ellerman if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) { 97f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 98f2699491SMichael Ellerman if (slot > 1) 99f2699491SMichael Ellerman return 4 * (slot - 1); 100f2699491SMichael Ellerman } 101f2699491SMichael Ellerman return 0; 102f2699491SMichael Ellerman } 103f2699491SMichael Ellerman 104f2699491SMichael Ellerman /* 105f2699491SMichael Ellerman * The user wants a data address recorded. 106f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 107f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 108f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 109f2699491SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC 110f2699491SMichael Ellerman * bit in MMCRA. 111f2699491SMichael Ellerman */ 112f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 113f2699491SMichael Ellerman { 114f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 115f2699491SMichael Ellerman unsigned long sdsync = (ppmu->flags & PPMU_ALT_SIPR) ? 116f2699491SMichael Ellerman POWER6_MMCRA_SDSYNC : MMCRA_SDSYNC; 117f2699491SMichael Ellerman 118f2699491SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) 119f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 120f2699491SMichael Ellerman } 121f2699491SMichael Ellerman 12268b30bb9SAnton Blanchard static bool mmcra_sihv(unsigned long mmcra) 12368b30bb9SAnton Blanchard { 12468b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 12568b30bb9SAnton Blanchard 12668b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 12768b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 12868b30bb9SAnton Blanchard 12968b30bb9SAnton Blanchard return !!(mmcra & sihv); 13068b30bb9SAnton Blanchard } 13168b30bb9SAnton Blanchard 13268b30bb9SAnton Blanchard static bool mmcra_sipr(unsigned long mmcra) 13368b30bb9SAnton Blanchard { 13468b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 13568b30bb9SAnton Blanchard 13668b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 13768b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 13868b30bb9SAnton Blanchard 13968b30bb9SAnton Blanchard return !!(mmcra & sipr); 14068b30bb9SAnton Blanchard } 14168b30bb9SAnton Blanchard 1421ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 1431ce447b9SBenjamin Herrenschmidt { 1441ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 1451ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 1461ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 1471ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 1481ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 1491ce447b9SBenjamin Herrenschmidt } 1501ce447b9SBenjamin Herrenschmidt 151f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 152f2699491SMichael Ellerman { 153f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 15475382aa7SAnton Blanchard unsigned long use_siar = regs->result; 155f2699491SMichael Ellerman 15675382aa7SAnton Blanchard if (!use_siar) 1571ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 1581ce447b9SBenjamin Herrenschmidt 1591ce447b9SBenjamin Herrenschmidt /* 1601ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 1611ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 1621ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 1631ce447b9SBenjamin Herrenschmidt * results 1641ce447b9SBenjamin Herrenschmidt */ 1651ce447b9SBenjamin Herrenschmidt if (ppmu->flags & PPMU_NO_SIPR) { 1661ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 1671ce447b9SBenjamin Herrenschmidt if (siar >= PAGE_OFFSET) 1681ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 1691ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 1701ce447b9SBenjamin Herrenschmidt } 171f2699491SMichael Ellerman 172f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 17368b30bb9SAnton Blanchard if (mmcra_sipr(mmcra)) 174f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 17568b30bb9SAnton Blanchard if (mmcra_sihv(mmcra) && (freeze_events_kernel != MMCR0_FCHV)) 176f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 177f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 178f2699491SMichael Ellerman } 179f2699491SMichael Ellerman 180f2699491SMichael Ellerman /* 181f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 182f2699491SMichael Ellerman * on each interrupt. 18375382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 18475382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 185f2699491SMichael Ellerman */ 186f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 187f2699491SMichael Ellerman { 18875382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 18975382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 19075382aa7SAnton Blanchard int use_siar; 19175382aa7SAnton Blanchard 19275382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 19375382aa7SAnton Blanchard use_siar = 0; 19475382aa7SAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING) && !marked) 19575382aa7SAnton Blanchard use_siar = 0; 19675382aa7SAnton Blanchard else 19775382aa7SAnton Blanchard use_siar = 1; 19875382aa7SAnton Blanchard 19975382aa7SAnton Blanchard regs->dsisr = mmcra; 20075382aa7SAnton Blanchard regs->result = use_siar; 201f2699491SMichael Ellerman } 202f2699491SMichael Ellerman 203f2699491SMichael Ellerman /* 204f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 205f2699491SMichael Ellerman * it as an NMI. 206f2699491SMichael Ellerman */ 207f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 208f2699491SMichael Ellerman { 209f2699491SMichael Ellerman return !regs->softe; 210f2699491SMichael Ellerman } 211f2699491SMichael Ellerman 212f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 213f2699491SMichael Ellerman 214f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 215f2699491SMichael Ellerman 216f2699491SMichael Ellerman void perf_event_print_debug(void) 217f2699491SMichael Ellerman { 218f2699491SMichael Ellerman } 219f2699491SMichael Ellerman 220f2699491SMichael Ellerman /* 221f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 222f2699491SMichael Ellerman */ 223f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 224f2699491SMichael Ellerman { 225f2699491SMichael Ellerman unsigned long val; 226f2699491SMichael Ellerman 227f2699491SMichael Ellerman switch (idx) { 228f2699491SMichael Ellerman case 1: 229f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 230f2699491SMichael Ellerman break; 231f2699491SMichael Ellerman case 2: 232f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 233f2699491SMichael Ellerman break; 234f2699491SMichael Ellerman case 3: 235f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 236f2699491SMichael Ellerman break; 237f2699491SMichael Ellerman case 4: 238f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 239f2699491SMichael Ellerman break; 240f2699491SMichael Ellerman case 5: 241f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 242f2699491SMichael Ellerman break; 243f2699491SMichael Ellerman case 6: 244f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 245f2699491SMichael Ellerman break; 246f2699491SMichael Ellerman #ifdef CONFIG_PPC64 247f2699491SMichael Ellerman case 7: 248f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 249f2699491SMichael Ellerman break; 250f2699491SMichael Ellerman case 8: 251f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 252f2699491SMichael Ellerman break; 253f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 254f2699491SMichael Ellerman default: 255f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 256f2699491SMichael Ellerman val = 0; 257f2699491SMichael Ellerman } 258f2699491SMichael Ellerman return val; 259f2699491SMichael Ellerman } 260f2699491SMichael Ellerman 261f2699491SMichael Ellerman /* 262f2699491SMichael Ellerman * Write one PMC. 263f2699491SMichael Ellerman */ 264f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 265f2699491SMichael Ellerman { 266f2699491SMichael Ellerman switch (idx) { 267f2699491SMichael Ellerman case 1: 268f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 269f2699491SMichael Ellerman break; 270f2699491SMichael Ellerman case 2: 271f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 272f2699491SMichael Ellerman break; 273f2699491SMichael Ellerman case 3: 274f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 275f2699491SMichael Ellerman break; 276f2699491SMichael Ellerman case 4: 277f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 278f2699491SMichael Ellerman break; 279f2699491SMichael Ellerman case 5: 280f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 281f2699491SMichael Ellerman break; 282f2699491SMichael Ellerman case 6: 283f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 284f2699491SMichael Ellerman break; 285f2699491SMichael Ellerman #ifdef CONFIG_PPC64 286f2699491SMichael Ellerman case 7: 287f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 288f2699491SMichael Ellerman break; 289f2699491SMichael Ellerman case 8: 290f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 291f2699491SMichael Ellerman break; 292f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 293f2699491SMichael Ellerman default: 294f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 295f2699491SMichael Ellerman } 296f2699491SMichael Ellerman } 297f2699491SMichael Ellerman 298f2699491SMichael Ellerman /* 299f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 300f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 301f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 302f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 303f2699491SMichael Ellerman */ 304f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 305f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 306f2699491SMichael Ellerman int n_ev) 307f2699491SMichael Ellerman { 308f2699491SMichael Ellerman unsigned long mask, value, nv; 309f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 310f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 311f2699491SMichael Ellerman int i, j; 312f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 313f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 314f2699491SMichael Ellerman 315f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 316f2699491SMichael Ellerman return -1; 317f2699491SMichael Ellerman 318f2699491SMichael Ellerman /* First see if the events will go on as-is */ 319f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 320f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 321f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 322f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 323f2699491SMichael Ellerman cpuhw->alternatives[i]); 324f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 325f2699491SMichael Ellerman } 326f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 327f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 328f2699491SMichael Ellerman return -1; 329f2699491SMichael Ellerman } 330f2699491SMichael Ellerman value = mask = 0; 331f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 332f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 333f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 334f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) != 0 || 335f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][0]) & 336f2699491SMichael Ellerman cpuhw->amasks[i][0]) != 0) 337f2699491SMichael Ellerman break; 338f2699491SMichael Ellerman value = nv; 339f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 340f2699491SMichael Ellerman } 341f2699491SMichael Ellerman if (i == n_ev) 342f2699491SMichael Ellerman return 0; /* all OK */ 343f2699491SMichael Ellerman 344f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 345f2699491SMichael Ellerman if (!ppmu->get_alternatives) 346f2699491SMichael Ellerman return -1; 347f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 348f2699491SMichael Ellerman choice[i] = 0; 349f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 350f2699491SMichael Ellerman cpuhw->alternatives[i]); 351f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 352f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 353f2699491SMichael Ellerman &cpuhw->amasks[i][j], 354f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 355f2699491SMichael Ellerman } 356f2699491SMichael Ellerman 357f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 358f2699491SMichael Ellerman i = 0; 359f2699491SMichael Ellerman j = -1; 360f2699491SMichael Ellerman value = mask = nv = 0; 361f2699491SMichael Ellerman while (i < n_ev) { 362f2699491SMichael Ellerman if (j >= 0) { 363f2699491SMichael Ellerman /* we're backtracking, restore context */ 364f2699491SMichael Ellerman value = svalues[i]; 365f2699491SMichael Ellerman mask = smasks[i]; 366f2699491SMichael Ellerman j = choice[i]; 367f2699491SMichael Ellerman } 368f2699491SMichael Ellerman /* 369f2699491SMichael Ellerman * See if any alternative k for event_id i, 370f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 371f2699491SMichael Ellerman */ 372f2699491SMichael Ellerman while (++j < n_alt[i]) { 373f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 374f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 375f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 376f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 377f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 378f2699491SMichael Ellerman break; 379f2699491SMichael Ellerman } 380f2699491SMichael Ellerman if (j >= n_alt[i]) { 381f2699491SMichael Ellerman /* 382f2699491SMichael Ellerman * No feasible alternative, backtrack 383f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 384f2699491SMichael Ellerman * alternatives from where we got up to. 385f2699491SMichael Ellerman */ 386f2699491SMichael Ellerman if (--i < 0) 387f2699491SMichael Ellerman return -1; 388f2699491SMichael Ellerman } else { 389f2699491SMichael Ellerman /* 390f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 391f2699491SMichael Ellerman * remember where we got up to with this event_id, 392f2699491SMichael Ellerman * go on to the next event_id, and start with 393f2699491SMichael Ellerman * the first alternative for it. 394f2699491SMichael Ellerman */ 395f2699491SMichael Ellerman choice[i] = j; 396f2699491SMichael Ellerman svalues[i] = value; 397f2699491SMichael Ellerman smasks[i] = mask; 398f2699491SMichael Ellerman value = nv; 399f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 400f2699491SMichael Ellerman ++i; 401f2699491SMichael Ellerman j = -1; 402f2699491SMichael Ellerman } 403f2699491SMichael Ellerman } 404f2699491SMichael Ellerman 405f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 406f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 407f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 408f2699491SMichael Ellerman return 0; 409f2699491SMichael Ellerman } 410f2699491SMichael Ellerman 411f2699491SMichael Ellerman /* 412f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 413f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 414f2699491SMichael Ellerman * added events. 415f2699491SMichael Ellerman */ 416f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 417f2699491SMichael Ellerman int n_prev, int n_new) 418f2699491SMichael Ellerman { 419f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 420f2699491SMichael Ellerman int i, n, first; 421f2699491SMichael Ellerman struct perf_event *event; 422f2699491SMichael Ellerman 423f2699491SMichael Ellerman n = n_prev + n_new; 424f2699491SMichael Ellerman if (n <= 1) 425f2699491SMichael Ellerman return 0; 426f2699491SMichael Ellerman 427f2699491SMichael Ellerman first = 1; 428f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 429f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 430f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 431f2699491SMichael Ellerman continue; 432f2699491SMichael Ellerman } 433f2699491SMichael Ellerman event = ctrs[i]; 434f2699491SMichael Ellerman if (first) { 435f2699491SMichael Ellerman eu = event->attr.exclude_user; 436f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 437f2699491SMichael Ellerman eh = event->attr.exclude_hv; 438f2699491SMichael Ellerman first = 0; 439f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 440f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 441f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 442f2699491SMichael Ellerman return -EAGAIN; 443f2699491SMichael Ellerman } 444f2699491SMichael Ellerman } 445f2699491SMichael Ellerman 446f2699491SMichael Ellerman if (eu || ek || eh) 447f2699491SMichael Ellerman for (i = 0; i < n; ++i) 448f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 449f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 450f2699491SMichael Ellerman 451f2699491SMichael Ellerman return 0; 452f2699491SMichael Ellerman } 453f2699491SMichael Ellerman 454f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 455f2699491SMichael Ellerman { 456f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 457f2699491SMichael Ellerman 458f2699491SMichael Ellerman /* 459f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 460f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 461f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 462f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 463f2699491SMichael Ellerman * number of events to rollback at once. If we dectect a rollback 464f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 465f2699491SMichael Ellerman * counters. 466f2699491SMichael Ellerman */ 467f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 468f2699491SMichael Ellerman delta = 0; 469f2699491SMichael Ellerman 470f2699491SMichael Ellerman return delta; 471f2699491SMichael Ellerman } 472f2699491SMichael Ellerman 473f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 474f2699491SMichael Ellerman { 475f2699491SMichael Ellerman s64 val, delta, prev; 476f2699491SMichael Ellerman 477f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 478f2699491SMichael Ellerman return; 479f2699491SMichael Ellerman 480f2699491SMichael Ellerman if (!event->hw.idx) 481f2699491SMichael Ellerman return; 482f2699491SMichael Ellerman /* 483f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 484f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 485f2699491SMichael Ellerman * Therefore we treat them like NMIs. 486f2699491SMichael Ellerman */ 487f2699491SMichael Ellerman do { 488f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 489f2699491SMichael Ellerman barrier(); 490f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 491f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 492f2699491SMichael Ellerman if (!delta) 493f2699491SMichael Ellerman return; 494f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 495f2699491SMichael Ellerman 496f2699491SMichael Ellerman local64_add(delta, &event->count); 497f2699491SMichael Ellerman local64_sub(delta, &event->hw.period_left); 498f2699491SMichael Ellerman } 499f2699491SMichael Ellerman 500f2699491SMichael Ellerman /* 501f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 502f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 503f2699491SMichael Ellerman * us if `event' is using such a PMC. 504f2699491SMichael Ellerman */ 505f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 506f2699491SMichael Ellerman { 507f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 508f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 509f2699491SMichael Ellerman } 510f2699491SMichael Ellerman 511f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 512f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 513f2699491SMichael Ellerman { 514f2699491SMichael Ellerman struct perf_event *event; 515f2699491SMichael Ellerman u64 val, prev, delta; 516f2699491SMichael Ellerman int i; 517f2699491SMichael Ellerman 518f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 519f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 520f2699491SMichael Ellerman if (!event->hw.idx) 521f2699491SMichael Ellerman continue; 522f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 523f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 524f2699491SMichael Ellerman event->hw.idx = 0; 525f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 526f2699491SMichael Ellerman if (delta) 527f2699491SMichael Ellerman local64_add(delta, &event->count); 528f2699491SMichael Ellerman } 529f2699491SMichael Ellerman } 530f2699491SMichael Ellerman 531f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 532f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 533f2699491SMichael Ellerman { 534f2699491SMichael Ellerman struct perf_event *event; 535f2699491SMichael Ellerman u64 val, prev; 536f2699491SMichael Ellerman int i; 537f2699491SMichael Ellerman 538f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 539f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 540f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 541f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 542f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 543f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 544f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 545f2699491SMichael Ellerman perf_event_update_userpage(event); 546f2699491SMichael Ellerman } 547f2699491SMichael Ellerman } 548f2699491SMichael Ellerman 549f2699491SMichael Ellerman /* 550f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 551f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 552f2699491SMichael Ellerman * other events. We try to keep the values from the limited 553f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 554f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 555f2699491SMichael Ellerman * the limited events as small and consistent as possible. 556f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 557f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 558f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 559f2699491SMichael Ellerman */ 560f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 561f2699491SMichael Ellerman { 562f2699491SMichael Ellerman unsigned long pmc5, pmc6; 563f2699491SMichael Ellerman 564f2699491SMichael Ellerman if (!cpuhw->n_limited) { 565f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 566f2699491SMichael Ellerman return; 567f2699491SMichael Ellerman } 568f2699491SMichael Ellerman 569f2699491SMichael Ellerman /* 570f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 571f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 572f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 573f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 574f2699491SMichael Ellerman * interrupt enable bits turned off. 575f2699491SMichael Ellerman */ 576f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 577f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 578f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 579f2699491SMichael Ellerman "i" (SPRN_MMCR0), 580f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 581f2699491SMichael Ellerman 582f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 583f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 584f2699491SMichael Ellerman else 585f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 586f2699491SMichael Ellerman 587f2699491SMichael Ellerman /* 588f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 589f2699491SMichael Ellerman * enable bits, if necessary. 590f2699491SMichael Ellerman */ 591f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 592f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 593f2699491SMichael Ellerman } 594f2699491SMichael Ellerman 595f2699491SMichael Ellerman /* 596f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 597f2699491SMichael Ellerman * events to be added or removed. 598f2699491SMichael Ellerman */ 599f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 600f2699491SMichael Ellerman { 601f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 602f2699491SMichael Ellerman unsigned long flags; 603f2699491SMichael Ellerman 604f2699491SMichael Ellerman if (!ppmu) 605f2699491SMichael Ellerman return; 606f2699491SMichael Ellerman local_irq_save(flags); 607f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 608f2699491SMichael Ellerman 609f2699491SMichael Ellerman if (!cpuhw->disabled) { 610f2699491SMichael Ellerman cpuhw->disabled = 1; 611f2699491SMichael Ellerman cpuhw->n_added = 0; 612f2699491SMichael Ellerman 613f2699491SMichael Ellerman /* 614f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 615f2699491SMichael Ellerman */ 616f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 617f2699491SMichael Ellerman ppc_enable_pmcs(); 618f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 619f2699491SMichael Ellerman } 620f2699491SMichael Ellerman 621f2699491SMichael Ellerman /* 622f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 623f2699491SMichael Ellerman */ 624f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 625f2699491SMichael Ellerman mtspr(SPRN_MMCRA, 626f2699491SMichael Ellerman cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 627f2699491SMichael Ellerman mb(); 628f2699491SMichael Ellerman } 629f2699491SMichael Ellerman 630f2699491SMichael Ellerman /* 631f2699491SMichael Ellerman * Set the 'freeze counters' bit. 632f2699491SMichael Ellerman * The barrier is to make sure the mtspr has been 633f2699491SMichael Ellerman * executed and the PMU has frozen the events 634f2699491SMichael Ellerman * before we return. 635f2699491SMichael Ellerman */ 636f2699491SMichael Ellerman write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); 637f2699491SMichael Ellerman mb(); 638f2699491SMichael Ellerman } 639f2699491SMichael Ellerman local_irq_restore(flags); 640f2699491SMichael Ellerman } 641f2699491SMichael Ellerman 642f2699491SMichael Ellerman /* 643f2699491SMichael Ellerman * Re-enable all events if disable == 0. 644f2699491SMichael Ellerman * If we were previously disabled and events were added, then 645f2699491SMichael Ellerman * put the new config on the PMU. 646f2699491SMichael Ellerman */ 647f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 648f2699491SMichael Ellerman { 649f2699491SMichael Ellerman struct perf_event *event; 650f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 651f2699491SMichael Ellerman unsigned long flags; 652f2699491SMichael Ellerman long i; 653f2699491SMichael Ellerman unsigned long val; 654f2699491SMichael Ellerman s64 left; 655f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 656f2699491SMichael Ellerman int n_lim; 657f2699491SMichael Ellerman int idx; 658f2699491SMichael Ellerman 659f2699491SMichael Ellerman if (!ppmu) 660f2699491SMichael Ellerman return; 661f2699491SMichael Ellerman local_irq_save(flags); 662f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 663f2699491SMichael Ellerman if (!cpuhw->disabled) { 664f2699491SMichael Ellerman local_irq_restore(flags); 665f2699491SMichael Ellerman return; 666f2699491SMichael Ellerman } 667f2699491SMichael Ellerman cpuhw->disabled = 0; 668f2699491SMichael Ellerman 669f2699491SMichael Ellerman /* 670f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 671f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 672f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 673f2699491SMichael Ellerman * (possibly updated for removal of events). 674f2699491SMichael Ellerman */ 675f2699491SMichael Ellerman if (!cpuhw->n_added) { 676f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 677f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 678f2699491SMichael Ellerman if (cpuhw->n_events == 0) 679f2699491SMichael Ellerman ppc_set_pmu_inuse(0); 680f2699491SMichael Ellerman goto out_enable; 681f2699491SMichael Ellerman } 682f2699491SMichael Ellerman 683f2699491SMichael Ellerman /* 684f2699491SMichael Ellerman * Compute MMCR* values for the new set of events 685f2699491SMichael Ellerman */ 686f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 687f2699491SMichael Ellerman cpuhw->mmcr)) { 688f2699491SMichael Ellerman /* shouldn't ever get here */ 689f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 690f2699491SMichael Ellerman goto out; 691f2699491SMichael Ellerman } 692f2699491SMichael Ellerman 693f2699491SMichael Ellerman /* 694f2699491SMichael Ellerman * Add in MMCR0 freeze bits corresponding to the 695f2699491SMichael Ellerman * attr.exclude_* bits for the first event. 696f2699491SMichael Ellerman * We have already checked that all events have the 697f2699491SMichael Ellerman * same values for these bits as the first event. 698f2699491SMichael Ellerman */ 699f2699491SMichael Ellerman event = cpuhw->event[0]; 700f2699491SMichael Ellerman if (event->attr.exclude_user) 701f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCP; 702f2699491SMichael Ellerman if (event->attr.exclude_kernel) 703f2699491SMichael Ellerman cpuhw->mmcr[0] |= freeze_events_kernel; 704f2699491SMichael Ellerman if (event->attr.exclude_hv) 705f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCHV; 706f2699491SMichael Ellerman 707f2699491SMichael Ellerman /* 708f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 709f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 710f2699491SMichael Ellerman * Then unfreeze the events. 711f2699491SMichael Ellerman */ 712f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 713f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 714f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 715f2699491SMichael Ellerman mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 716f2699491SMichael Ellerman | MMCR0_FC); 717f2699491SMichael Ellerman 718f2699491SMichael Ellerman /* 719f2699491SMichael Ellerman * Read off any pre-existing events that need to move 720f2699491SMichael Ellerman * to another PMC. 721f2699491SMichael Ellerman */ 722f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 723f2699491SMichael Ellerman event = cpuhw->event[i]; 724f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 725f2699491SMichael Ellerman power_pmu_read(event); 726f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 727f2699491SMichael Ellerman event->hw.idx = 0; 728f2699491SMichael Ellerman } 729f2699491SMichael Ellerman } 730f2699491SMichael Ellerman 731f2699491SMichael Ellerman /* 732f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 733f2699491SMichael Ellerman */ 734f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 735f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 736f2699491SMichael Ellerman event = cpuhw->event[i]; 737f2699491SMichael Ellerman if (event->hw.idx) 738f2699491SMichael Ellerman continue; 739f2699491SMichael Ellerman idx = hwc_index[i] + 1; 740f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 741f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 742f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 743f2699491SMichael Ellerman ++n_lim; 744f2699491SMichael Ellerman continue; 745f2699491SMichael Ellerman } 746f2699491SMichael Ellerman val = 0; 747f2699491SMichael Ellerman if (event->hw.sample_period) { 748f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 749f2699491SMichael Ellerman if (left < 0x80000000L) 750f2699491SMichael Ellerman val = 0x80000000L - left; 751f2699491SMichael Ellerman } 752f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 753f2699491SMichael Ellerman event->hw.idx = idx; 754f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 755f2699491SMichael Ellerman val = 0; 756f2699491SMichael Ellerman write_pmc(idx, val); 757f2699491SMichael Ellerman perf_event_update_userpage(event); 758f2699491SMichael Ellerman } 759f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 760f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 761f2699491SMichael Ellerman 762f2699491SMichael Ellerman out_enable: 763f2699491SMichael Ellerman mb(); 764f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 765f2699491SMichael Ellerman 766f2699491SMichael Ellerman /* 767f2699491SMichael Ellerman * Enable instruction sampling if necessary 768f2699491SMichael Ellerman */ 769f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 770f2699491SMichael Ellerman mb(); 771f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 772f2699491SMichael Ellerman } 773f2699491SMichael Ellerman 774f2699491SMichael Ellerman out: 775f2699491SMichael Ellerman local_irq_restore(flags); 776f2699491SMichael Ellerman } 777f2699491SMichael Ellerman 778f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 779f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 780f2699491SMichael Ellerman unsigned int *flags) 781f2699491SMichael Ellerman { 782f2699491SMichael Ellerman int n = 0; 783f2699491SMichael Ellerman struct perf_event *event; 784f2699491SMichael Ellerman 785f2699491SMichael Ellerman if (!is_software_event(group)) { 786f2699491SMichael Ellerman if (n >= max_count) 787f2699491SMichael Ellerman return -1; 788f2699491SMichael Ellerman ctrs[n] = group; 789f2699491SMichael Ellerman flags[n] = group->hw.event_base; 790f2699491SMichael Ellerman events[n++] = group->hw.config; 791f2699491SMichael Ellerman } 792f2699491SMichael Ellerman list_for_each_entry(event, &group->sibling_list, group_entry) { 793f2699491SMichael Ellerman if (!is_software_event(event) && 794f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 795f2699491SMichael Ellerman if (n >= max_count) 796f2699491SMichael Ellerman return -1; 797f2699491SMichael Ellerman ctrs[n] = event; 798f2699491SMichael Ellerman flags[n] = event->hw.event_base; 799f2699491SMichael Ellerman events[n++] = event->hw.config; 800f2699491SMichael Ellerman } 801f2699491SMichael Ellerman } 802f2699491SMichael Ellerman return n; 803f2699491SMichael Ellerman } 804f2699491SMichael Ellerman 805f2699491SMichael Ellerman /* 806f2699491SMichael Ellerman * Add a event to the PMU. 807f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 808f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 809f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 810f2699491SMichael Ellerman */ 811f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 812f2699491SMichael Ellerman { 813f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 814f2699491SMichael Ellerman unsigned long flags; 815f2699491SMichael Ellerman int n0; 816f2699491SMichael Ellerman int ret = -EAGAIN; 817f2699491SMichael Ellerman 818f2699491SMichael Ellerman local_irq_save(flags); 819f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 820f2699491SMichael Ellerman 821f2699491SMichael Ellerman /* 822f2699491SMichael Ellerman * Add the event to the list (if there is room) 823f2699491SMichael Ellerman * and check whether the total set is still feasible. 824f2699491SMichael Ellerman */ 825f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 826f2699491SMichael Ellerman n0 = cpuhw->n_events; 827f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 828f2699491SMichael Ellerman goto out; 829f2699491SMichael Ellerman cpuhw->event[n0] = event; 830f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 831f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 832f2699491SMichael Ellerman 833f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 834f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 835f2699491SMichael Ellerman 836f2699491SMichael Ellerman /* 837f2699491SMichael Ellerman * If group events scheduling transaction was started, 838f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 839f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 840f2699491SMichael Ellerman */ 841f2699491SMichael Ellerman if (cpuhw->group_flag & PERF_EVENT_TXN) 842f2699491SMichael Ellerman goto nocheck; 843f2699491SMichael Ellerman 844f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 845f2699491SMichael Ellerman goto out; 846f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 847f2699491SMichael Ellerman goto out; 848f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 849f2699491SMichael Ellerman 850f2699491SMichael Ellerman nocheck: 851f2699491SMichael Ellerman ++cpuhw->n_events; 852f2699491SMichael Ellerman ++cpuhw->n_added; 853f2699491SMichael Ellerman 854f2699491SMichael Ellerman ret = 0; 855f2699491SMichael Ellerman out: 856f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 857f2699491SMichael Ellerman local_irq_restore(flags); 858f2699491SMichael Ellerman return ret; 859f2699491SMichael Ellerman } 860f2699491SMichael Ellerman 861f2699491SMichael Ellerman /* 862f2699491SMichael Ellerman * Remove a event from the PMU. 863f2699491SMichael Ellerman */ 864f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 865f2699491SMichael Ellerman { 866f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 867f2699491SMichael Ellerman long i; 868f2699491SMichael Ellerman unsigned long flags; 869f2699491SMichael Ellerman 870f2699491SMichael Ellerman local_irq_save(flags); 871f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 872f2699491SMichael Ellerman 873f2699491SMichael Ellerman power_pmu_read(event); 874f2699491SMichael Ellerman 875f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 876f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 877f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 878f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 879f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 880f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 881f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 882f2699491SMichael Ellerman } 883f2699491SMichael Ellerman --cpuhw->n_events; 884f2699491SMichael Ellerman ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 885f2699491SMichael Ellerman if (event->hw.idx) { 886f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 887f2699491SMichael Ellerman event->hw.idx = 0; 888f2699491SMichael Ellerman } 889f2699491SMichael Ellerman perf_event_update_userpage(event); 890f2699491SMichael Ellerman break; 891f2699491SMichael Ellerman } 892f2699491SMichael Ellerman } 893f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 894f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 895f2699491SMichael Ellerman break; 896f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 897f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 898f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 899f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 900f2699491SMichael Ellerman } 901f2699491SMichael Ellerman --cpuhw->n_limited; 902f2699491SMichael Ellerman } 903f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 904f2699491SMichael Ellerman /* disable exceptions if no events are running */ 905f2699491SMichael Ellerman cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 906f2699491SMichael Ellerman } 907f2699491SMichael Ellerman 908f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 909f2699491SMichael Ellerman local_irq_restore(flags); 910f2699491SMichael Ellerman } 911f2699491SMichael Ellerman 912f2699491SMichael Ellerman /* 913f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 914f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 915f2699491SMichael Ellerman */ 916f2699491SMichael Ellerman 917f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 918f2699491SMichael Ellerman { 919f2699491SMichael Ellerman unsigned long flags; 920f2699491SMichael Ellerman s64 left; 921f2699491SMichael Ellerman unsigned long val; 922f2699491SMichael Ellerman 923f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 924f2699491SMichael Ellerman return; 925f2699491SMichael Ellerman 926f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 927f2699491SMichael Ellerman return; 928f2699491SMichael Ellerman 929f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 930f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 931f2699491SMichael Ellerman 932f2699491SMichael Ellerman local_irq_save(flags); 933f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 934f2699491SMichael Ellerman 935f2699491SMichael Ellerman event->hw.state = 0; 936f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 937f2699491SMichael Ellerman 938f2699491SMichael Ellerman val = 0; 939f2699491SMichael Ellerman if (left < 0x80000000L) 940f2699491SMichael Ellerman val = 0x80000000L - left; 941f2699491SMichael Ellerman 942f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 943f2699491SMichael Ellerman 944f2699491SMichael Ellerman perf_event_update_userpage(event); 945f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 946f2699491SMichael Ellerman local_irq_restore(flags); 947f2699491SMichael Ellerman } 948f2699491SMichael Ellerman 949f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 950f2699491SMichael Ellerman { 951f2699491SMichael Ellerman unsigned long flags; 952f2699491SMichael Ellerman 953f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 954f2699491SMichael Ellerman return; 955f2699491SMichael Ellerman 956f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 957f2699491SMichael Ellerman return; 958f2699491SMichael Ellerman 959f2699491SMichael Ellerman local_irq_save(flags); 960f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 961f2699491SMichael Ellerman 962f2699491SMichael Ellerman power_pmu_read(event); 963f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 964f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 965f2699491SMichael Ellerman 966f2699491SMichael Ellerman perf_event_update_userpage(event); 967f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 968f2699491SMichael Ellerman local_irq_restore(flags); 969f2699491SMichael Ellerman } 970f2699491SMichael Ellerman 971f2699491SMichael Ellerman /* 972f2699491SMichael Ellerman * Start group events scheduling transaction 973f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 974f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 975f2699491SMichael Ellerman */ 976f2699491SMichael Ellerman void power_pmu_start_txn(struct pmu *pmu) 977f2699491SMichael Ellerman { 978f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 979f2699491SMichael Ellerman 980f2699491SMichael Ellerman perf_pmu_disable(pmu); 981f2699491SMichael Ellerman cpuhw->group_flag |= PERF_EVENT_TXN; 982f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 983f2699491SMichael Ellerman } 984f2699491SMichael Ellerman 985f2699491SMichael Ellerman /* 986f2699491SMichael Ellerman * Stop group events scheduling transaction 987f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 988f2699491SMichael Ellerman * schedulability test. 989f2699491SMichael Ellerman */ 990f2699491SMichael Ellerman void power_pmu_cancel_txn(struct pmu *pmu) 991f2699491SMichael Ellerman { 992f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 993f2699491SMichael Ellerman 994f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 995f2699491SMichael Ellerman perf_pmu_enable(pmu); 996f2699491SMichael Ellerman } 997f2699491SMichael Ellerman 998f2699491SMichael Ellerman /* 999f2699491SMichael Ellerman * Commit group events scheduling transaction 1000f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1001f2699491SMichael Ellerman * Return 0 if success 1002f2699491SMichael Ellerman */ 1003f2699491SMichael Ellerman int power_pmu_commit_txn(struct pmu *pmu) 1004f2699491SMichael Ellerman { 1005f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1006f2699491SMichael Ellerman long i, n; 1007f2699491SMichael Ellerman 1008f2699491SMichael Ellerman if (!ppmu) 1009f2699491SMichael Ellerman return -EAGAIN; 1010f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1011f2699491SMichael Ellerman n = cpuhw->n_events; 1012f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1013f2699491SMichael Ellerman return -EAGAIN; 1014f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1015f2699491SMichael Ellerman if (i < 0) 1016f2699491SMichael Ellerman return -EAGAIN; 1017f2699491SMichael Ellerman 1018f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1019f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1020f2699491SMichael Ellerman 1021f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1022f2699491SMichael Ellerman perf_pmu_enable(pmu); 1023f2699491SMichael Ellerman return 0; 1024f2699491SMichael Ellerman } 1025f2699491SMichael Ellerman 1026f2699491SMichael Ellerman /* 1027f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1028f2699491SMichael Ellerman * or 0 if not. 1029f2699491SMichael Ellerman * A event can only go on a limited PMC if it counts something 1030f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1031f2699491SMichael Ellerman * doesn't exclude any processor mode. 1032f2699491SMichael Ellerman */ 1033f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1034f2699491SMichael Ellerman unsigned int flags) 1035f2699491SMichael Ellerman { 1036f2699491SMichael Ellerman int n; 1037f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1038f2699491SMichael Ellerman 1039f2699491SMichael Ellerman if (event->attr.exclude_user 1040f2699491SMichael Ellerman || event->attr.exclude_kernel 1041f2699491SMichael Ellerman || event->attr.exclude_hv 1042f2699491SMichael Ellerman || event->attr.sample_period) 1043f2699491SMichael Ellerman return 0; 1044f2699491SMichael Ellerman 1045f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1046f2699491SMichael Ellerman return 1; 1047f2699491SMichael Ellerman 1048f2699491SMichael Ellerman /* 1049f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1050f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1051f2699491SMichael Ellerman */ 1052f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1053f2699491SMichael Ellerman return 0; 1054f2699491SMichael Ellerman 1055f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1056f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1057f2699491SMichael Ellerman 1058f2699491SMichael Ellerman return n > 0; 1059f2699491SMichael Ellerman } 1060f2699491SMichael Ellerman 1061f2699491SMichael Ellerman /* 1062f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1063f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1064f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1065f2699491SMichael Ellerman */ 1066f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1067f2699491SMichael Ellerman { 1068f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1069f2699491SMichael Ellerman int n; 1070f2699491SMichael Ellerman 1071f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1072f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1073f2699491SMichael Ellerman if (!n) 1074f2699491SMichael Ellerman return 0; 1075f2699491SMichael Ellerman return alt[0]; 1076f2699491SMichael Ellerman } 1077f2699491SMichael Ellerman 1078f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1079f2699491SMichael Ellerman static atomic_t num_events; 1080f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1081f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1082f2699491SMichael Ellerman 1083f2699491SMichael Ellerman /* 1084f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1085f2699491SMichael Ellerman */ 1086f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1087f2699491SMichael Ellerman { 1088f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1089f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1090f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1091f2699491SMichael Ellerman release_pmc_hardware(); 1092f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1093f2699491SMichael Ellerman } 1094f2699491SMichael Ellerman } 1095f2699491SMichael Ellerman 1096f2699491SMichael Ellerman /* 1097f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1098f2699491SMichael Ellerman */ 1099f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1100f2699491SMichael Ellerman { 1101f2699491SMichael Ellerman unsigned long type, op, result; 1102f2699491SMichael Ellerman int ev; 1103f2699491SMichael Ellerman 1104f2699491SMichael Ellerman if (!ppmu->cache_events) 1105f2699491SMichael Ellerman return -EINVAL; 1106f2699491SMichael Ellerman 1107f2699491SMichael Ellerman /* unpack config */ 1108f2699491SMichael Ellerman type = config & 0xff; 1109f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1110f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1111f2699491SMichael Ellerman 1112f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1113f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1114f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1115f2699491SMichael Ellerman return -EINVAL; 1116f2699491SMichael Ellerman 1117f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1118f2699491SMichael Ellerman if (ev == 0) 1119f2699491SMichael Ellerman return -EOPNOTSUPP; 1120f2699491SMichael Ellerman if (ev == -1) 1121f2699491SMichael Ellerman return -EINVAL; 1122f2699491SMichael Ellerman *eventp = ev; 1123f2699491SMichael Ellerman return 0; 1124f2699491SMichael Ellerman } 1125f2699491SMichael Ellerman 1126f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1127f2699491SMichael Ellerman { 1128f2699491SMichael Ellerman u64 ev; 1129f2699491SMichael Ellerman unsigned long flags; 1130f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1131f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1132f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1133f2699491SMichael Ellerman int n; 1134f2699491SMichael Ellerman int err; 1135f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1136f2699491SMichael Ellerman 1137f2699491SMichael Ellerman if (!ppmu) 1138f2699491SMichael Ellerman return -ENOENT; 1139f2699491SMichael Ellerman 11405375871dSLinus Torvalds /* does not support taken branch sampling */ 11415375871dSLinus Torvalds if (has_branch_stack(event)) 11425375871dSLinus Torvalds return -EOPNOTSUPP; 11435375871dSLinus Torvalds 1144f2699491SMichael Ellerman switch (event->attr.type) { 1145f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1146f2699491SMichael Ellerman ev = event->attr.config; 1147f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1148f2699491SMichael Ellerman return -EOPNOTSUPP; 1149f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1150f2699491SMichael Ellerman break; 1151f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1152f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1153f2699491SMichael Ellerman if (err) 1154f2699491SMichael Ellerman return err; 1155f2699491SMichael Ellerman break; 1156f2699491SMichael Ellerman case PERF_TYPE_RAW: 1157f2699491SMichael Ellerman ev = event->attr.config; 1158f2699491SMichael Ellerman break; 1159f2699491SMichael Ellerman default: 1160f2699491SMichael Ellerman return -ENOENT; 1161f2699491SMichael Ellerman } 1162f2699491SMichael Ellerman 1163f2699491SMichael Ellerman event->hw.config_base = ev; 1164f2699491SMichael Ellerman event->hw.idx = 0; 1165f2699491SMichael Ellerman 1166f2699491SMichael Ellerman /* 1167f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1168f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1169f2699491SMichael Ellerman * the user set it to. 1170f2699491SMichael Ellerman */ 1171f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1172f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1173f2699491SMichael Ellerman 1174f2699491SMichael Ellerman /* 1175f2699491SMichael Ellerman * If this is a per-task event, then we can use 1176f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1177f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1178f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1179f2699491SMichael Ellerman */ 1180f2699491SMichael Ellerman flags = 0; 1181f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1182f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1183f2699491SMichael Ellerman 1184f2699491SMichael Ellerman /* 1185f2699491SMichael Ellerman * If this machine has limited events, check whether this 1186f2699491SMichael Ellerman * event_id could go on a limited event. 1187f2699491SMichael Ellerman */ 1188f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1189f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1190f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1191f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1192f2699491SMichael Ellerman /* 1193f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1194f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1195f2699491SMichael Ellerman * alternative goes on a normal PMC. 1196f2699491SMichael Ellerman */ 1197f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1198f2699491SMichael Ellerman if (!ev) 1199f2699491SMichael Ellerman return -EINVAL; 1200f2699491SMichael Ellerman } 1201f2699491SMichael Ellerman } 1202f2699491SMichael Ellerman 1203f2699491SMichael Ellerman /* 1204f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1205f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1206f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1207f2699491SMichael Ellerman */ 1208f2699491SMichael Ellerman n = 0; 1209f2699491SMichael Ellerman if (event->group_leader != event) { 1210f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1211f2699491SMichael Ellerman ctrs, events, cflags); 1212f2699491SMichael Ellerman if (n < 0) 1213f2699491SMichael Ellerman return -EINVAL; 1214f2699491SMichael Ellerman } 1215f2699491SMichael Ellerman events[n] = ev; 1216f2699491SMichael Ellerman ctrs[n] = event; 1217f2699491SMichael Ellerman cflags[n] = flags; 1218f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1219f2699491SMichael Ellerman return -EINVAL; 1220f2699491SMichael Ellerman 1221f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1222f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 1223f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 1224f2699491SMichael Ellerman if (err) 1225f2699491SMichael Ellerman return -EINVAL; 1226f2699491SMichael Ellerman 1227f2699491SMichael Ellerman event->hw.config = events[n]; 1228f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 1229f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1230f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 1231f2699491SMichael Ellerman 1232f2699491SMichael Ellerman /* 1233f2699491SMichael Ellerman * See if we need to reserve the PMU. 1234f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 1235f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 1236f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 1237f2699491SMichael Ellerman */ 1238f2699491SMichael Ellerman err = 0; 1239f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 1240f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1241f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 1242f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 1243f2699491SMichael Ellerman err = -EBUSY; 1244f2699491SMichael Ellerman else 1245f2699491SMichael Ellerman atomic_inc(&num_events); 1246f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1247f2699491SMichael Ellerman } 1248f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 1249f2699491SMichael Ellerman 1250f2699491SMichael Ellerman return err; 1251f2699491SMichael Ellerman } 1252f2699491SMichael Ellerman 12535375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 12545375871dSLinus Torvalds { 12555375871dSLinus Torvalds return event->hw.idx; 12565375871dSLinus Torvalds } 12575375871dSLinus Torvalds 1258f2699491SMichael Ellerman struct pmu power_pmu = { 1259f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 1260f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 1261f2699491SMichael Ellerman .event_init = power_pmu_event_init, 1262f2699491SMichael Ellerman .add = power_pmu_add, 1263f2699491SMichael Ellerman .del = power_pmu_del, 1264f2699491SMichael Ellerman .start = power_pmu_start, 1265f2699491SMichael Ellerman .stop = power_pmu_stop, 1266f2699491SMichael Ellerman .read = power_pmu_read, 1267f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 1268f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 1269f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 12705375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 1271f2699491SMichael Ellerman }; 1272f2699491SMichael Ellerman 1273f2699491SMichael Ellerman /* 1274f2699491SMichael Ellerman * A counter has overflowed; update its count and record 1275f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 1276f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 1277f2699491SMichael Ellerman */ 1278f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 1279f2699491SMichael Ellerman struct pt_regs *regs) 1280f2699491SMichael Ellerman { 1281f2699491SMichael Ellerman u64 period = event->hw.sample_period; 1282f2699491SMichael Ellerman s64 prev, delta, left; 1283f2699491SMichael Ellerman int record = 0; 1284f2699491SMichael Ellerman 1285f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 1286f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1287f2699491SMichael Ellerman return; 1288f2699491SMichael Ellerman } 1289f2699491SMichael Ellerman 1290f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 1291f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1292f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1293f2699491SMichael Ellerman local64_add(delta, &event->count); 1294f2699491SMichael Ellerman 1295f2699491SMichael Ellerman /* 1296f2699491SMichael Ellerman * See if the total period for this event has expired, 1297f2699491SMichael Ellerman * and update for the next period. 1298f2699491SMichael Ellerman */ 1299f2699491SMichael Ellerman val = 0; 1300f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 1301f2699491SMichael Ellerman if (period) { 1302f2699491SMichael Ellerman if (left <= 0) { 1303f2699491SMichael Ellerman left += period; 1304f2699491SMichael Ellerman if (left <= 0) 1305f2699491SMichael Ellerman left = period; 1306f2699491SMichael Ellerman record = 1; 1307f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1308f2699491SMichael Ellerman } 1309f2699491SMichael Ellerman if (left < 0x80000000LL) 1310f2699491SMichael Ellerman val = 0x80000000LL - left; 1311f2699491SMichael Ellerman } 1312f2699491SMichael Ellerman 1313f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1314f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1315f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 1316f2699491SMichael Ellerman perf_event_update_userpage(event); 1317f2699491SMichael Ellerman 1318f2699491SMichael Ellerman /* 1319f2699491SMichael Ellerman * Finally record data if requested. 1320f2699491SMichael Ellerman */ 1321f2699491SMichael Ellerman if (record) { 1322f2699491SMichael Ellerman struct perf_sample_data data; 1323f2699491SMichael Ellerman 1324fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 1325f2699491SMichael Ellerman 1326f2699491SMichael Ellerman if (event->attr.sample_type & PERF_SAMPLE_ADDR) 1327f2699491SMichael Ellerman perf_get_data_addr(regs, &data.addr); 1328f2699491SMichael Ellerman 1329f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 1330f2699491SMichael Ellerman power_pmu_stop(event, 0); 1331f2699491SMichael Ellerman } 1332f2699491SMichael Ellerman } 1333f2699491SMichael Ellerman 1334f2699491SMichael Ellerman /* 1335f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 1336f2699491SMichael Ellerman * for an event_id. 1337f2699491SMichael Ellerman */ 1338f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 1339f2699491SMichael Ellerman { 1340f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 1341f2699491SMichael Ellerman 1342f2699491SMichael Ellerman if (flags) 1343f2699491SMichael Ellerman return flags; 1344f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 1345f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 1346f2699491SMichael Ellerman } 1347f2699491SMichael Ellerman 1348f2699491SMichael Ellerman /* 1349f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 1350f2699491SMichael Ellerman * for an event_id. 1351f2699491SMichael Ellerman */ 1352f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 1353f2699491SMichael Ellerman { 135475382aa7SAnton Blanchard unsigned long use_siar = regs->result; 1355f2699491SMichael Ellerman 135675382aa7SAnton Blanchard if (use_siar) 13571ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 135875382aa7SAnton Blanchard else 135975382aa7SAnton Blanchard return regs->nip; 1360f2699491SMichael Ellerman } 1361f2699491SMichael Ellerman 1362f2699491SMichael Ellerman static bool pmc_overflow(unsigned long val) 1363f2699491SMichael Ellerman { 1364f2699491SMichael Ellerman if ((int)val < 0) 1365f2699491SMichael Ellerman return true; 1366f2699491SMichael Ellerman 1367f2699491SMichael Ellerman /* 1368f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 1369f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 1370f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 1371f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 1372f2699491SMichael Ellerman * cycles from overflow. 1373f2699491SMichael Ellerman * 1374f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 1375f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 1376f2699491SMichael Ellerman * don't want to mistakenly reset them. 1377f2699491SMichael Ellerman */ 1378f2699491SMichael Ellerman if (__is_processor(PV_POWER7) && ((0x80000000 - val) <= 256)) 1379f2699491SMichael Ellerman return true; 1380f2699491SMichael Ellerman 1381f2699491SMichael Ellerman return false; 1382f2699491SMichael Ellerman } 1383f2699491SMichael Ellerman 1384f2699491SMichael Ellerman /* 1385f2699491SMichael Ellerman * Performance monitor interrupt stuff 1386f2699491SMichael Ellerman */ 1387f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs) 1388f2699491SMichael Ellerman { 1389f2699491SMichael Ellerman int i; 1390f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1391f2699491SMichael Ellerman struct perf_event *event; 1392f2699491SMichael Ellerman unsigned long val; 1393f2699491SMichael Ellerman int found = 0; 1394f2699491SMichael Ellerman int nmi; 1395f2699491SMichael Ellerman 1396f2699491SMichael Ellerman if (cpuhw->n_limited) 1397f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 1398f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 1399f2699491SMichael Ellerman 1400f2699491SMichael Ellerman perf_read_regs(regs); 1401f2699491SMichael Ellerman 1402f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 1403f2699491SMichael Ellerman if (nmi) 1404f2699491SMichael Ellerman nmi_enter(); 1405f2699491SMichael Ellerman else 1406f2699491SMichael Ellerman irq_enter(); 1407f2699491SMichael Ellerman 1408f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1409f2699491SMichael Ellerman event = cpuhw->event[i]; 1410f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 1411f2699491SMichael Ellerman continue; 1412f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 1413f2699491SMichael Ellerman if ((int)val < 0) { 1414f2699491SMichael Ellerman /* event has overflowed */ 1415f2699491SMichael Ellerman found = 1; 1416f2699491SMichael Ellerman record_and_restart(event, val, regs); 1417f2699491SMichael Ellerman } 1418f2699491SMichael Ellerman } 1419f2699491SMichael Ellerman 1420f2699491SMichael Ellerman /* 1421f2699491SMichael Ellerman * In case we didn't find and reset the event that caused 1422f2699491SMichael Ellerman * the interrupt, scan all events and reset any that are 1423f2699491SMichael Ellerman * negative, to avoid getting continual interrupts. 1424f2699491SMichael Ellerman * Any that we processed in the previous loop will not be negative. 1425f2699491SMichael Ellerman */ 1426f2699491SMichael Ellerman if (!found) { 1427f2699491SMichael Ellerman for (i = 0; i < ppmu->n_counter; ++i) { 1428f2699491SMichael Ellerman if (is_limited_pmc(i + 1)) 1429f2699491SMichael Ellerman continue; 1430f2699491SMichael Ellerman val = read_pmc(i + 1); 1431f2699491SMichael Ellerman if (pmc_overflow(val)) 1432f2699491SMichael Ellerman write_pmc(i + 1, 0); 1433f2699491SMichael Ellerman } 1434f2699491SMichael Ellerman } 1435f2699491SMichael Ellerman 1436f2699491SMichael Ellerman /* 1437f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 1438f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 1439f2699491SMichael Ellerman * and thus allow interrupts to occur again. 1440f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 1441f2699491SMichael Ellerman * we get back out of this interrupt. 1442f2699491SMichael Ellerman */ 1443f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 1444f2699491SMichael Ellerman 1445f2699491SMichael Ellerman if (nmi) 1446f2699491SMichael Ellerman nmi_exit(); 1447f2699491SMichael Ellerman else 1448f2699491SMichael Ellerman irq_exit(); 1449f2699491SMichael Ellerman } 1450f2699491SMichael Ellerman 1451f2699491SMichael Ellerman static void power_pmu_setup(int cpu) 1452f2699491SMichael Ellerman { 1453f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 1454f2699491SMichael Ellerman 1455f2699491SMichael Ellerman if (!ppmu) 1456f2699491SMichael Ellerman return; 1457f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 1458f2699491SMichael Ellerman cpuhw->mmcr[0] = MMCR0_FC; 1459f2699491SMichael Ellerman } 1460f2699491SMichael Ellerman 1461f2699491SMichael Ellerman static int __cpuinit 1462f2699491SMichael Ellerman power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) 1463f2699491SMichael Ellerman { 1464f2699491SMichael Ellerman unsigned int cpu = (long)hcpu; 1465f2699491SMichael Ellerman 1466f2699491SMichael Ellerman switch (action & ~CPU_TASKS_FROZEN) { 1467f2699491SMichael Ellerman case CPU_UP_PREPARE: 1468f2699491SMichael Ellerman power_pmu_setup(cpu); 1469f2699491SMichael Ellerman break; 1470f2699491SMichael Ellerman 1471f2699491SMichael Ellerman default: 1472f2699491SMichael Ellerman break; 1473f2699491SMichael Ellerman } 1474f2699491SMichael Ellerman 1475f2699491SMichael Ellerman return NOTIFY_OK; 1476f2699491SMichael Ellerman } 1477f2699491SMichael Ellerman 1478f2699491SMichael Ellerman int __cpuinit register_power_pmu(struct power_pmu *pmu) 1479f2699491SMichael Ellerman { 1480f2699491SMichael Ellerman if (ppmu) 1481f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 1482f2699491SMichael Ellerman 1483f2699491SMichael Ellerman ppmu = pmu; 1484f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 1485f2699491SMichael Ellerman pmu->name); 1486f2699491SMichael Ellerman 1487f2699491SMichael Ellerman #ifdef MSR_HV 1488f2699491SMichael Ellerman /* 1489f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 1490f2699491SMichael Ellerman */ 1491f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 1492f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 1493f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 1494f2699491SMichael Ellerman 1495f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 1496f2699491SMichael Ellerman perf_cpu_notifier(power_pmu_notifier); 1497f2699491SMichael Ellerman 1498f2699491SMichael Ellerman return 0; 1499f2699491SMichael Ellerman } 1500