1f2699491SMichael Ellerman /* 2f2699491SMichael Ellerman * Performance event support - powerpc architecture code 3f2699491SMichael Ellerman * 4f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5f2699491SMichael Ellerman * 6f2699491SMichael Ellerman * This program is free software; you can redistribute it and/or 7f2699491SMichael Ellerman * modify it under the terms of the GNU General Public License 8f2699491SMichael Ellerman * as published by the Free Software Foundation; either version 9f2699491SMichael Ellerman * 2 of the License, or (at your option) any later version. 10f2699491SMichael Ellerman */ 11f2699491SMichael Ellerman #include <linux/kernel.h> 12f2699491SMichael Ellerman #include <linux/sched.h> 13f2699491SMichael Ellerman #include <linux/perf_event.h> 14f2699491SMichael Ellerman #include <linux/percpu.h> 15f2699491SMichael Ellerman #include <linux/hardirq.h> 1669123184SMichael Neuling #include <linux/uaccess.h> 17f2699491SMichael Ellerman #include <asm/reg.h> 18f2699491SMichael Ellerman #include <asm/pmc.h> 19f2699491SMichael Ellerman #include <asm/machdep.h> 20f2699491SMichael Ellerman #include <asm/firmware.h> 21f2699491SMichael Ellerman #include <asm/ptrace.h> 2269123184SMichael Neuling #include <asm/code-patching.h> 23f2699491SMichael Ellerman 243925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 253925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 263925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 27b0d436c7SAnton Blanchard #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 283925f46bSAnshuman Khandual 29f2699491SMichael Ellerman struct cpu_hw_events { 30f2699491SMichael Ellerman int n_events; 31f2699491SMichael Ellerman int n_percpu; 32f2699491SMichael Ellerman int disabled; 33f2699491SMichael Ellerman int n_added; 34f2699491SMichael Ellerman int n_limited; 35f2699491SMichael Ellerman u8 pmcs_enabled; 36f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 37f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 38f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 399de5cb0fSMichael Ellerman /* 409de5cb0fSMichael Ellerman * The order of the MMCR array is: 419de5cb0fSMichael Ellerman * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 429de5cb0fSMichael Ellerman * - 32-bit, MMCR0, MMCR1, MMCR2 439de5cb0fSMichael Ellerman */ 449de5cb0fSMichael Ellerman unsigned long mmcr[4]; 45f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 46f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 47f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 48f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 49f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 50f2699491SMichael Ellerman 51f2699491SMichael Ellerman unsigned int group_flag; 52f2699491SMichael Ellerman int n_txn_start; 533925f46bSAnshuman Khandual 543925f46bSAnshuman Khandual /* BHRB bits */ 553925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 563925f46bSAnshuman Khandual int bhrb_users; 573925f46bSAnshuman Khandual void *bhrb_context; 583925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 593925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 60f2699491SMichael Ellerman }; 613925f46bSAnshuman Khandual 62e51df2c1SAnton Blanchard static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 63f2699491SMichael Ellerman 64e51df2c1SAnton Blanchard static struct power_pmu *ppmu; 65f2699491SMichael Ellerman 66f2699491SMichael Ellerman /* 67f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 68f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 69f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 70f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 71f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 72f2699491SMichael Ellerman */ 73f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 74f2699491SMichael Ellerman 75f2699491SMichael Ellerman /* 76f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 77f2699491SMichael Ellerman * and a few other names are different. 78f2699491SMichael Ellerman */ 79f2699491SMichael Ellerman #ifdef CONFIG_PPC32 80f2699491SMichael Ellerman 81f2699491SMichael Ellerman #define MMCR0_FCHV 0 82f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 837a7a41f9SMichael Ellerman #define MMCR0_FC56 0 84378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 85330a1eb7SMichael Ellerman #define MMCR0_EBE 0 8676cb8a78SMichael Ellerman #define MMCR0_BHRBA 0 87330a1eb7SMichael Ellerman #define MMCR0_PMCC 0 88330a1eb7SMichael Ellerman #define MMCR0_PMCC_U6 0 89f2699491SMichael Ellerman 90f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 91f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 92f2699491SMichael Ellerman 93f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 94f2699491SMichael Ellerman { 95f2699491SMichael Ellerman return 0; 96f2699491SMichael Ellerman } 97f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 98f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 99f2699491SMichael Ellerman { 100f2699491SMichael Ellerman return 0; 101f2699491SMichael Ellerman } 10275382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 10375382aa7SAnton Blanchard { 10475382aa7SAnton Blanchard regs->result = 0; 10575382aa7SAnton Blanchard } 106f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 107f2699491SMichael Ellerman { 108f2699491SMichael Ellerman return 0; 109f2699491SMichael Ellerman } 110f2699491SMichael Ellerman 111e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 112e6878835Ssukadev@linux.vnet.ibm.com { 113e6878835Ssukadev@linux.vnet.ibm.com return 1; 114e6878835Ssukadev@linux.vnet.ibm.com } 115e6878835Ssukadev@linux.vnet.ibm.com 116330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) { return false; } 117330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) { return 0; } 118330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) { } 119330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) { } 1209de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 121330a1eb7SMichael Ellerman { 1229de5cb0fSMichael Ellerman return cpuhw->mmcr[0]; 123330a1eb7SMichael Ellerman } 124330a1eb7SMichael Ellerman 125d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 126d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 127e51df2c1SAnton Blanchard static void power_pmu_flush_branch_stack(void) {} 128d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 129c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) { } 130f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 131f2699491SMichael Ellerman 13233904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 13333904054SMichael Ellerman { 134cbda6aa1SMichael Ellerman return !!regs->result; 13533904054SMichael Ellerman } 13633904054SMichael Ellerman 137f2699491SMichael Ellerman /* 138f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 139f2699491SMichael Ellerman */ 140f2699491SMichael Ellerman #ifdef CONFIG_PPC64 141f2699491SMichael Ellerman 142f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 143f2699491SMichael Ellerman { 144f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 145f2699491SMichael Ellerman 1467a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 147f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 148f2699491SMichael Ellerman if (slot > 1) 149f2699491SMichael Ellerman return 4 * (slot - 1); 150f2699491SMichael Ellerman } 1517a786832SMichael Ellerman 152f2699491SMichael Ellerman return 0; 153f2699491SMichael Ellerman } 154f2699491SMichael Ellerman 155f2699491SMichael Ellerman /* 156f2699491SMichael Ellerman * The user wants a data address recorded. 157f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 158f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 159f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 16058a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 16158a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 162f2699491SMichael Ellerman */ 163f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 164f2699491SMichael Ellerman { 165f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 16658a032c3SMichael Ellerman bool sdar_valid; 16758a032c3SMichael Ellerman 16858a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 16958a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 17058a032c3SMichael Ellerman else { 171e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 172e6878835Ssukadev@linux.vnet.ibm.com 173e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 174e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 175e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 176e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 177e6878835Ssukadev@linux.vnet.ibm.com else 178e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 179f2699491SMichael Ellerman 18058a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 18158a032c3SMichael Ellerman } 18258a032c3SMichael Ellerman 18358a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 184f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 185f2699491SMichael Ellerman } 186f2699491SMichael Ellerman 1875682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 18868b30bb9SAnton Blanchard { 18968b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 19068b30bb9SAnton Blanchard 1918f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 1928f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 1938f61aa32SMichael Ellerman 19468b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 19568b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 19668b30bb9SAnton Blanchard 1975682c460SMichael Ellerman return !!(regs->dsisr & sihv); 19868b30bb9SAnton Blanchard } 19968b30bb9SAnton Blanchard 2005682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 20168b30bb9SAnton Blanchard { 20268b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 20368b30bb9SAnton Blanchard 2048f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2058f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 2068f61aa32SMichael Ellerman 20768b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 20868b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 20968b30bb9SAnton Blanchard 2105682c460SMichael Ellerman return !!(regs->dsisr & sipr); 21168b30bb9SAnton Blanchard } 21268b30bb9SAnton Blanchard 2131ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 2141ce447b9SBenjamin Herrenschmidt { 2151ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 2161ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2171ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 2181ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2191ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2201ce447b9SBenjamin Herrenschmidt } 2211ce447b9SBenjamin Herrenschmidt 222f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 223f2699491SMichael Ellerman { 22433904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 225f2699491SMichael Ellerman 22675382aa7SAnton Blanchard if (!use_siar) 2271ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2281ce447b9SBenjamin Herrenschmidt 2291ce447b9SBenjamin Herrenschmidt /* 2301ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2311ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2321ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2331ce447b9SBenjamin Herrenschmidt * results 2341ce447b9SBenjamin Herrenschmidt */ 235cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 2361ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 2371ce447b9SBenjamin Herrenschmidt if (siar >= PAGE_OFFSET) 2381ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2391ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2401ce447b9SBenjamin Herrenschmidt } 241f2699491SMichael Ellerman 242f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 2435682c460SMichael Ellerman if (regs_sipr(regs)) 244f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 2455682c460SMichael Ellerman 2465682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 247f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 2485682c460SMichael Ellerman 249f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 250f2699491SMichael Ellerman } 251f2699491SMichael Ellerman 252f2699491SMichael Ellerman /* 253f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 254f2699491SMichael Ellerman * on each interrupt. 2558f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 25675382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 25775382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 258f2699491SMichael Ellerman */ 259f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 260f2699491SMichael Ellerman { 26175382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 26275382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 26375382aa7SAnton Blanchard int use_siar; 26475382aa7SAnton Blanchard 2655682c460SMichael Ellerman regs->dsisr = mmcra; 266860aad71SMichael Ellerman 267cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2688f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 2698f61aa32SMichael Ellerman 2708f61aa32SMichael Ellerman /* 2715c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 2725c093efaSAnton Blanchard * not valid. Use pt_regs. 2735c093efaSAnton Blanchard * 2745c093efaSAnton Blanchard * If it is a marked event use the SIAR. 2755c093efaSAnton Blanchard * 2765c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 2775c093efaSAnton Blanchard * pt_regs. 2785c093efaSAnton Blanchard * 2795c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 2805c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 2815c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 2825c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 2835c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 2845c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 2855c093efaSAnton Blanchard * interrupts off hence the userspace check. 2865c093efaSAnton Blanchard */ 28775382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 28875382aa7SAnton Blanchard use_siar = 0; 2895c093efaSAnton Blanchard else if (marked) 2905c093efaSAnton Blanchard use_siar = 1; 2915c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 2925c093efaSAnton Blanchard use_siar = 0; 293cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 29475382aa7SAnton Blanchard use_siar = 0; 29575382aa7SAnton Blanchard else 29675382aa7SAnton Blanchard use_siar = 1; 29775382aa7SAnton Blanchard 298cbda6aa1SMichael Ellerman regs->result = use_siar; 299f2699491SMichael Ellerman } 300f2699491SMichael Ellerman 301f2699491SMichael Ellerman /* 302f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 303f2699491SMichael Ellerman * it as an NMI. 304f2699491SMichael Ellerman */ 305f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 306f2699491SMichael Ellerman { 307f2699491SMichael Ellerman return !regs->softe; 308f2699491SMichael Ellerman } 309f2699491SMichael Ellerman 310e6878835Ssukadev@linux.vnet.ibm.com /* 311e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 312e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 313e6878835Ssukadev@linux.vnet.ibm.com * 314e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 315e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 316e6878835Ssukadev@linux.vnet.ibm.com */ 317e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 318e6878835Ssukadev@linux.vnet.ibm.com { 319e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 320e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 321e6878835Ssukadev@linux.vnet.ibm.com 32258a032c3SMichael Ellerman if (marked) { 32358a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 32458a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 32558a032c3SMichael Ellerman 32658a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 327e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 32858a032c3SMichael Ellerman } 329e6878835Ssukadev@linux.vnet.ibm.com 330e6878835Ssukadev@linux.vnet.ibm.com return 1; 331e6878835Ssukadev@linux.vnet.ibm.com } 332e6878835Ssukadev@linux.vnet.ibm.com 333d52f2dc4SMichael Neuling 334d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 335d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 336d52f2dc4SMichael Neuling { 337d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 338d52f2dc4SMichael Neuling } 339d52f2dc4SMichael Neuling 340d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 341d52f2dc4SMichael Neuling { 34269111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 343d52f2dc4SMichael Neuling 344d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 345d52f2dc4SMichael Neuling return; 346d52f2dc4SMichael Neuling 347d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 348d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 349d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 350d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 351d52f2dc4SMichael Neuling } 352d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 353d52f2dc4SMichael Neuling } 354d52f2dc4SMichael Neuling 355d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 356d52f2dc4SMichael Neuling { 35769111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 358d52f2dc4SMichael Neuling 359d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 360d52f2dc4SMichael Neuling return; 361d52f2dc4SMichael Neuling 362d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 363d52f2dc4SMichael Neuling WARN_ON_ONCE(cpuhw->bhrb_users < 0); 364d52f2dc4SMichael Neuling 365d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 366d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 367d52f2dc4SMichael Neuling * events are active on the PMU. 368d52f2dc4SMichael Neuling */ 369d52f2dc4SMichael Neuling 370d52f2dc4SMichael Neuling /* avoid stale pointer */ 371d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 372d52f2dc4SMichael Neuling } 373d52f2dc4SMichael Neuling } 374d52f2dc4SMichael Neuling 375d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 376d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 377d52f2dc4SMichael Neuling */ 378e51df2c1SAnton Blanchard static void power_pmu_flush_branch_stack(void) 379d52f2dc4SMichael Neuling { 380d52f2dc4SMichael Neuling if (ppmu->bhrb_nr) 381d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 382d52f2dc4SMichael Neuling } 38369123184SMichael Neuling /* Calculate the to address for a branch */ 38469123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 38569123184SMichael Neuling { 38669123184SMichael Neuling unsigned int instr; 38769123184SMichael Neuling int ret; 38869123184SMichael Neuling __u64 target; 38969123184SMichael Neuling 39069123184SMichael Neuling if (is_kernel_addr(addr)) 39169123184SMichael Neuling return branch_target((unsigned int *)addr); 39269123184SMichael Neuling 39369123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 39469123184SMichael Neuling pagefault_disable(); 39569123184SMichael Neuling ret = __get_user_inatomic(instr, (unsigned int __user *)addr); 39669123184SMichael Neuling if (ret) { 39769123184SMichael Neuling pagefault_enable(); 39869123184SMichael Neuling return 0; 39969123184SMichael Neuling } 40069123184SMichael Neuling pagefault_enable(); 40169123184SMichael Neuling 40269123184SMichael Neuling target = branch_target(&instr); 40369123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 40469123184SMichael Neuling return target; 40569123184SMichael Neuling 40669123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 40769123184SMichael Neuling return target - (unsigned long)&instr + addr; 40869123184SMichael Neuling } 409d52f2dc4SMichael Neuling 410d52f2dc4SMichael Neuling /* Processing BHRB entries */ 411e51df2c1SAnton Blanchard static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 412d52f2dc4SMichael Neuling { 413d52f2dc4SMichael Neuling u64 val; 414d52f2dc4SMichael Neuling u64 addr; 415506e70d1SMichael Neuling int r_index, u_index, pred; 416d52f2dc4SMichael Neuling 417d52f2dc4SMichael Neuling r_index = 0; 418d52f2dc4SMichael Neuling u_index = 0; 419d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 420d52f2dc4SMichael Neuling /* Assembly read function */ 421506e70d1SMichael Neuling val = read_bhrb(r_index++); 422506e70d1SMichael Neuling if (!val) 423d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 424d52f2dc4SMichael Neuling break; 425506e70d1SMichael Neuling else { 426d52f2dc4SMichael Neuling addr = val & BHRB_EA; 427d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 428d52f2dc4SMichael Neuling 429506e70d1SMichael Neuling if (!addr) 430506e70d1SMichael Neuling /* invalid entry */ 431d52f2dc4SMichael Neuling continue; 432d52f2dc4SMichael Neuling 433506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 434506e70d1SMichael Neuling * the most recent branch). 435506e70d1SMichael Neuling * There are two types of valid entries: 436506e70d1SMichael Neuling * 1) a target entry which is the to address of a 437506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 438506e70d1SMichael Neuling * entry read from the bhrb will be branch 439506e70d1SMichael Neuling * corresponding to this target (ie. the actual 440506e70d1SMichael Neuling * blr/bctr/btar instruction). 441506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 442506e70d1SMichael Neuling * target entry proceeds this, then this is the 443506e70d1SMichael Neuling * matching branch for that target. If this is not 444506e70d1SMichael Neuling * following a target entry, then this is a branch 445506e70d1SMichael Neuling * where the target is given as an immediate field 446506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 447506e70d1SMichael Neuling * In this case we need to read the instruction from 448506e70d1SMichael Neuling * memory to determine the target/to address. 449506e70d1SMichael Neuling */ 450d52f2dc4SMichael Neuling 451d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 452506e70d1SMichael Neuling /* Target branches use two entries 453506e70d1SMichael Neuling * (ie. computed gotos/XL form) 454506e70d1SMichael Neuling */ 455506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 456d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 457d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 458d52f2dc4SMichael Neuling 459506e70d1SMichael Neuling /* Get from address in next entry */ 460506e70d1SMichael Neuling val = read_bhrb(r_index++); 461506e70d1SMichael Neuling addr = val & BHRB_EA; 462506e70d1SMichael Neuling if (val & BHRB_TARGET) { 463506e70d1SMichael Neuling /* Shouldn't have two targets in a 464506e70d1SMichael Neuling row.. Reset index and try again */ 465506e70d1SMichael Neuling r_index--; 466506e70d1SMichael Neuling addr = 0; 467d52f2dc4SMichael Neuling } 468506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 469506e70d1SMichael Neuling } else { 470506e70d1SMichael Neuling /* Branches to immediate field 471506e70d1SMichael Neuling (ie I or B form) */ 472506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 47369123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 47469123184SMichael Neuling power_pmu_bhrb_to(addr); 475506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 476506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 477506e70d1SMichael Neuling } 478506e70d1SMichael Neuling u_index++; 479506e70d1SMichael Neuling 480d52f2dc4SMichael Neuling } 481d52f2dc4SMichael Neuling } 482d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 483d52f2dc4SMichael Neuling return; 484d52f2dc4SMichael Neuling } 485d52f2dc4SMichael Neuling 486330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) 487330a1eb7SMichael Ellerman { 488330a1eb7SMichael Ellerman /* 489330a1eb7SMichael Ellerman * This could be a per-PMU callback, but we'd rather avoid the cost. We 490330a1eb7SMichael Ellerman * check that the PMU supports EBB, meaning those that don't can still 491330a1eb7SMichael Ellerman * use bit 63 of the event code for something else if they wish. 492330a1eb7SMichael Ellerman */ 4934d9690ddSJoel Stanley return (ppmu->flags & PPMU_ARCH_207S) && 4948d7c55d0SMichael Ellerman ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 495330a1eb7SMichael Ellerman } 496330a1eb7SMichael Ellerman 497330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) 498330a1eb7SMichael Ellerman { 499330a1eb7SMichael Ellerman struct perf_event *leader = event->group_leader; 500330a1eb7SMichael Ellerman 501330a1eb7SMichael Ellerman /* Event and group leader must agree on EBB */ 502330a1eb7SMichael Ellerman if (is_ebb_event(leader) != is_ebb_event(event)) 503330a1eb7SMichael Ellerman return -EINVAL; 504330a1eb7SMichael Ellerman 505330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 506330a1eb7SMichael Ellerman if (!(event->attach_state & PERF_ATTACH_TASK)) 507330a1eb7SMichael Ellerman return -EINVAL; 508330a1eb7SMichael Ellerman 509330a1eb7SMichael Ellerman if (!leader->attr.pinned || !leader->attr.exclusive) 510330a1eb7SMichael Ellerman return -EINVAL; 511330a1eb7SMichael Ellerman 51258b5fb00SMichael Ellerman if (event->attr.freq || 51358b5fb00SMichael Ellerman event->attr.inherit || 51458b5fb00SMichael Ellerman event->attr.sample_type || 51558b5fb00SMichael Ellerman event->attr.sample_period || 51658b5fb00SMichael Ellerman event->attr.enable_on_exec) 517330a1eb7SMichael Ellerman return -EINVAL; 518330a1eb7SMichael Ellerman } 519330a1eb7SMichael Ellerman 520330a1eb7SMichael Ellerman return 0; 521330a1eb7SMichael Ellerman } 522330a1eb7SMichael Ellerman 523330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) 524330a1eb7SMichael Ellerman { 525330a1eb7SMichael Ellerman if (!is_ebb_event(event) || current->thread.used_ebb) 526330a1eb7SMichael Ellerman return; 527330a1eb7SMichael Ellerman 528330a1eb7SMichael Ellerman /* 529330a1eb7SMichael Ellerman * IFF this is the first time we've added an EBB event, set 530330a1eb7SMichael Ellerman * PMXE in the user MMCR0 so we can detect when it's cleared by 531330a1eb7SMichael Ellerman * userspace. We need this so that we can context switch while 532330a1eb7SMichael Ellerman * userspace is in the EBB handler (where PMXE is 0). 533330a1eb7SMichael Ellerman */ 534330a1eb7SMichael Ellerman current->thread.used_ebb = 1; 535330a1eb7SMichael Ellerman current->thread.mmcr0 |= MMCR0_PMXE; 536330a1eb7SMichael Ellerman } 537330a1eb7SMichael Ellerman 538330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) 539330a1eb7SMichael Ellerman { 540330a1eb7SMichael Ellerman if (!(mmcr0 & MMCR0_EBE)) 541330a1eb7SMichael Ellerman return; 542330a1eb7SMichael Ellerman 543330a1eb7SMichael Ellerman current->thread.siar = mfspr(SPRN_SIAR); 544330a1eb7SMichael Ellerman current->thread.sier = mfspr(SPRN_SIER); 545330a1eb7SMichael Ellerman current->thread.sdar = mfspr(SPRN_SDAR); 546330a1eb7SMichael Ellerman current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 547330a1eb7SMichael Ellerman current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 548330a1eb7SMichael Ellerman } 549330a1eb7SMichael Ellerman 5509de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 551330a1eb7SMichael Ellerman { 5529de5cb0fSMichael Ellerman unsigned long mmcr0 = cpuhw->mmcr[0]; 5539de5cb0fSMichael Ellerman 554330a1eb7SMichael Ellerman if (!ebb) 555330a1eb7SMichael Ellerman goto out; 556330a1eb7SMichael Ellerman 55776cb8a78SMichael Ellerman /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 55876cb8a78SMichael Ellerman mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 559330a1eb7SMichael Ellerman 560c2e37a26SMichael Ellerman /* 561c2e37a26SMichael Ellerman * Add any bits from the user MMCR0, FC or PMAO. This is compatible 562c2e37a26SMichael Ellerman * with pmao_restore_workaround() because we may add PMAO but we never 563c2e37a26SMichael Ellerman * clear it here. 564c2e37a26SMichael Ellerman */ 565330a1eb7SMichael Ellerman mmcr0 |= current->thread.mmcr0; 566330a1eb7SMichael Ellerman 567c2e37a26SMichael Ellerman /* 568c2e37a26SMichael Ellerman * Be careful not to set PMXE if userspace had it cleared. This is also 569c2e37a26SMichael Ellerman * compatible with pmao_restore_workaround() because it has already 570c2e37a26SMichael Ellerman * cleared PMXE and we leave PMAO alone. 571c2e37a26SMichael Ellerman */ 572330a1eb7SMichael Ellerman if (!(current->thread.mmcr0 & MMCR0_PMXE)) 573330a1eb7SMichael Ellerman mmcr0 &= ~MMCR0_PMXE; 574330a1eb7SMichael Ellerman 575330a1eb7SMichael Ellerman mtspr(SPRN_SIAR, current->thread.siar); 576330a1eb7SMichael Ellerman mtspr(SPRN_SIER, current->thread.sier); 577330a1eb7SMichael Ellerman mtspr(SPRN_SDAR, current->thread.sdar); 5789de5cb0fSMichael Ellerman 5799de5cb0fSMichael Ellerman /* 5809de5cb0fSMichael Ellerman * Merge the kernel & user values of MMCR2. The semantics we implement 5819de5cb0fSMichael Ellerman * are that the user MMCR2 can set bits, ie. cause counters to freeze, 5829de5cb0fSMichael Ellerman * but not clear bits. If a task wants to be able to clear bits, ie. 5839de5cb0fSMichael Ellerman * unfreeze counters, it should not set exclude_xxx in its events and 5849de5cb0fSMichael Ellerman * instead manage the MMCR2 entirely by itself. 5859de5cb0fSMichael Ellerman */ 5869de5cb0fSMichael Ellerman mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); 587330a1eb7SMichael Ellerman out: 588330a1eb7SMichael Ellerman return mmcr0; 589330a1eb7SMichael Ellerman } 590c2e37a26SMichael Ellerman 591c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) 592c2e37a26SMichael Ellerman { 593c2e37a26SMichael Ellerman unsigned pmcs[6]; 594c2e37a26SMichael Ellerman 595c2e37a26SMichael Ellerman if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 596c2e37a26SMichael Ellerman return; 597c2e37a26SMichael Ellerman 598c2e37a26SMichael Ellerman /* 599c2e37a26SMichael Ellerman * On POWER8E there is a hardware defect which affects the PMU context 600c2e37a26SMichael Ellerman * switch logic, ie. power_pmu_disable/enable(). 601c2e37a26SMichael Ellerman * 602c2e37a26SMichael Ellerman * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 603c2e37a26SMichael Ellerman * by the hardware. Sometime later the actual PMU exception is 604c2e37a26SMichael Ellerman * delivered. 605c2e37a26SMichael Ellerman * 606c2e37a26SMichael Ellerman * If we context switch, or simply disable/enable, the PMU prior to the 607c2e37a26SMichael Ellerman * exception arriving, the exception will be lost when we clear PMAO. 608c2e37a26SMichael Ellerman * 609c2e37a26SMichael Ellerman * When we reenable the PMU, we will write the saved MMCR0 with PMAO 610c2e37a26SMichael Ellerman * set, and this _should_ generate an exception. However because of the 611c2e37a26SMichael Ellerman * defect no exception is generated when we write PMAO, and we get 612c2e37a26SMichael Ellerman * stuck with no counters counting but no exception delivered. 613c2e37a26SMichael Ellerman * 614c2e37a26SMichael Ellerman * The workaround is to detect this case and tweak the hardware to 615c2e37a26SMichael Ellerman * create another pending PMU exception. 616c2e37a26SMichael Ellerman * 617c2e37a26SMichael Ellerman * We do that by setting up PMC6 (cycles) for an imminent overflow and 618c2e37a26SMichael Ellerman * enabling the PMU. That causes a new exception to be generated in the 619c2e37a26SMichael Ellerman * chip, but we don't take it yet because we have interrupts hard 620c2e37a26SMichael Ellerman * disabled. We then write back the PMU state as we want it to be seen 621c2e37a26SMichael Ellerman * by the exception handler. When we reenable interrupts the exception 622c2e37a26SMichael Ellerman * handler will be called and see the correct state. 623c2e37a26SMichael Ellerman * 624c2e37a26SMichael Ellerman * The logic is the same for EBB, except that the exception is gated by 625c2e37a26SMichael Ellerman * us having interrupts hard disabled as well as the fact that we are 626c2e37a26SMichael Ellerman * not in userspace. The exception is finally delivered when we return 627c2e37a26SMichael Ellerman * to userspace. 628c2e37a26SMichael Ellerman */ 629c2e37a26SMichael Ellerman 630c2e37a26SMichael Ellerman /* Only if PMAO is set and PMAO_SYNC is clear */ 631c2e37a26SMichael Ellerman if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 632c2e37a26SMichael Ellerman return; 633c2e37a26SMichael Ellerman 634c2e37a26SMichael Ellerman /* If we're doing EBB, only if BESCR[GE] is set */ 635c2e37a26SMichael Ellerman if (ebb && !(current->thread.bescr & BESCR_GE)) 636c2e37a26SMichael Ellerman return; 637c2e37a26SMichael Ellerman 638c2e37a26SMichael Ellerman /* 639c2e37a26SMichael Ellerman * We are already soft-disabled in power_pmu_enable(). We need to hard 640c2e37a26SMichael Ellerman * enable to actually prevent the PMU exception from firing. 641c2e37a26SMichael Ellerman */ 642c2e37a26SMichael Ellerman hard_irq_disable(); 643c2e37a26SMichael Ellerman 644c2e37a26SMichael Ellerman /* 645c2e37a26SMichael Ellerman * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 646c2e37a26SMichael Ellerman * Using read/write_pmc() in a for loop adds 12 function calls and 647c2e37a26SMichael Ellerman * almost doubles our code size. 648c2e37a26SMichael Ellerman */ 649c2e37a26SMichael Ellerman pmcs[0] = mfspr(SPRN_PMC1); 650c2e37a26SMichael Ellerman pmcs[1] = mfspr(SPRN_PMC2); 651c2e37a26SMichael Ellerman pmcs[2] = mfspr(SPRN_PMC3); 652c2e37a26SMichael Ellerman pmcs[3] = mfspr(SPRN_PMC4); 653c2e37a26SMichael Ellerman pmcs[4] = mfspr(SPRN_PMC5); 654c2e37a26SMichael Ellerman pmcs[5] = mfspr(SPRN_PMC6); 655c2e37a26SMichael Ellerman 656c2e37a26SMichael Ellerman /* Ensure all freeze bits are unset */ 657c2e37a26SMichael Ellerman mtspr(SPRN_MMCR2, 0); 658c2e37a26SMichael Ellerman 659c2e37a26SMichael Ellerman /* Set up PMC6 to overflow in one cycle */ 660c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, 0x7FFFFFFE); 661c2e37a26SMichael Ellerman 662c2e37a26SMichael Ellerman /* Enable exceptions and unfreeze PMC6 */ 663c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 664c2e37a26SMichael Ellerman 665c2e37a26SMichael Ellerman /* Now we need to refreeze and restore the PMCs */ 666c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 667c2e37a26SMichael Ellerman 668c2e37a26SMichael Ellerman mtspr(SPRN_PMC1, pmcs[0]); 669c2e37a26SMichael Ellerman mtspr(SPRN_PMC2, pmcs[1]); 670c2e37a26SMichael Ellerman mtspr(SPRN_PMC3, pmcs[2]); 671c2e37a26SMichael Ellerman mtspr(SPRN_PMC4, pmcs[3]); 672c2e37a26SMichael Ellerman mtspr(SPRN_PMC5, pmcs[4]); 673c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, pmcs[5]); 674c2e37a26SMichael Ellerman } 675f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 676f2699491SMichael Ellerman 677f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 678f2699491SMichael Ellerman 679f2699491SMichael Ellerman /* 680f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 681f2699491SMichael Ellerman */ 682f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 683f2699491SMichael Ellerman { 684f2699491SMichael Ellerman unsigned long val; 685f2699491SMichael Ellerman 686f2699491SMichael Ellerman switch (idx) { 687f2699491SMichael Ellerman case 1: 688f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 689f2699491SMichael Ellerman break; 690f2699491SMichael Ellerman case 2: 691f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 692f2699491SMichael Ellerman break; 693f2699491SMichael Ellerman case 3: 694f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 695f2699491SMichael Ellerman break; 696f2699491SMichael Ellerman case 4: 697f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 698f2699491SMichael Ellerman break; 699f2699491SMichael Ellerman case 5: 700f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 701f2699491SMichael Ellerman break; 702f2699491SMichael Ellerman case 6: 703f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 704f2699491SMichael Ellerman break; 705f2699491SMichael Ellerman #ifdef CONFIG_PPC64 706f2699491SMichael Ellerman case 7: 707f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 708f2699491SMichael Ellerman break; 709f2699491SMichael Ellerman case 8: 710f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 711f2699491SMichael Ellerman break; 712f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 713f2699491SMichael Ellerman default: 714f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 715f2699491SMichael Ellerman val = 0; 716f2699491SMichael Ellerman } 717f2699491SMichael Ellerman return val; 718f2699491SMichael Ellerman } 719f2699491SMichael Ellerman 720f2699491SMichael Ellerman /* 721f2699491SMichael Ellerman * Write one PMC. 722f2699491SMichael Ellerman */ 723f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 724f2699491SMichael Ellerman { 725f2699491SMichael Ellerman switch (idx) { 726f2699491SMichael Ellerman case 1: 727f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 728f2699491SMichael Ellerman break; 729f2699491SMichael Ellerman case 2: 730f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 731f2699491SMichael Ellerman break; 732f2699491SMichael Ellerman case 3: 733f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 734f2699491SMichael Ellerman break; 735f2699491SMichael Ellerman case 4: 736f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 737f2699491SMichael Ellerman break; 738f2699491SMichael Ellerman case 5: 739f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 740f2699491SMichael Ellerman break; 741f2699491SMichael Ellerman case 6: 742f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 743f2699491SMichael Ellerman break; 744f2699491SMichael Ellerman #ifdef CONFIG_PPC64 745f2699491SMichael Ellerman case 7: 746f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 747f2699491SMichael Ellerman break; 748f2699491SMichael Ellerman case 8: 749f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 750f2699491SMichael Ellerman break; 751f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 752f2699491SMichael Ellerman default: 753f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 754f2699491SMichael Ellerman } 755f2699491SMichael Ellerman } 756f2699491SMichael Ellerman 7575f6d0380SAnshuman Khandual /* Called from sysrq_handle_showregs() */ 7585f6d0380SAnshuman Khandual void perf_event_print_debug(void) 7595f6d0380SAnshuman Khandual { 7605f6d0380SAnshuman Khandual unsigned long sdar, sier, flags; 7615f6d0380SAnshuman Khandual u32 pmcs[MAX_HWEVENTS]; 7625f6d0380SAnshuman Khandual int i; 7635f6d0380SAnshuman Khandual 7645f6d0380SAnshuman Khandual if (!ppmu->n_counter) 7655f6d0380SAnshuman Khandual return; 7665f6d0380SAnshuman Khandual 7675f6d0380SAnshuman Khandual local_irq_save(flags); 7685f6d0380SAnshuman Khandual 7695f6d0380SAnshuman Khandual pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 7705f6d0380SAnshuman Khandual smp_processor_id(), ppmu->name, ppmu->n_counter); 7715f6d0380SAnshuman Khandual 7725f6d0380SAnshuman Khandual for (i = 0; i < ppmu->n_counter; i++) 7735f6d0380SAnshuman Khandual pmcs[i] = read_pmc(i + 1); 7745f6d0380SAnshuman Khandual 7755f6d0380SAnshuman Khandual for (; i < MAX_HWEVENTS; i++) 7765f6d0380SAnshuman Khandual pmcs[i] = 0xdeadbeef; 7775f6d0380SAnshuman Khandual 7785f6d0380SAnshuman Khandual pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 7795f6d0380SAnshuman Khandual pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 7805f6d0380SAnshuman Khandual 7815f6d0380SAnshuman Khandual if (ppmu->n_counter > 4) 7825f6d0380SAnshuman Khandual pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 7835f6d0380SAnshuman Khandual pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 7845f6d0380SAnshuman Khandual 7855f6d0380SAnshuman Khandual pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 7865f6d0380SAnshuman Khandual mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 7875f6d0380SAnshuman Khandual 7885f6d0380SAnshuman Khandual sdar = sier = 0; 7895f6d0380SAnshuman Khandual #ifdef CONFIG_PPC64 7905f6d0380SAnshuman Khandual sdar = mfspr(SPRN_SDAR); 7915f6d0380SAnshuman Khandual 7925f6d0380SAnshuman Khandual if (ppmu->flags & PPMU_HAS_SIER) 7935f6d0380SAnshuman Khandual sier = mfspr(SPRN_SIER); 7945f6d0380SAnshuman Khandual 7954d9690ddSJoel Stanley if (ppmu->flags & PPMU_ARCH_207S) { 7965f6d0380SAnshuman Khandual pr_info("MMCR2: %016lx EBBHR: %016lx\n", 7975f6d0380SAnshuman Khandual mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 7985f6d0380SAnshuman Khandual pr_info("EBBRR: %016lx BESCR: %016lx\n", 7995f6d0380SAnshuman Khandual mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 8005f6d0380SAnshuman Khandual } 8015f6d0380SAnshuman Khandual #endif 8025f6d0380SAnshuman Khandual pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 8035f6d0380SAnshuman Khandual mfspr(SPRN_SIAR), sdar, sier); 8045f6d0380SAnshuman Khandual 8055f6d0380SAnshuman Khandual local_irq_restore(flags); 8065f6d0380SAnshuman Khandual } 8075f6d0380SAnshuman Khandual 808f2699491SMichael Ellerman /* 809f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 810f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 811f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 812f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 813f2699491SMichael Ellerman */ 814f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 815f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 816f2699491SMichael Ellerman int n_ev) 817f2699491SMichael Ellerman { 818f2699491SMichael Ellerman unsigned long mask, value, nv; 819f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 820f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 821f2699491SMichael Ellerman int i, j; 822f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 823f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 824f2699491SMichael Ellerman 825f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 826f2699491SMichael Ellerman return -1; 827f2699491SMichael Ellerman 828f2699491SMichael Ellerman /* First see if the events will go on as-is */ 829f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 830f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 831f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 832f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 833f2699491SMichael Ellerman cpuhw->alternatives[i]); 834f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 835f2699491SMichael Ellerman } 836f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 837f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 838f2699491SMichael Ellerman return -1; 839f2699491SMichael Ellerman } 840f2699491SMichael Ellerman value = mask = 0; 841f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 842f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 843f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 844f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) != 0 || 845f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][0]) & 846f2699491SMichael Ellerman cpuhw->amasks[i][0]) != 0) 847f2699491SMichael Ellerman break; 848f2699491SMichael Ellerman value = nv; 849f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 850f2699491SMichael Ellerman } 851f2699491SMichael Ellerman if (i == n_ev) 852f2699491SMichael Ellerman return 0; /* all OK */ 853f2699491SMichael Ellerman 854f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 855f2699491SMichael Ellerman if (!ppmu->get_alternatives) 856f2699491SMichael Ellerman return -1; 857f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 858f2699491SMichael Ellerman choice[i] = 0; 859f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 860f2699491SMichael Ellerman cpuhw->alternatives[i]); 861f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 862f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 863f2699491SMichael Ellerman &cpuhw->amasks[i][j], 864f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 865f2699491SMichael Ellerman } 866f2699491SMichael Ellerman 867f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 868f2699491SMichael Ellerman i = 0; 869f2699491SMichael Ellerman j = -1; 870f2699491SMichael Ellerman value = mask = nv = 0; 871f2699491SMichael Ellerman while (i < n_ev) { 872f2699491SMichael Ellerman if (j >= 0) { 873f2699491SMichael Ellerman /* we're backtracking, restore context */ 874f2699491SMichael Ellerman value = svalues[i]; 875f2699491SMichael Ellerman mask = smasks[i]; 876f2699491SMichael Ellerman j = choice[i]; 877f2699491SMichael Ellerman } 878f2699491SMichael Ellerman /* 879f2699491SMichael Ellerman * See if any alternative k for event_id i, 880f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 881f2699491SMichael Ellerman */ 882f2699491SMichael Ellerman while (++j < n_alt[i]) { 883f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 884f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 885f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 886f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 887f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 888f2699491SMichael Ellerman break; 889f2699491SMichael Ellerman } 890f2699491SMichael Ellerman if (j >= n_alt[i]) { 891f2699491SMichael Ellerman /* 892f2699491SMichael Ellerman * No feasible alternative, backtrack 893f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 894f2699491SMichael Ellerman * alternatives from where we got up to. 895f2699491SMichael Ellerman */ 896f2699491SMichael Ellerman if (--i < 0) 897f2699491SMichael Ellerman return -1; 898f2699491SMichael Ellerman } else { 899f2699491SMichael Ellerman /* 900f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 901f2699491SMichael Ellerman * remember where we got up to with this event_id, 902f2699491SMichael Ellerman * go on to the next event_id, and start with 903f2699491SMichael Ellerman * the first alternative for it. 904f2699491SMichael Ellerman */ 905f2699491SMichael Ellerman choice[i] = j; 906f2699491SMichael Ellerman svalues[i] = value; 907f2699491SMichael Ellerman smasks[i] = mask; 908f2699491SMichael Ellerman value = nv; 909f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 910f2699491SMichael Ellerman ++i; 911f2699491SMichael Ellerman j = -1; 912f2699491SMichael Ellerman } 913f2699491SMichael Ellerman } 914f2699491SMichael Ellerman 915f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 916f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 917f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 918f2699491SMichael Ellerman return 0; 919f2699491SMichael Ellerman } 920f2699491SMichael Ellerman 921f2699491SMichael Ellerman /* 922f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 923f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 924f2699491SMichael Ellerman * added events. 925f2699491SMichael Ellerman */ 926f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 927f2699491SMichael Ellerman int n_prev, int n_new) 928f2699491SMichael Ellerman { 929f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 930f2699491SMichael Ellerman int i, n, first; 931f2699491SMichael Ellerman struct perf_event *event; 932f2699491SMichael Ellerman 9339de5cb0fSMichael Ellerman /* 9349de5cb0fSMichael Ellerman * If the PMU we're on supports per event exclude settings then we 9359de5cb0fSMichael Ellerman * don't need to do any of this logic. NB. This assumes no PMU has both 9369de5cb0fSMichael Ellerman * per event exclude and limited PMCs. 9379de5cb0fSMichael Ellerman */ 9389de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 9399de5cb0fSMichael Ellerman return 0; 9409de5cb0fSMichael Ellerman 941f2699491SMichael Ellerman n = n_prev + n_new; 942f2699491SMichael Ellerman if (n <= 1) 943f2699491SMichael Ellerman return 0; 944f2699491SMichael Ellerman 945f2699491SMichael Ellerman first = 1; 946f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 947f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 948f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 949f2699491SMichael Ellerman continue; 950f2699491SMichael Ellerman } 951f2699491SMichael Ellerman event = ctrs[i]; 952f2699491SMichael Ellerman if (first) { 953f2699491SMichael Ellerman eu = event->attr.exclude_user; 954f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 955f2699491SMichael Ellerman eh = event->attr.exclude_hv; 956f2699491SMichael Ellerman first = 0; 957f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 958f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 959f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 960f2699491SMichael Ellerman return -EAGAIN; 961f2699491SMichael Ellerman } 962f2699491SMichael Ellerman } 963f2699491SMichael Ellerman 964f2699491SMichael Ellerman if (eu || ek || eh) 965f2699491SMichael Ellerman for (i = 0; i < n; ++i) 966f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 967f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 968f2699491SMichael Ellerman 969f2699491SMichael Ellerman return 0; 970f2699491SMichael Ellerman } 971f2699491SMichael Ellerman 972f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 973f2699491SMichael Ellerman { 974f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 975f2699491SMichael Ellerman 976f2699491SMichael Ellerman /* 977f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 978f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 979f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 980f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 981f2699491SMichael Ellerman * number of events to rollback at once. If we dectect a rollback 982f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 983f2699491SMichael Ellerman * counters. 984f2699491SMichael Ellerman */ 985f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 986f2699491SMichael Ellerman delta = 0; 987f2699491SMichael Ellerman 988f2699491SMichael Ellerman return delta; 989f2699491SMichael Ellerman } 990f2699491SMichael Ellerman 991f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 992f2699491SMichael Ellerman { 993f2699491SMichael Ellerman s64 val, delta, prev; 994f2699491SMichael Ellerman 995f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 996f2699491SMichael Ellerman return; 997f2699491SMichael Ellerman 998f2699491SMichael Ellerman if (!event->hw.idx) 999f2699491SMichael Ellerman return; 1000330a1eb7SMichael Ellerman 1001330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 1002330a1eb7SMichael Ellerman val = read_pmc(event->hw.idx); 1003330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, val); 1004330a1eb7SMichael Ellerman return; 1005330a1eb7SMichael Ellerman } 1006330a1eb7SMichael Ellerman 1007f2699491SMichael Ellerman /* 1008f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 1009f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 1010f2699491SMichael Ellerman * Therefore we treat them like NMIs. 1011f2699491SMichael Ellerman */ 1012f2699491SMichael Ellerman do { 1013f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1014f2699491SMichael Ellerman barrier(); 1015f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 1016f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1017f2699491SMichael Ellerman if (!delta) 1018f2699491SMichael Ellerman return; 1019f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1020f2699491SMichael Ellerman 1021f2699491SMichael Ellerman local64_add(delta, &event->count); 1022f5602941SAnton Blanchard 1023f5602941SAnton Blanchard /* 1024f5602941SAnton Blanchard * A number of places program the PMC with (0x80000000 - period_left). 1025f5602941SAnton Blanchard * We never want period_left to be less than 1 because we will program 1026f5602941SAnton Blanchard * the PMC with a value >= 0x800000000 and an edge detected PMC will 1027f5602941SAnton Blanchard * roll around to 0 before taking an exception. We have seen this 1028f5602941SAnton Blanchard * on POWER8. 1029f5602941SAnton Blanchard * 1030f5602941SAnton Blanchard * To fix this, clamp the minimum value of period_left to 1. 1031f5602941SAnton Blanchard */ 1032f5602941SAnton Blanchard do { 1033f5602941SAnton Blanchard prev = local64_read(&event->hw.period_left); 1034f5602941SAnton Blanchard val = prev - delta; 1035f5602941SAnton Blanchard if (val < 1) 1036f5602941SAnton Blanchard val = 1; 1037f5602941SAnton Blanchard } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1038f2699491SMichael Ellerman } 1039f2699491SMichael Ellerman 1040f2699491SMichael Ellerman /* 1041f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 1042f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 1043f2699491SMichael Ellerman * us if `event' is using such a PMC. 1044f2699491SMichael Ellerman */ 1045f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 1046f2699491SMichael Ellerman { 1047f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1048f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 1049f2699491SMichael Ellerman } 1050f2699491SMichael Ellerman 1051f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1052f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1053f2699491SMichael Ellerman { 1054f2699491SMichael Ellerman struct perf_event *event; 1055f2699491SMichael Ellerman u64 val, prev, delta; 1056f2699491SMichael Ellerman int i; 1057f2699491SMichael Ellerman 1058f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1059f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1060f2699491SMichael Ellerman if (!event->hw.idx) 1061f2699491SMichael Ellerman continue; 1062f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1063f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1064f2699491SMichael Ellerman event->hw.idx = 0; 1065f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1066f2699491SMichael Ellerman if (delta) 1067f2699491SMichael Ellerman local64_add(delta, &event->count); 1068f2699491SMichael Ellerman } 1069f2699491SMichael Ellerman } 1070f2699491SMichael Ellerman 1071f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1072f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1073f2699491SMichael Ellerman { 1074f2699491SMichael Ellerman struct perf_event *event; 1075f2699491SMichael Ellerman u64 val, prev; 1076f2699491SMichael Ellerman int i; 1077f2699491SMichael Ellerman 1078f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1079f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1080f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 1081f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1082f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1083f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 1084f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1085f2699491SMichael Ellerman perf_event_update_userpage(event); 1086f2699491SMichael Ellerman } 1087f2699491SMichael Ellerman } 1088f2699491SMichael Ellerman 1089f2699491SMichael Ellerman /* 1090f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 1091f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 1092f2699491SMichael Ellerman * other events. We try to keep the values from the limited 1093f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 1094f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 1095f2699491SMichael Ellerman * the limited events as small and consistent as possible. 1096f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 1097f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 1098f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 1099f2699491SMichael Ellerman */ 1100f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1101f2699491SMichael Ellerman { 1102f2699491SMichael Ellerman unsigned long pmc5, pmc6; 1103f2699491SMichael Ellerman 1104f2699491SMichael Ellerman if (!cpuhw->n_limited) { 1105f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1106f2699491SMichael Ellerman return; 1107f2699491SMichael Ellerman } 1108f2699491SMichael Ellerman 1109f2699491SMichael Ellerman /* 1110f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 1111f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 1112f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 1113f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 1114f2699491SMichael Ellerman * interrupt enable bits turned off. 1115f2699491SMichael Ellerman */ 1116f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1117f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 1118f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1119f2699491SMichael Ellerman "i" (SPRN_MMCR0), 1120f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1121f2699491SMichael Ellerman 1122f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 1123f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 1124f2699491SMichael Ellerman else 1125f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 1126f2699491SMichael Ellerman 1127f2699491SMichael Ellerman /* 1128f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 1129f2699491SMichael Ellerman * enable bits, if necessary. 1130f2699491SMichael Ellerman */ 1131f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1132f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1133f2699491SMichael Ellerman } 1134f2699491SMichael Ellerman 1135f2699491SMichael Ellerman /* 1136f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 1137f2699491SMichael Ellerman * events to be added or removed. 1138f2699491SMichael Ellerman */ 1139f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 1140f2699491SMichael Ellerman { 1141f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1142330a1eb7SMichael Ellerman unsigned long flags, mmcr0, val; 1143f2699491SMichael Ellerman 1144f2699491SMichael Ellerman if (!ppmu) 1145f2699491SMichael Ellerman return; 1146f2699491SMichael Ellerman local_irq_save(flags); 114769111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1148f2699491SMichael Ellerman 1149f2699491SMichael Ellerman if (!cpuhw->disabled) { 1150f2699491SMichael Ellerman /* 1151f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 1152f2699491SMichael Ellerman */ 1153f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 1154f2699491SMichael Ellerman ppc_enable_pmcs(); 1155f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 1156f2699491SMichael Ellerman } 1157f2699491SMichael Ellerman 1158f2699491SMichael Ellerman /* 115976cb8a78SMichael Ellerman * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1160378a6ee9SMichael Ellerman */ 1161330a1eb7SMichael Ellerman val = mmcr0 = mfspr(SPRN_MMCR0); 1162378a6ee9SMichael Ellerman val |= MMCR0_FC; 116376cb8a78SMichael Ellerman val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 116476cb8a78SMichael Ellerman MMCR0_FC56); 1165378a6ee9SMichael Ellerman 1166378a6ee9SMichael Ellerman /* 1167378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 1168378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 1169378a6ee9SMichael Ellerman * before we return. 1170378a6ee9SMichael Ellerman */ 1171378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 1172378a6ee9SMichael Ellerman mb(); 1173378a6ee9SMichael Ellerman 1174378a6ee9SMichael Ellerman /* 1175f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 1176f2699491SMichael Ellerman */ 1177f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1178f2699491SMichael Ellerman mtspr(SPRN_MMCRA, 1179f2699491SMichael Ellerman cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1180f2699491SMichael Ellerman mb(); 1181f2699491SMichael Ellerman } 1182f2699491SMichael Ellerman 1183378a6ee9SMichael Ellerman cpuhw->disabled = 1; 1184378a6ee9SMichael Ellerman cpuhw->n_added = 0; 1185330a1eb7SMichael Ellerman 1186330a1eb7SMichael Ellerman ebb_switch_out(mmcr0); 1187f2699491SMichael Ellerman } 1188330a1eb7SMichael Ellerman 1189f2699491SMichael Ellerman local_irq_restore(flags); 1190f2699491SMichael Ellerman } 1191f2699491SMichael Ellerman 1192f2699491SMichael Ellerman /* 1193f2699491SMichael Ellerman * Re-enable all events if disable == 0. 1194f2699491SMichael Ellerman * If we were previously disabled and events were added, then 1195f2699491SMichael Ellerman * put the new config on the PMU. 1196f2699491SMichael Ellerman */ 1197f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 1198f2699491SMichael Ellerman { 1199f2699491SMichael Ellerman struct perf_event *event; 1200f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1201f2699491SMichael Ellerman unsigned long flags; 1202f2699491SMichael Ellerman long i; 1203330a1eb7SMichael Ellerman unsigned long val, mmcr0; 1204f2699491SMichael Ellerman s64 left; 1205f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 1206f2699491SMichael Ellerman int n_lim; 1207f2699491SMichael Ellerman int idx; 1208330a1eb7SMichael Ellerman bool ebb; 1209f2699491SMichael Ellerman 1210f2699491SMichael Ellerman if (!ppmu) 1211f2699491SMichael Ellerman return; 1212f2699491SMichael Ellerman local_irq_save(flags); 12130a48843dSMichael Ellerman 121469111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 12150a48843dSMichael Ellerman if (!cpuhw->disabled) 12160a48843dSMichael Ellerman goto out; 12170a48843dSMichael Ellerman 12184ea355b5SMichael Ellerman if (cpuhw->n_events == 0) { 12194ea355b5SMichael Ellerman ppc_set_pmu_inuse(0); 12204ea355b5SMichael Ellerman goto out; 12214ea355b5SMichael Ellerman } 12224ea355b5SMichael Ellerman 1223f2699491SMichael Ellerman cpuhw->disabled = 0; 1224f2699491SMichael Ellerman 1225f2699491SMichael Ellerman /* 1226330a1eb7SMichael Ellerman * EBB requires an exclusive group and all events must have the EBB 1227330a1eb7SMichael Ellerman * flag set, or not set, so we can just check a single event. Also we 1228330a1eb7SMichael Ellerman * know we have at least one event. 1229330a1eb7SMichael Ellerman */ 1230330a1eb7SMichael Ellerman ebb = is_ebb_event(cpuhw->event[0]); 1231330a1eb7SMichael Ellerman 1232330a1eb7SMichael Ellerman /* 1233f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 1234f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 1235f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 1236f2699491SMichael Ellerman * (possibly updated for removal of events). 1237f2699491SMichael Ellerman */ 1238f2699491SMichael Ellerman if (!cpuhw->n_added) { 1239f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1240f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1241f2699491SMichael Ellerman goto out_enable; 1242f2699491SMichael Ellerman } 1243f2699491SMichael Ellerman 1244f2699491SMichael Ellerman /* 124579a4cb28SMichael Ellerman * Clear all MMCR settings and recompute them for the new set of events. 1246f2699491SMichael Ellerman */ 124779a4cb28SMichael Ellerman memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 124879a4cb28SMichael Ellerman 1249f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 12508abd818fSMichael Ellerman cpuhw->mmcr, cpuhw->event)) { 1251f2699491SMichael Ellerman /* shouldn't ever get here */ 1252f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 1253f2699491SMichael Ellerman goto out; 1254f2699491SMichael Ellerman } 1255f2699491SMichael Ellerman 12569de5cb0fSMichael Ellerman if (!(ppmu->flags & PPMU_ARCH_207S)) { 1257f2699491SMichael Ellerman /* 12589de5cb0fSMichael Ellerman * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 12599de5cb0fSMichael Ellerman * bits for the first event. We have already checked that all 12609de5cb0fSMichael Ellerman * events have the same value for these bits as the first event. 1261f2699491SMichael Ellerman */ 1262f2699491SMichael Ellerman event = cpuhw->event[0]; 1263f2699491SMichael Ellerman if (event->attr.exclude_user) 1264f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCP; 1265f2699491SMichael Ellerman if (event->attr.exclude_kernel) 1266f2699491SMichael Ellerman cpuhw->mmcr[0] |= freeze_events_kernel; 1267f2699491SMichael Ellerman if (event->attr.exclude_hv) 1268f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCHV; 12699de5cb0fSMichael Ellerman } 1270f2699491SMichael Ellerman 1271f2699491SMichael Ellerman /* 1272f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 1273f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 1274f2699491SMichael Ellerman * Then unfreeze the events. 1275f2699491SMichael Ellerman */ 1276f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 1277f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1278f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1279f2699491SMichael Ellerman mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1280f2699491SMichael Ellerman | MMCR0_FC); 12819de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 12829de5cb0fSMichael Ellerman mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); 1283f2699491SMichael Ellerman 1284f2699491SMichael Ellerman /* 1285f2699491SMichael Ellerman * Read off any pre-existing events that need to move 1286f2699491SMichael Ellerman * to another PMC. 1287f2699491SMichael Ellerman */ 1288f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1289f2699491SMichael Ellerman event = cpuhw->event[i]; 1290f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1291f2699491SMichael Ellerman power_pmu_read(event); 1292f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1293f2699491SMichael Ellerman event->hw.idx = 0; 1294f2699491SMichael Ellerman } 1295f2699491SMichael Ellerman } 1296f2699491SMichael Ellerman 1297f2699491SMichael Ellerman /* 1298f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 1299f2699491SMichael Ellerman */ 1300f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 1301f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1302f2699491SMichael Ellerman event = cpuhw->event[i]; 1303f2699491SMichael Ellerman if (event->hw.idx) 1304f2699491SMichael Ellerman continue; 1305f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1306f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1307f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1308f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1309f2699491SMichael Ellerman ++n_lim; 1310f2699491SMichael Ellerman continue; 1311f2699491SMichael Ellerman } 1312330a1eb7SMichael Ellerman 1313330a1eb7SMichael Ellerman if (ebb) 1314330a1eb7SMichael Ellerman val = local64_read(&event->hw.prev_count); 1315330a1eb7SMichael Ellerman else { 1316f2699491SMichael Ellerman val = 0; 1317f2699491SMichael Ellerman if (event->hw.sample_period) { 1318f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1319f2699491SMichael Ellerman if (left < 0x80000000L) 1320f2699491SMichael Ellerman val = 0x80000000L - left; 1321f2699491SMichael Ellerman } 1322f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1323330a1eb7SMichael Ellerman } 1324330a1eb7SMichael Ellerman 1325f2699491SMichael Ellerman event->hw.idx = idx; 1326f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1327f2699491SMichael Ellerman val = 0; 1328f2699491SMichael Ellerman write_pmc(idx, val); 1329330a1eb7SMichael Ellerman 1330f2699491SMichael Ellerman perf_event_update_userpage(event); 1331f2699491SMichael Ellerman } 1332f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 1333f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 1334f2699491SMichael Ellerman 1335f2699491SMichael Ellerman out_enable: 1336c2e37a26SMichael Ellerman pmao_restore_workaround(ebb); 1337c2e37a26SMichael Ellerman 13389de5cb0fSMichael Ellerman mmcr0 = ebb_switch_in(ebb, cpuhw); 1339330a1eb7SMichael Ellerman 1340f2699491SMichael Ellerman mb(); 1341b4d6c06cSAnshuman Khandual if (cpuhw->bhrb_users) 1342b4d6c06cSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 1343b4d6c06cSAnshuman Khandual 1344330a1eb7SMichael Ellerman write_mmcr0(cpuhw, mmcr0); 1345f2699491SMichael Ellerman 1346f2699491SMichael Ellerman /* 1347f2699491SMichael Ellerman * Enable instruction sampling if necessary 1348f2699491SMichael Ellerman */ 1349f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1350f2699491SMichael Ellerman mb(); 1351f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 1352f2699491SMichael Ellerman } 1353f2699491SMichael Ellerman 1354f2699491SMichael Ellerman out: 13553925f46bSAnshuman Khandual 1356f2699491SMichael Ellerman local_irq_restore(flags); 1357f2699491SMichael Ellerman } 1358f2699491SMichael Ellerman 1359f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1360f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1361f2699491SMichael Ellerman unsigned int *flags) 1362f2699491SMichael Ellerman { 1363f2699491SMichael Ellerman int n = 0; 1364f2699491SMichael Ellerman struct perf_event *event; 1365f2699491SMichael Ellerman 1366f2699491SMichael Ellerman if (!is_software_event(group)) { 1367f2699491SMichael Ellerman if (n >= max_count) 1368f2699491SMichael Ellerman return -1; 1369f2699491SMichael Ellerman ctrs[n] = group; 1370f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1371f2699491SMichael Ellerman events[n++] = group->hw.config; 1372f2699491SMichael Ellerman } 1373f2699491SMichael Ellerman list_for_each_entry(event, &group->sibling_list, group_entry) { 1374f2699491SMichael Ellerman if (!is_software_event(event) && 1375f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1376f2699491SMichael Ellerman if (n >= max_count) 1377f2699491SMichael Ellerman return -1; 1378f2699491SMichael Ellerman ctrs[n] = event; 1379f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1380f2699491SMichael Ellerman events[n++] = event->hw.config; 1381f2699491SMichael Ellerman } 1382f2699491SMichael Ellerman } 1383f2699491SMichael Ellerman return n; 1384f2699491SMichael Ellerman } 1385f2699491SMichael Ellerman 1386f2699491SMichael Ellerman /* 1387f2699491SMichael Ellerman * Add a event to the PMU. 1388f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1389f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1390f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1391f2699491SMichael Ellerman */ 1392f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1393f2699491SMichael Ellerman { 1394f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1395f2699491SMichael Ellerman unsigned long flags; 1396f2699491SMichael Ellerman int n0; 1397f2699491SMichael Ellerman int ret = -EAGAIN; 1398f2699491SMichael Ellerman 1399f2699491SMichael Ellerman local_irq_save(flags); 1400f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1401f2699491SMichael Ellerman 1402f2699491SMichael Ellerman /* 1403f2699491SMichael Ellerman * Add the event to the list (if there is room) 1404f2699491SMichael Ellerman * and check whether the total set is still feasible. 1405f2699491SMichael Ellerman */ 140669111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1407f2699491SMichael Ellerman n0 = cpuhw->n_events; 1408f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1409f2699491SMichael Ellerman goto out; 1410f2699491SMichael Ellerman cpuhw->event[n0] = event; 1411f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1412f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1413f2699491SMichael Ellerman 1414f53d168cSsukadev@linux.vnet.ibm.com /* 1415f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1416f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1417f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1418f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1419f53d168cSsukadev@linux.vnet.ibm.com */ 1420f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1421f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1422f53d168cSsukadev@linux.vnet.ibm.com else 1423f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1424f2699491SMichael Ellerman 1425f2699491SMichael Ellerman /* 1426f2699491SMichael Ellerman * If group events scheduling transaction was started, 1427f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1428f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1429f2699491SMichael Ellerman */ 1430f2699491SMichael Ellerman if (cpuhw->group_flag & PERF_EVENT_TXN) 1431f2699491SMichael Ellerman goto nocheck; 1432f2699491SMichael Ellerman 1433f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1434f2699491SMichael Ellerman goto out; 1435f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1436f2699491SMichael Ellerman goto out; 1437f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1438f2699491SMichael Ellerman 1439f2699491SMichael Ellerman nocheck: 1440330a1eb7SMichael Ellerman ebb_event_add(event); 1441330a1eb7SMichael Ellerman 1442f2699491SMichael Ellerman ++cpuhw->n_events; 1443f2699491SMichael Ellerman ++cpuhw->n_added; 1444f2699491SMichael Ellerman 1445f2699491SMichael Ellerman ret = 0; 1446f2699491SMichael Ellerman out: 1447ff3d79dcSAnshuman Khandual if (has_branch_stack(event)) { 14483925f46bSAnshuman Khandual power_pmu_bhrb_enable(event); 1449ff3d79dcSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1450ff3d79dcSAnshuman Khandual event->attr.branch_sample_type); 1451ff3d79dcSAnshuman Khandual } 14523925f46bSAnshuman Khandual 1453f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1454f2699491SMichael Ellerman local_irq_restore(flags); 1455f2699491SMichael Ellerman return ret; 1456f2699491SMichael Ellerman } 1457f2699491SMichael Ellerman 1458f2699491SMichael Ellerman /* 1459f2699491SMichael Ellerman * Remove a event from the PMU. 1460f2699491SMichael Ellerman */ 1461f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1462f2699491SMichael Ellerman { 1463f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1464f2699491SMichael Ellerman long i; 1465f2699491SMichael Ellerman unsigned long flags; 1466f2699491SMichael Ellerman 1467f2699491SMichael Ellerman local_irq_save(flags); 1468f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1469f2699491SMichael Ellerman 1470f2699491SMichael Ellerman power_pmu_read(event); 1471f2699491SMichael Ellerman 147269111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1473f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1474f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1475f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1476f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1477f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1478f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1479f2699491SMichael Ellerman } 1480f2699491SMichael Ellerman --cpuhw->n_events; 1481f2699491SMichael Ellerman ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1482f2699491SMichael Ellerman if (event->hw.idx) { 1483f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1484f2699491SMichael Ellerman event->hw.idx = 0; 1485f2699491SMichael Ellerman } 1486f2699491SMichael Ellerman perf_event_update_userpage(event); 1487f2699491SMichael Ellerman break; 1488f2699491SMichael Ellerman } 1489f2699491SMichael Ellerman } 1490f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1491f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1492f2699491SMichael Ellerman break; 1493f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1494f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1495f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1496f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1497f2699491SMichael Ellerman } 1498f2699491SMichael Ellerman --cpuhw->n_limited; 1499f2699491SMichael Ellerman } 1500f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1501f2699491SMichael Ellerman /* disable exceptions if no events are running */ 1502f2699491SMichael Ellerman cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1503f2699491SMichael Ellerman } 1504f2699491SMichael Ellerman 15053925f46bSAnshuman Khandual if (has_branch_stack(event)) 15063925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 15073925f46bSAnshuman Khandual 1508f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1509f2699491SMichael Ellerman local_irq_restore(flags); 1510f2699491SMichael Ellerman } 1511f2699491SMichael Ellerman 1512f2699491SMichael Ellerman /* 1513f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1514f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1515f2699491SMichael Ellerman */ 1516f2699491SMichael Ellerman 1517f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1518f2699491SMichael Ellerman { 1519f2699491SMichael Ellerman unsigned long flags; 1520f2699491SMichael Ellerman s64 left; 1521f2699491SMichael Ellerman unsigned long val; 1522f2699491SMichael Ellerman 1523f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1524f2699491SMichael Ellerman return; 1525f2699491SMichael Ellerman 1526f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1527f2699491SMichael Ellerman return; 1528f2699491SMichael Ellerman 1529f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1530f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1531f2699491SMichael Ellerman 1532f2699491SMichael Ellerman local_irq_save(flags); 1533f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1534f2699491SMichael Ellerman 1535f2699491SMichael Ellerman event->hw.state = 0; 1536f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1537f2699491SMichael Ellerman 1538f2699491SMichael Ellerman val = 0; 1539f2699491SMichael Ellerman if (left < 0x80000000L) 1540f2699491SMichael Ellerman val = 0x80000000L - left; 1541f2699491SMichael Ellerman 1542f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1543f2699491SMichael Ellerman 1544f2699491SMichael Ellerman perf_event_update_userpage(event); 1545f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1546f2699491SMichael Ellerman local_irq_restore(flags); 1547f2699491SMichael Ellerman } 1548f2699491SMichael Ellerman 1549f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1550f2699491SMichael Ellerman { 1551f2699491SMichael Ellerman unsigned long flags; 1552f2699491SMichael Ellerman 1553f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1554f2699491SMichael Ellerman return; 1555f2699491SMichael Ellerman 1556f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1557f2699491SMichael Ellerman return; 1558f2699491SMichael Ellerman 1559f2699491SMichael Ellerman local_irq_save(flags); 1560f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1561f2699491SMichael Ellerman 1562f2699491SMichael Ellerman power_pmu_read(event); 1563f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1564f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1565f2699491SMichael Ellerman 1566f2699491SMichael Ellerman perf_event_update_userpage(event); 1567f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1568f2699491SMichael Ellerman local_irq_restore(flags); 1569f2699491SMichael Ellerman } 1570f2699491SMichael Ellerman 1571f2699491SMichael Ellerman /* 1572f2699491SMichael Ellerman * Start group events scheduling transaction 1573f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1574f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1575f2699491SMichael Ellerman */ 1576e51df2c1SAnton Blanchard static void power_pmu_start_txn(struct pmu *pmu) 1577f2699491SMichael Ellerman { 157869111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1579f2699491SMichael Ellerman 1580f2699491SMichael Ellerman perf_pmu_disable(pmu); 1581f2699491SMichael Ellerman cpuhw->group_flag |= PERF_EVENT_TXN; 1582f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1583f2699491SMichael Ellerman } 1584f2699491SMichael Ellerman 1585f2699491SMichael Ellerman /* 1586f2699491SMichael Ellerman * Stop group events scheduling transaction 1587f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1588f2699491SMichael Ellerman * schedulability test. 1589f2699491SMichael Ellerman */ 1590e51df2c1SAnton Blanchard static void power_pmu_cancel_txn(struct pmu *pmu) 1591f2699491SMichael Ellerman { 159269111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1593f2699491SMichael Ellerman 1594f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1595f2699491SMichael Ellerman perf_pmu_enable(pmu); 1596f2699491SMichael Ellerman } 1597f2699491SMichael Ellerman 1598f2699491SMichael Ellerman /* 1599f2699491SMichael Ellerman * Commit group events scheduling transaction 1600f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1601f2699491SMichael Ellerman * Return 0 if success 1602f2699491SMichael Ellerman */ 1603e51df2c1SAnton Blanchard static int power_pmu_commit_txn(struct pmu *pmu) 1604f2699491SMichael Ellerman { 1605f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1606f2699491SMichael Ellerman long i, n; 1607f2699491SMichael Ellerman 1608f2699491SMichael Ellerman if (!ppmu) 1609f2699491SMichael Ellerman return -EAGAIN; 161069111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1611f2699491SMichael Ellerman n = cpuhw->n_events; 1612f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1613f2699491SMichael Ellerman return -EAGAIN; 1614f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1615f2699491SMichael Ellerman if (i < 0) 1616f2699491SMichael Ellerman return -EAGAIN; 1617f2699491SMichael Ellerman 1618f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1619f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1620f2699491SMichael Ellerman 1621f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1622f2699491SMichael Ellerman perf_pmu_enable(pmu); 1623f2699491SMichael Ellerman return 0; 1624f2699491SMichael Ellerman } 1625f2699491SMichael Ellerman 1626f2699491SMichael Ellerman /* 1627f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1628f2699491SMichael Ellerman * or 0 if not. 1629f2699491SMichael Ellerman * A event can only go on a limited PMC if it counts something 1630f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1631f2699491SMichael Ellerman * doesn't exclude any processor mode. 1632f2699491SMichael Ellerman */ 1633f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1634f2699491SMichael Ellerman unsigned int flags) 1635f2699491SMichael Ellerman { 1636f2699491SMichael Ellerman int n; 1637f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1638f2699491SMichael Ellerman 1639f2699491SMichael Ellerman if (event->attr.exclude_user 1640f2699491SMichael Ellerman || event->attr.exclude_kernel 1641f2699491SMichael Ellerman || event->attr.exclude_hv 1642f2699491SMichael Ellerman || event->attr.sample_period) 1643f2699491SMichael Ellerman return 0; 1644f2699491SMichael Ellerman 1645f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1646f2699491SMichael Ellerman return 1; 1647f2699491SMichael Ellerman 1648f2699491SMichael Ellerman /* 1649f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1650f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1651f2699491SMichael Ellerman */ 1652f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1653f2699491SMichael Ellerman return 0; 1654f2699491SMichael Ellerman 1655f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1656f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1657f2699491SMichael Ellerman 1658f2699491SMichael Ellerman return n > 0; 1659f2699491SMichael Ellerman } 1660f2699491SMichael Ellerman 1661f2699491SMichael Ellerman /* 1662f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1663f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1664f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1665f2699491SMichael Ellerman */ 1666f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1667f2699491SMichael Ellerman { 1668f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1669f2699491SMichael Ellerman int n; 1670f2699491SMichael Ellerman 1671f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1672f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1673f2699491SMichael Ellerman if (!n) 1674f2699491SMichael Ellerman return 0; 1675f2699491SMichael Ellerman return alt[0]; 1676f2699491SMichael Ellerman } 1677f2699491SMichael Ellerman 1678f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1679f2699491SMichael Ellerman static atomic_t num_events; 1680f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1681f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1682f2699491SMichael Ellerman 1683f2699491SMichael Ellerman /* 1684f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1685f2699491SMichael Ellerman */ 1686f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1687f2699491SMichael Ellerman { 1688f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1689f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1690f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1691f2699491SMichael Ellerman release_pmc_hardware(); 1692f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1693f2699491SMichael Ellerman } 1694f2699491SMichael Ellerman } 1695f2699491SMichael Ellerman 1696f2699491SMichael Ellerman /* 1697f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1698f2699491SMichael Ellerman */ 1699f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1700f2699491SMichael Ellerman { 1701f2699491SMichael Ellerman unsigned long type, op, result; 1702f2699491SMichael Ellerman int ev; 1703f2699491SMichael Ellerman 1704f2699491SMichael Ellerman if (!ppmu->cache_events) 1705f2699491SMichael Ellerman return -EINVAL; 1706f2699491SMichael Ellerman 1707f2699491SMichael Ellerman /* unpack config */ 1708f2699491SMichael Ellerman type = config & 0xff; 1709f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1710f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1711f2699491SMichael Ellerman 1712f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1713f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1714f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1715f2699491SMichael Ellerman return -EINVAL; 1716f2699491SMichael Ellerman 1717f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1718f2699491SMichael Ellerman if (ev == 0) 1719f2699491SMichael Ellerman return -EOPNOTSUPP; 1720f2699491SMichael Ellerman if (ev == -1) 1721f2699491SMichael Ellerman return -EINVAL; 1722f2699491SMichael Ellerman *eventp = ev; 1723f2699491SMichael Ellerman return 0; 1724f2699491SMichael Ellerman } 1725f2699491SMichael Ellerman 1726f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1727f2699491SMichael Ellerman { 1728f2699491SMichael Ellerman u64 ev; 1729f2699491SMichael Ellerman unsigned long flags; 1730f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1731f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1732f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1733f2699491SMichael Ellerman int n; 1734f2699491SMichael Ellerman int err; 1735f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1736f2699491SMichael Ellerman 1737f2699491SMichael Ellerman if (!ppmu) 1738f2699491SMichael Ellerman return -ENOENT; 1739f2699491SMichael Ellerman 17403925f46bSAnshuman Khandual if (has_branch_stack(event)) { 17413925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 17424d9690ddSJoel Stanley if (!(ppmu->flags & PPMU_ARCH_207S)) 17435375871dSLinus Torvalds return -EOPNOTSUPP; 17443925f46bSAnshuman Khandual } 17455375871dSLinus Torvalds 1746f2699491SMichael Ellerman switch (event->attr.type) { 1747f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1748f2699491SMichael Ellerman ev = event->attr.config; 1749f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1750f2699491SMichael Ellerman return -EOPNOTSUPP; 1751f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1752f2699491SMichael Ellerman break; 1753f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1754f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1755f2699491SMichael Ellerman if (err) 1756f2699491SMichael Ellerman return err; 1757f2699491SMichael Ellerman break; 1758f2699491SMichael Ellerman case PERF_TYPE_RAW: 1759f2699491SMichael Ellerman ev = event->attr.config; 1760f2699491SMichael Ellerman break; 1761f2699491SMichael Ellerman default: 1762f2699491SMichael Ellerman return -ENOENT; 1763f2699491SMichael Ellerman } 1764f2699491SMichael Ellerman 1765f2699491SMichael Ellerman event->hw.config_base = ev; 1766f2699491SMichael Ellerman event->hw.idx = 0; 1767f2699491SMichael Ellerman 1768f2699491SMichael Ellerman /* 1769f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1770f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1771f2699491SMichael Ellerman * the user set it to. 1772f2699491SMichael Ellerman */ 1773f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1774f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1775f2699491SMichael Ellerman 1776f2699491SMichael Ellerman /* 1777f2699491SMichael Ellerman * If this is a per-task event, then we can use 1778f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1779f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1780f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1781f2699491SMichael Ellerman */ 1782f2699491SMichael Ellerman flags = 0; 1783f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1784f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1785f2699491SMichael Ellerman 1786f2699491SMichael Ellerman /* 1787f2699491SMichael Ellerman * If this machine has limited events, check whether this 1788f2699491SMichael Ellerman * event_id could go on a limited event. 1789f2699491SMichael Ellerman */ 1790f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1791f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1792f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1793f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1794f2699491SMichael Ellerman /* 1795f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1796f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1797f2699491SMichael Ellerman * alternative goes on a normal PMC. 1798f2699491SMichael Ellerman */ 1799f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1800f2699491SMichael Ellerman if (!ev) 1801f2699491SMichael Ellerman return -EINVAL; 1802f2699491SMichael Ellerman } 1803f2699491SMichael Ellerman } 1804f2699491SMichael Ellerman 1805330a1eb7SMichael Ellerman /* Extra checks for EBB */ 1806330a1eb7SMichael Ellerman err = ebb_event_check(event); 1807330a1eb7SMichael Ellerman if (err) 1808330a1eb7SMichael Ellerman return err; 1809330a1eb7SMichael Ellerman 1810f2699491SMichael Ellerman /* 1811f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1812f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1813f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1814f2699491SMichael Ellerman */ 1815f2699491SMichael Ellerman n = 0; 1816f2699491SMichael Ellerman if (event->group_leader != event) { 1817f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1818f2699491SMichael Ellerman ctrs, events, cflags); 1819f2699491SMichael Ellerman if (n < 0) 1820f2699491SMichael Ellerman return -EINVAL; 1821f2699491SMichael Ellerman } 1822f2699491SMichael Ellerman events[n] = ev; 1823f2699491SMichael Ellerman ctrs[n] = event; 1824f2699491SMichael Ellerman cflags[n] = flags; 1825f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1826f2699491SMichael Ellerman return -EINVAL; 1827f2699491SMichael Ellerman 1828f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1829f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 18303925f46bSAnshuman Khandual 18313925f46bSAnshuman Khandual if (has_branch_stack(event)) { 18323925f46bSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 18333925f46bSAnshuman Khandual event->attr.branch_sample_type); 18343925f46bSAnshuman Khandual 18353925f46bSAnshuman Khandual if(cpuhw->bhrb_filter == -1) 18363925f46bSAnshuman Khandual return -EOPNOTSUPP; 18373925f46bSAnshuman Khandual } 18383925f46bSAnshuman Khandual 1839f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 1840f2699491SMichael Ellerman if (err) 1841f2699491SMichael Ellerman return -EINVAL; 1842f2699491SMichael Ellerman 1843f2699491SMichael Ellerman event->hw.config = events[n]; 1844f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 1845f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1846f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 1847f2699491SMichael Ellerman 1848f2699491SMichael Ellerman /* 1849330a1eb7SMichael Ellerman * For EBB events we just context switch the PMC value, we don't do any 1850330a1eb7SMichael Ellerman * of the sample_period logic. We use hw.prev_count for this. 1851330a1eb7SMichael Ellerman */ 1852330a1eb7SMichael Ellerman if (is_ebb_event(event)) 1853330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, 0); 1854330a1eb7SMichael Ellerman 1855330a1eb7SMichael Ellerman /* 1856f2699491SMichael Ellerman * See if we need to reserve the PMU. 1857f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 1858f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 1859f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 1860f2699491SMichael Ellerman */ 1861f2699491SMichael Ellerman err = 0; 1862f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 1863f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1864f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 1865f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 1866f2699491SMichael Ellerman err = -EBUSY; 1867f2699491SMichael Ellerman else 1868f2699491SMichael Ellerman atomic_inc(&num_events); 1869f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1870f2699491SMichael Ellerman } 1871f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 1872f2699491SMichael Ellerman 1873f2699491SMichael Ellerman return err; 1874f2699491SMichael Ellerman } 1875f2699491SMichael Ellerman 18765375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 18775375871dSLinus Torvalds { 18785375871dSLinus Torvalds return event->hw.idx; 18795375871dSLinus Torvalds } 18805375871dSLinus Torvalds 18811c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 18821c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 18831c53a270SSukadev Bhattiprolu { 18841c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 18851c53a270SSukadev Bhattiprolu 18861c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 18871c53a270SSukadev Bhattiprolu 18881c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 18891c53a270SSukadev Bhattiprolu } 18901c53a270SSukadev Bhattiprolu 1891e51df2c1SAnton Blanchard static struct pmu power_pmu = { 1892f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 1893f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 1894f2699491SMichael Ellerman .event_init = power_pmu_event_init, 1895f2699491SMichael Ellerman .add = power_pmu_add, 1896f2699491SMichael Ellerman .del = power_pmu_del, 1897f2699491SMichael Ellerman .start = power_pmu_start, 1898f2699491SMichael Ellerman .stop = power_pmu_stop, 1899f2699491SMichael Ellerman .read = power_pmu_read, 1900f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 1901f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 1902f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 19035375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 19043925f46bSAnshuman Khandual .flush_branch_stack = power_pmu_flush_branch_stack, 1905f2699491SMichael Ellerman }; 1906f2699491SMichael Ellerman 1907f2699491SMichael Ellerman /* 1908f2699491SMichael Ellerman * A counter has overflowed; update its count and record 1909f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 1910f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 1911f2699491SMichael Ellerman */ 1912f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 1913f2699491SMichael Ellerman struct pt_regs *regs) 1914f2699491SMichael Ellerman { 1915f2699491SMichael Ellerman u64 period = event->hw.sample_period; 1916f2699491SMichael Ellerman s64 prev, delta, left; 1917f2699491SMichael Ellerman int record = 0; 1918f2699491SMichael Ellerman 1919f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 1920f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1921f2699491SMichael Ellerman return; 1922f2699491SMichael Ellerman } 1923f2699491SMichael Ellerman 1924f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 1925f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1926f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1927f2699491SMichael Ellerman local64_add(delta, &event->count); 1928f2699491SMichael Ellerman 1929f2699491SMichael Ellerman /* 1930f2699491SMichael Ellerman * See if the total period for this event has expired, 1931f2699491SMichael Ellerman * and update for the next period. 1932f2699491SMichael Ellerman */ 1933f2699491SMichael Ellerman val = 0; 1934f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 1935e13e895fSMichael Neuling if (delta == 0) 1936e13e895fSMichael Neuling left++; 1937f2699491SMichael Ellerman if (period) { 1938f2699491SMichael Ellerman if (left <= 0) { 1939f2699491SMichael Ellerman left += period; 1940f2699491SMichael Ellerman if (left <= 0) 1941f2699491SMichael Ellerman left = period; 1942e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 1943f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1944f2699491SMichael Ellerman } 1945f2699491SMichael Ellerman if (left < 0x80000000LL) 1946f2699491SMichael Ellerman val = 0x80000000LL - left; 1947f2699491SMichael Ellerman } 1948f2699491SMichael Ellerman 1949f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1950f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1951f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 1952f2699491SMichael Ellerman perf_event_update_userpage(event); 1953f2699491SMichael Ellerman 1954f2699491SMichael Ellerman /* 1955f2699491SMichael Ellerman * Finally record data if requested. 1956f2699491SMichael Ellerman */ 1957f2699491SMichael Ellerman if (record) { 1958f2699491SMichael Ellerman struct perf_sample_data data; 1959f2699491SMichael Ellerman 1960fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 1961f2699491SMichael Ellerman 1962f2699491SMichael Ellerman if (event->attr.sample_type & PERF_SAMPLE_ADDR) 1963f2699491SMichael Ellerman perf_get_data_addr(regs, &data.addr); 1964f2699491SMichael Ellerman 19653925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 19663925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 196769111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 19683925f46bSAnshuman Khandual power_pmu_bhrb_read(cpuhw); 19693925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 19703925f46bSAnshuman Khandual } 19713925f46bSAnshuman Khandual 1972f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 1973f2699491SMichael Ellerman power_pmu_stop(event, 0); 1974f2699491SMichael Ellerman } 1975f2699491SMichael Ellerman } 1976f2699491SMichael Ellerman 1977f2699491SMichael Ellerman /* 1978f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 1979f2699491SMichael Ellerman * for an event_id. 1980f2699491SMichael Ellerman */ 1981f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 1982f2699491SMichael Ellerman { 1983f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 1984f2699491SMichael Ellerman 1985f2699491SMichael Ellerman if (flags) 1986f2699491SMichael Ellerman return flags; 1987f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 1988f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 1989f2699491SMichael Ellerman } 1990f2699491SMichael Ellerman 1991f2699491SMichael Ellerman /* 1992f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 1993f2699491SMichael Ellerman * for an event_id. 1994f2699491SMichael Ellerman */ 1995f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 1996f2699491SMichael Ellerman { 199733904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 1998f2699491SMichael Ellerman 1999e6878835Ssukadev@linux.vnet.ibm.com if (use_siar && siar_valid(regs)) 20001ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 2001e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 2002e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 200375382aa7SAnton Blanchard else 200475382aa7SAnton Blanchard return regs->nip; 2005f2699491SMichael Ellerman } 2006f2699491SMichael Ellerman 2007bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 2008f2699491SMichael Ellerman { 2009f2699491SMichael Ellerman /* 2010f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 2011f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 2012f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 2013f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 2014f2699491SMichael Ellerman * cycles from overflow. 2015f2699491SMichael Ellerman * 2016f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 2017f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 2018f2699491SMichael Ellerman * don't want to mistakenly reset them. 2019f2699491SMichael Ellerman */ 2020bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 2021bc09c219SMichael Neuling return true; 2022bc09c219SMichael Neuling 2023bc09c219SMichael Neuling return false; 2024bc09c219SMichael Neuling } 2025bc09c219SMichael Neuling 2026bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 2027bc09c219SMichael Neuling { 2028bc09c219SMichael Neuling if ((int)val < 0) 2029f2699491SMichael Ellerman return true; 2030f2699491SMichael Ellerman 2031f2699491SMichael Ellerman return false; 2032f2699491SMichael Ellerman } 2033f2699491SMichael Ellerman 2034f2699491SMichael Ellerman /* 2035f2699491SMichael Ellerman * Performance monitor interrupt stuff 2036f2699491SMichael Ellerman */ 2037f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs) 2038f2699491SMichael Ellerman { 2039bc09c219SMichael Neuling int i, j; 204069111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2041f2699491SMichael Ellerman struct perf_event *event; 2042bc09c219SMichael Neuling unsigned long val[8]; 2043bc09c219SMichael Neuling int found, active; 2044f2699491SMichael Ellerman int nmi; 2045f2699491SMichael Ellerman 2046f2699491SMichael Ellerman if (cpuhw->n_limited) 2047f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2048f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 2049f2699491SMichael Ellerman 2050f2699491SMichael Ellerman perf_read_regs(regs); 2051f2699491SMichael Ellerman 2052f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 2053f2699491SMichael Ellerman if (nmi) 2054f2699491SMichael Ellerman nmi_enter(); 2055f2699491SMichael Ellerman else 2056f2699491SMichael Ellerman irq_enter(); 2057f2699491SMichael Ellerman 2058bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 2059bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 2060bc09c219SMichael Neuling val[i] = read_pmc(i + 1); 2061bc09c219SMichael Neuling 2062bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 2063bc09c219SMichael Neuling found = 0; 2064bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 2065bc09c219SMichael Neuling if (!pmc_overflow(val[i])) 2066bc09c219SMichael Neuling continue; 2067bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 2068bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 2069bc09c219SMichael Neuling /* 2070bc09c219SMichael Neuling * We've found one that's overflowed. For active 2071bc09c219SMichael Neuling * counters we need to log this. For inactive 2072bc09c219SMichael Neuling * counters, we need to reset it anyway 2073bc09c219SMichael Neuling */ 2074bc09c219SMichael Neuling found = 1; 2075bc09c219SMichael Neuling active = 0; 2076bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 2077bc09c219SMichael Neuling event = cpuhw->event[j]; 2078bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 2079bc09c219SMichael Neuling active = 1; 2080bc09c219SMichael Neuling record_and_restart(event, val[i], regs); 2081bc09c219SMichael Neuling break; 2082bc09c219SMichael Neuling } 2083bc09c219SMichael Neuling } 2084bc09c219SMichael Neuling if (!active) 2085bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 2086bc09c219SMichael Neuling write_pmc(i + 1, 0); 2087bc09c219SMichael Neuling } 2088bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 2089bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 2090f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 2091f2699491SMichael Ellerman event = cpuhw->event[i]; 2092f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2093f2699491SMichael Ellerman continue; 2094bc09c219SMichael Neuling if (pmc_overflow_power7(val[event->hw.idx - 1])) { 2095bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 2096f2699491SMichael Ellerman found = 1; 2097bc09c219SMichael Neuling record_and_restart(event, 2098bc09c219SMichael Neuling val[event->hw.idx - 1], 2099bc09c219SMichael Neuling regs); 2100f2699491SMichael Ellerman } 2101f2699491SMichael Ellerman } 2102f2699491SMichael Ellerman } 21036772faa1SMichael Ellerman if (!found && !nmi && printk_ratelimit()) 2104bc09c219SMichael Neuling printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2105f2699491SMichael Ellerman 2106f2699491SMichael Ellerman /* 2107f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 2108f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2109f2699491SMichael Ellerman * and thus allow interrupts to occur again. 2110f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 2111f2699491SMichael Ellerman * we get back out of this interrupt. 2112f2699491SMichael Ellerman */ 2113f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 2114f2699491SMichael Ellerman 2115f2699491SMichael Ellerman if (nmi) 2116f2699491SMichael Ellerman nmi_exit(); 2117f2699491SMichael Ellerman else 2118f2699491SMichael Ellerman irq_exit(); 2119f2699491SMichael Ellerman } 2120f2699491SMichael Ellerman 2121f2699491SMichael Ellerman static void power_pmu_setup(int cpu) 2122f2699491SMichael Ellerman { 2123f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2124f2699491SMichael Ellerman 2125f2699491SMichael Ellerman if (!ppmu) 2126f2699491SMichael Ellerman return; 2127f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 2128f2699491SMichael Ellerman cpuhw->mmcr[0] = MMCR0_FC; 2129f2699491SMichael Ellerman } 2130f2699491SMichael Ellerman 2131061d19f2SPaul Gortmaker static int 2132f2699491SMichael Ellerman power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) 2133f2699491SMichael Ellerman { 2134f2699491SMichael Ellerman unsigned int cpu = (long)hcpu; 2135f2699491SMichael Ellerman 2136f2699491SMichael Ellerman switch (action & ~CPU_TASKS_FROZEN) { 2137f2699491SMichael Ellerman case CPU_UP_PREPARE: 2138f2699491SMichael Ellerman power_pmu_setup(cpu); 2139f2699491SMichael Ellerman break; 2140f2699491SMichael Ellerman 2141f2699491SMichael Ellerman default: 2142f2699491SMichael Ellerman break; 2143f2699491SMichael Ellerman } 2144f2699491SMichael Ellerman 2145f2699491SMichael Ellerman return NOTIFY_OK; 2146f2699491SMichael Ellerman } 2147f2699491SMichael Ellerman 2148061d19f2SPaul Gortmaker int register_power_pmu(struct power_pmu *pmu) 2149f2699491SMichael Ellerman { 2150f2699491SMichael Ellerman if (ppmu) 2151f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 2152f2699491SMichael Ellerman 2153f2699491SMichael Ellerman ppmu = pmu; 2154f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 2155f2699491SMichael Ellerman pmu->name); 2156f2699491SMichael Ellerman 21571c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 21581c53a270SSukadev Bhattiprolu 2159f2699491SMichael Ellerman #ifdef MSR_HV 2160f2699491SMichael Ellerman /* 2161f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 2162f2699491SMichael Ellerman */ 2163f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 2164f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 2165f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 2166f2699491SMichael Ellerman 2167f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 2168f2699491SMichael Ellerman perf_cpu_notifier(power_pmu_notifier); 2169f2699491SMichael Ellerman 2170f2699491SMichael Ellerman return 0; 2171f2699491SMichael Ellerman } 2172