12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2f2699491SMichael Ellerman /* 3f2699491SMichael Ellerman * Performance event support - powerpc architecture code 4f2699491SMichael Ellerman * 5f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 6f2699491SMichael Ellerman */ 7f2699491SMichael Ellerman #include <linux/kernel.h> 8f2699491SMichael Ellerman #include <linux/sched.h> 90c9108b0SRavi Bangoria #include <linux/sched/clock.h> 10f2699491SMichael Ellerman #include <linux/perf_event.h> 11f2699491SMichael Ellerman #include <linux/percpu.h> 12f2699491SMichael Ellerman #include <linux/hardirq.h> 1369123184SMichael Neuling #include <linux/uaccess.h> 14f2699491SMichael Ellerman #include <asm/reg.h> 15f2699491SMichael Ellerman #include <asm/pmc.h> 16f2699491SMichael Ellerman #include <asm/machdep.h> 17f2699491SMichael Ellerman #include <asm/firmware.h> 18f2699491SMichael Ellerman #include <asm/ptrace.h> 1969123184SMichael Neuling #include <asm/code-patching.h> 20f2699491SMichael Ellerman 21708597daSMadhavan Srinivasan #ifdef CONFIG_PPC64 22708597daSMadhavan Srinivasan #include "internal.h" 23708597daSMadhavan Srinivasan #endif 24708597daSMadhavan Srinivasan 253925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 263925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 273925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 28b0d436c7SAnton Blanchard #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 293925f46bSAnshuman Khandual 30f2699491SMichael Ellerman struct cpu_hw_events { 31f2699491SMichael Ellerman int n_events; 32f2699491SMichael Ellerman int n_percpu; 33f2699491SMichael Ellerman int disabled; 34f2699491SMichael Ellerman int n_added; 35f2699491SMichael Ellerman int n_limited; 36f2699491SMichael Ellerman u8 pmcs_enabled; 37f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 38f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 39f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 4078d76819SAthira Rajeev struct mmcr_regs mmcr; 41f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 42f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 43f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 44f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 45f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 46f2699491SMichael Ellerman 47fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 48f2699491SMichael Ellerman int n_txn_start; 493925f46bSAnshuman Khandual 503925f46bSAnshuman Khandual /* BHRB bits */ 513925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 52f0322f7fSAnshuman Khandual unsigned int bhrb_users; 533925f46bSAnshuman Khandual void *bhrb_context; 543925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 553925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 56356d8ce3SMadhavan Srinivasan u64 ic_init; 57f2699491SMichael Ellerman }; 583925f46bSAnshuman Khandual 59e51df2c1SAnton Blanchard static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 60f2699491SMichael Ellerman 61e51df2c1SAnton Blanchard static struct power_pmu *ppmu; 62f2699491SMichael Ellerman 63f2699491SMichael Ellerman /* 64f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 65f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 66f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 67f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 68f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 69f2699491SMichael Ellerman */ 70f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 71f2699491SMichael Ellerman 72f2699491SMichael Ellerman /* 73f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 74f2699491SMichael Ellerman * and a few other names are different. 75c718547eSMadhavan Srinivasan * Also 32-bit doesn't have MMCR3, SIER2 and SIER3. 76c718547eSMadhavan Srinivasan * Define them as zero knowing that any code path accessing 77c718547eSMadhavan Srinivasan * these registers (via mtspr/mfspr) are done under ppmu flag 78c718547eSMadhavan Srinivasan * check for PPMU_ARCH_31 and we will not enter that code path 79c718547eSMadhavan Srinivasan * for 32-bit. 80f2699491SMichael Ellerman */ 81f2699491SMichael Ellerman #ifdef CONFIG_PPC32 82f2699491SMichael Ellerman 83f2699491SMichael Ellerman #define MMCR0_FCHV 0 84f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 857a7a41f9SMichael Ellerman #define MMCR0_FC56 0 86378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 87330a1eb7SMichael Ellerman #define MMCR0_EBE 0 8876cb8a78SMichael Ellerman #define MMCR0_BHRBA 0 89330a1eb7SMichael Ellerman #define MMCR0_PMCC 0 90330a1eb7SMichael Ellerman #define MMCR0_PMCC_U6 0 91f2699491SMichael Ellerman 92f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 93c718547eSMadhavan Srinivasan #define SPRN_MMCR3 0 94c718547eSMadhavan Srinivasan #define SPRN_SIER2 0 95c718547eSMadhavan Srinivasan #define SPRN_SIER3 0 96f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 979908c826SMadhavan Srinivasan #define MMCRA_BHRB_DISABLE 0 98f2699491SMichael Ellerman 99f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 100f2699491SMichael Ellerman { 101f2699491SMichael Ellerman return 0; 102f2699491SMichael Ellerman } 103da97e184SJoel Fernandes (Google) static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { } 104f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 105f2699491SMichael Ellerman { 106f2699491SMichael Ellerman return 0; 107f2699491SMichael Ellerman } 10875382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 10975382aa7SAnton Blanchard { 11075382aa7SAnton Blanchard regs->result = 0; 11175382aa7SAnton Blanchard } 112f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 113f2699491SMichael Ellerman { 114f2699491SMichael Ellerman return 0; 115f2699491SMichael Ellerman } 116f2699491SMichael Ellerman 117e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 118e6878835Ssukadev@linux.vnet.ibm.com { 119e6878835Ssukadev@linux.vnet.ibm.com return 1; 120e6878835Ssukadev@linux.vnet.ibm.com } 121e6878835Ssukadev@linux.vnet.ibm.com 122330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) { return false; } 123330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) { return 0; } 124330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) { } 125330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) { } 1269de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 127330a1eb7SMichael Ellerman { 12878d76819SAthira Rajeev return cpuhw->mmcr.mmcr0; 129330a1eb7SMichael Ellerman } 130330a1eb7SMichael Ellerman 131d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 132d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 133acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 134da97e184SJoel Fernandes (Google) static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {} 135c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) { } 136f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 137f2699491SMichael Ellerman 138333804dcSMadhavan Srinivasan bool is_sier_available(void) 139333804dcSMadhavan Srinivasan { 140333804dcSMadhavan Srinivasan if (ppmu->flags & PPMU_HAS_SIER) 141333804dcSMadhavan Srinivasan return true; 142333804dcSMadhavan Srinivasan 143333804dcSMadhavan Srinivasan return false; 144333804dcSMadhavan Srinivasan } 145333804dcSMadhavan Srinivasan 14633904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 14733904054SMichael Ellerman { 14872e349f1SAnton Blanchard /* 14972e349f1SAnton Blanchard * When we take a performance monitor exception the regs are setup 15072e349f1SAnton Blanchard * using perf_read_regs() which overloads some fields, in particular 15172e349f1SAnton Blanchard * regs->result to tell us whether to use SIAR. 15272e349f1SAnton Blanchard * 15372e349f1SAnton Blanchard * However if the regs are from another exception, eg. a syscall, then 15472e349f1SAnton Blanchard * they have not been setup using perf_read_regs() and so regs->result 15572e349f1SAnton Blanchard * is something random. 15672e349f1SAnton Blanchard */ 15772e349f1SAnton Blanchard return ((TRAP(regs) == 0xf00) && regs->result); 15833904054SMichael Ellerman } 15933904054SMichael Ellerman 160f2699491SMichael Ellerman /* 161f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 162f2699491SMichael Ellerman */ 163f2699491SMichael Ellerman #ifdef CONFIG_PPC64 164f2699491SMichael Ellerman 165f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 166f2699491SMichael Ellerman { 167f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 168f2699491SMichael Ellerman 1697a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 170f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 171f2699491SMichael Ellerman if (slot > 1) 172f2699491SMichael Ellerman return 4 * (slot - 1); 173f2699491SMichael Ellerman } 1747a786832SMichael Ellerman 175f2699491SMichael Ellerman return 0; 176f2699491SMichael Ellerman } 177f2699491SMichael Ellerman 178f2699491SMichael Ellerman /* 179f2699491SMichael Ellerman * The user wants a data address recorded. 180f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 181f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 182f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 18358a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 18458a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 185f2699491SMichael Ellerman */ 186da97e184SJoel Fernandes (Google) static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) 187f2699491SMichael Ellerman { 188f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 18958a032c3SMichael Ellerman bool sdar_valid; 19058a032c3SMichael Ellerman 19158a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 19258a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 19358a032c3SMichael Ellerman else { 194e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 195e6878835Ssukadev@linux.vnet.ibm.com 196e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 197e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 198e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 199e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 200f04d1080SMadhavan Srinivasan else if (ppmu->flags & PPMU_NO_SIAR) 201f04d1080SMadhavan Srinivasan sdsync = MMCRA_SAMPLE_ENABLE; 202e6878835Ssukadev@linux.vnet.ibm.com else 203e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 204f2699491SMichael Ellerman 20558a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 20658a032c3SMichael Ellerman } 20758a032c3SMichael Ellerman 20858a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 209f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 210cd1231d7SMadhavan Srinivasan 211da97e184SJoel Fernandes (Google) if (is_kernel_addr(mfspr(SPRN_SDAR)) && perf_allow_kernel(&event->attr) != 0) 212cd1231d7SMadhavan Srinivasan *addrp = 0; 213f2699491SMichael Ellerman } 214f2699491SMichael Ellerman 2155682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 21668b30bb9SAnton Blanchard { 21768b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 21868b30bb9SAnton Blanchard 2198f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2208f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 2218f61aa32SMichael Ellerman 22268b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 22368b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 22468b30bb9SAnton Blanchard 2255682c460SMichael Ellerman return !!(regs->dsisr & sihv); 22668b30bb9SAnton Blanchard } 22768b30bb9SAnton Blanchard 2285682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 22968b30bb9SAnton Blanchard { 23068b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 23168b30bb9SAnton Blanchard 2328f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2338f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 2348f61aa32SMichael Ellerman 23568b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 23668b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 23768b30bb9SAnton Blanchard 2385682c460SMichael Ellerman return !!(regs->dsisr & sipr); 23968b30bb9SAnton Blanchard } 24068b30bb9SAnton Blanchard 2411ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 2421ce447b9SBenjamin Herrenschmidt { 2431ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 2441ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2451ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 2461ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2471ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2481ce447b9SBenjamin Herrenschmidt } 2491ce447b9SBenjamin Herrenschmidt 250f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 251f2699491SMichael Ellerman { 25233904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 253f2699491SMichael Ellerman 25475382aa7SAnton Blanchard if (!use_siar) 2551ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2561ce447b9SBenjamin Herrenschmidt 2571ce447b9SBenjamin Herrenschmidt /* 2581ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2591ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2601ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2611ce447b9SBenjamin Herrenschmidt * results 2621ce447b9SBenjamin Herrenschmidt */ 263cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 2641ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 265a2391b35SMadhavan Srinivasan if (is_kernel_addr(siar)) 2661ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2671ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2681ce447b9SBenjamin Herrenschmidt } 269f2699491SMichael Ellerman 270f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 2715682c460SMichael Ellerman if (regs_sipr(regs)) 272f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 2735682c460SMichael Ellerman 2745682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 275f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 2765682c460SMichael Ellerman 277f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 278f2699491SMichael Ellerman } 279f2699491SMichael Ellerman 280f2699491SMichael Ellerman /* 281f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 282f2699491SMichael Ellerman * on each interrupt. 2838f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 28475382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 28575382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 286f2699491SMichael Ellerman */ 287f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 288f2699491SMichael Ellerman { 28975382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 29075382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 29175382aa7SAnton Blanchard int use_siar; 29275382aa7SAnton Blanchard 2935682c460SMichael Ellerman regs->dsisr = mmcra; 294860aad71SMichael Ellerman 295cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2968f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 2978f61aa32SMichael Ellerman 2988f61aa32SMichael Ellerman /* 2995c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 3005c093efaSAnton Blanchard * not valid. Use pt_regs. 3015c093efaSAnton Blanchard * 3025c093efaSAnton Blanchard * If it is a marked event use the SIAR. 3035c093efaSAnton Blanchard * 3045c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 3055c093efaSAnton Blanchard * pt_regs. 3065c093efaSAnton Blanchard * 3075c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 3085c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 3095c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 3105c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 3115c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 3125c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 3135c093efaSAnton Blanchard * interrupts off hence the userspace check. 3145c093efaSAnton Blanchard */ 31575382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 31675382aa7SAnton Blanchard use_siar = 0; 31727593d72SMadhavan Srinivasan else if ((ppmu->flags & PPMU_NO_SIAR)) 31827593d72SMadhavan Srinivasan use_siar = 0; 3195c093efaSAnton Blanchard else if (marked) 3205c093efaSAnton Blanchard use_siar = 1; 3215c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 3225c093efaSAnton Blanchard use_siar = 0; 323cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 32475382aa7SAnton Blanchard use_siar = 0; 32575382aa7SAnton Blanchard else 32675382aa7SAnton Blanchard use_siar = 1; 32775382aa7SAnton Blanchard 328cbda6aa1SMichael Ellerman regs->result = use_siar; 329f2699491SMichael Ellerman } 330f2699491SMichael Ellerman 331f2699491SMichael Ellerman /* 332f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 333f2699491SMichael Ellerman * it as an NMI. 334f2699491SMichael Ellerman */ 335f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 336f2699491SMichael Ellerman { 33701417c6cSMadhavan Srinivasan return (regs->softe & IRQS_DISABLED); 338f2699491SMichael Ellerman } 339f2699491SMichael Ellerman 340e6878835Ssukadev@linux.vnet.ibm.com /* 341e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 342e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 343e6878835Ssukadev@linux.vnet.ibm.com * 344e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 345e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 346e6878835Ssukadev@linux.vnet.ibm.com */ 347e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 348e6878835Ssukadev@linux.vnet.ibm.com { 349e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 350e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 351e6878835Ssukadev@linux.vnet.ibm.com 35258a032c3SMichael Ellerman if (marked) { 35358a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 35458a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 35558a032c3SMichael Ellerman 35658a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 357e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 35858a032c3SMichael Ellerman } 359e6878835Ssukadev@linux.vnet.ibm.com 360e6878835Ssukadev@linux.vnet.ibm.com return 1; 361e6878835Ssukadev@linux.vnet.ibm.com } 362e6878835Ssukadev@linux.vnet.ibm.com 363d52f2dc4SMichael Neuling 364d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 365d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 366d52f2dc4SMichael Neuling { 367d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 368d52f2dc4SMichael Neuling } 369d52f2dc4SMichael Neuling 370d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 371d52f2dc4SMichael Neuling { 37269111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 373d52f2dc4SMichael Neuling 374d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 375d52f2dc4SMichael Neuling return; 376d52f2dc4SMichael Neuling 377d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 378d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 379d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 380d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 381d52f2dc4SMichael Neuling } 382d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 383acba3c7eSPeter Zijlstra perf_sched_cb_inc(event->ctx->pmu); 384d52f2dc4SMichael Neuling } 385d52f2dc4SMichael Neuling 386d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 387d52f2dc4SMichael Neuling { 38869111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 389d52f2dc4SMichael Neuling 390d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 391d52f2dc4SMichael Neuling return; 392d52f2dc4SMichael Neuling 393f0322f7fSAnshuman Khandual WARN_ON_ONCE(!cpuhw->bhrb_users); 394d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 395acba3c7eSPeter Zijlstra perf_sched_cb_dec(event->ctx->pmu); 396d52f2dc4SMichael Neuling 397d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 398d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 399d52f2dc4SMichael Neuling * events are active on the PMU. 400d52f2dc4SMichael Neuling */ 401d52f2dc4SMichael Neuling 402d52f2dc4SMichael Neuling /* avoid stale pointer */ 403d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 404d52f2dc4SMichael Neuling } 405d52f2dc4SMichael Neuling } 406d52f2dc4SMichael Neuling 407d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 408d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 409d52f2dc4SMichael Neuling */ 410acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 411d52f2dc4SMichael Neuling { 412acba3c7eSPeter Zijlstra if (!ppmu->bhrb_nr) 413acba3c7eSPeter Zijlstra return; 414acba3c7eSPeter Zijlstra 415acba3c7eSPeter Zijlstra if (sched_in) 416d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 417d52f2dc4SMichael Neuling } 41869123184SMichael Neuling /* Calculate the to address for a branch */ 41969123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 42069123184SMichael Neuling { 42169123184SMichael Neuling unsigned int instr; 42269123184SMichael Neuling __u64 target; 42369123184SMichael Neuling 424f41d84ddSRavi Bangoria if (is_kernel_addr(addr)) { 425fe557319SChristoph Hellwig if (copy_from_kernel_nofault(&instr, (void *)addr, 426fe557319SChristoph Hellwig sizeof(instr))) 427f41d84ddSRavi Bangoria return 0; 428f41d84ddSRavi Bangoria 42994afd069SJordan Niethe return branch_target((struct ppc_inst *)&instr); 430f41d84ddSRavi Bangoria } 43169123184SMichael Neuling 43269123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 433c0ee37e8SChristoph Hellwig if (copy_from_user_nofault(&instr, (unsigned int __user *)addr, 434c0ee37e8SChristoph Hellwig sizeof(instr))) 43569123184SMichael Neuling return 0; 43669123184SMichael Neuling 43794afd069SJordan Niethe target = branch_target((struct ppc_inst *)&instr); 43869123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 43969123184SMichael Neuling return target; 44069123184SMichael Neuling 44169123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 44269123184SMichael Neuling return target - (unsigned long)&instr + addr; 44369123184SMichael Neuling } 444d52f2dc4SMichael Neuling 445d52f2dc4SMichael Neuling /* Processing BHRB entries */ 446da97e184SJoel Fernandes (Google) static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) 447d52f2dc4SMichael Neuling { 448d52f2dc4SMichael Neuling u64 val; 449d52f2dc4SMichael Neuling u64 addr; 450506e70d1SMichael Neuling int r_index, u_index, pred; 451d52f2dc4SMichael Neuling 452d52f2dc4SMichael Neuling r_index = 0; 453d52f2dc4SMichael Neuling u_index = 0; 454d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 455d52f2dc4SMichael Neuling /* Assembly read function */ 456506e70d1SMichael Neuling val = read_bhrb(r_index++); 457506e70d1SMichael Neuling if (!val) 458d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 459d52f2dc4SMichael Neuling break; 460506e70d1SMichael Neuling else { 461d52f2dc4SMichael Neuling addr = val & BHRB_EA; 462d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 463d52f2dc4SMichael Neuling 464506e70d1SMichael Neuling if (!addr) 465506e70d1SMichael Neuling /* invalid entry */ 466d52f2dc4SMichael Neuling continue; 467d52f2dc4SMichael Neuling 468bb19af81SMadhavan Srinivasan /* 469bb19af81SMadhavan Srinivasan * BHRB rolling buffer could very much contain the kernel 470bb19af81SMadhavan Srinivasan * addresses at this point. Check the privileges before 471bb19af81SMadhavan Srinivasan * exporting it to userspace (avoid exposure of regions 472bb19af81SMadhavan Srinivasan * where we could have speculative execution) 473bfe3b194SAthira Rajeev * Incase of ISA v3.1, BHRB will capture only user-space 474bfe3b194SAthira Rajeev * addresses, hence include a check before filtering code 475bb19af81SMadhavan Srinivasan */ 476bfe3b194SAthira Rajeev if (!(ppmu->flags & PPMU_ARCH_31) && 477bfe3b194SAthira Rajeev is_kernel_addr(addr) && perf_allow_kernel(&event->attr) != 0) 478bb19af81SMadhavan Srinivasan continue; 479bb19af81SMadhavan Srinivasan 480506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 481506e70d1SMichael Neuling * the most recent branch). 482506e70d1SMichael Neuling * There are two types of valid entries: 483506e70d1SMichael Neuling * 1) a target entry which is the to address of a 484506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 485506e70d1SMichael Neuling * entry read from the bhrb will be branch 486506e70d1SMichael Neuling * corresponding to this target (ie. the actual 487506e70d1SMichael Neuling * blr/bctr/btar instruction). 488506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 489506e70d1SMichael Neuling * target entry proceeds this, then this is the 490506e70d1SMichael Neuling * matching branch for that target. If this is not 491506e70d1SMichael Neuling * following a target entry, then this is a branch 492506e70d1SMichael Neuling * where the target is given as an immediate field 493506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 494506e70d1SMichael Neuling * In this case we need to read the instruction from 495506e70d1SMichael Neuling * memory to determine the target/to address. 496506e70d1SMichael Neuling */ 497d52f2dc4SMichael Neuling 498d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 499506e70d1SMichael Neuling /* Target branches use two entries 500506e70d1SMichael Neuling * (ie. computed gotos/XL form) 501506e70d1SMichael Neuling */ 502506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 503d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 504d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 505d52f2dc4SMichael Neuling 506506e70d1SMichael Neuling /* Get from address in next entry */ 507506e70d1SMichael Neuling val = read_bhrb(r_index++); 508506e70d1SMichael Neuling addr = val & BHRB_EA; 509506e70d1SMichael Neuling if (val & BHRB_TARGET) { 510506e70d1SMichael Neuling /* Shouldn't have two targets in a 511506e70d1SMichael Neuling row.. Reset index and try again */ 512506e70d1SMichael Neuling r_index--; 513506e70d1SMichael Neuling addr = 0; 514d52f2dc4SMichael Neuling } 515506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 516506e70d1SMichael Neuling } else { 517506e70d1SMichael Neuling /* Branches to immediate field 518506e70d1SMichael Neuling (ie I or B form) */ 519506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 52069123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 52169123184SMichael Neuling power_pmu_bhrb_to(addr); 522506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 523506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 524506e70d1SMichael Neuling } 525506e70d1SMichael Neuling u_index++; 526506e70d1SMichael Neuling 527d52f2dc4SMichael Neuling } 528d52f2dc4SMichael Neuling } 529d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 530bbfd5e4fSKan Liang cpuhw->bhrb_stack.hw_idx = -1ULL; 531d52f2dc4SMichael Neuling return; 532d52f2dc4SMichael Neuling } 533d52f2dc4SMichael Neuling 534330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) 535330a1eb7SMichael Ellerman { 536330a1eb7SMichael Ellerman /* 537330a1eb7SMichael Ellerman * This could be a per-PMU callback, but we'd rather avoid the cost. We 538330a1eb7SMichael Ellerman * check that the PMU supports EBB, meaning those that don't can still 539330a1eb7SMichael Ellerman * use bit 63 of the event code for something else if they wish. 540330a1eb7SMichael Ellerman */ 5414d9690ddSJoel Stanley return (ppmu->flags & PPMU_ARCH_207S) && 5428d7c55d0SMichael Ellerman ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 543330a1eb7SMichael Ellerman } 544330a1eb7SMichael Ellerman 545330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) 546330a1eb7SMichael Ellerman { 547330a1eb7SMichael Ellerman struct perf_event *leader = event->group_leader; 548330a1eb7SMichael Ellerman 549330a1eb7SMichael Ellerman /* Event and group leader must agree on EBB */ 550330a1eb7SMichael Ellerman if (is_ebb_event(leader) != is_ebb_event(event)) 551330a1eb7SMichael Ellerman return -EINVAL; 552330a1eb7SMichael Ellerman 553330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 554330a1eb7SMichael Ellerman if (!(event->attach_state & PERF_ATTACH_TASK)) 555330a1eb7SMichael Ellerman return -EINVAL; 556330a1eb7SMichael Ellerman 557330a1eb7SMichael Ellerman if (!leader->attr.pinned || !leader->attr.exclusive) 558330a1eb7SMichael Ellerman return -EINVAL; 559330a1eb7SMichael Ellerman 56058b5fb00SMichael Ellerman if (event->attr.freq || 56158b5fb00SMichael Ellerman event->attr.inherit || 56258b5fb00SMichael Ellerman event->attr.sample_type || 56358b5fb00SMichael Ellerman event->attr.sample_period || 56458b5fb00SMichael Ellerman event->attr.enable_on_exec) 565330a1eb7SMichael Ellerman return -EINVAL; 566330a1eb7SMichael Ellerman } 567330a1eb7SMichael Ellerman 568330a1eb7SMichael Ellerman return 0; 569330a1eb7SMichael Ellerman } 570330a1eb7SMichael Ellerman 571330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) 572330a1eb7SMichael Ellerman { 573330a1eb7SMichael Ellerman if (!is_ebb_event(event) || current->thread.used_ebb) 574330a1eb7SMichael Ellerman return; 575330a1eb7SMichael Ellerman 576330a1eb7SMichael Ellerman /* 577330a1eb7SMichael Ellerman * IFF this is the first time we've added an EBB event, set 578330a1eb7SMichael Ellerman * PMXE in the user MMCR0 so we can detect when it's cleared by 579330a1eb7SMichael Ellerman * userspace. We need this so that we can context switch while 580330a1eb7SMichael Ellerman * userspace is in the EBB handler (where PMXE is 0). 581330a1eb7SMichael Ellerman */ 582330a1eb7SMichael Ellerman current->thread.used_ebb = 1; 583330a1eb7SMichael Ellerman current->thread.mmcr0 |= MMCR0_PMXE; 584330a1eb7SMichael Ellerman } 585330a1eb7SMichael Ellerman 586330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) 587330a1eb7SMichael Ellerman { 588330a1eb7SMichael Ellerman if (!(mmcr0 & MMCR0_EBE)) 589330a1eb7SMichael Ellerman return; 590330a1eb7SMichael Ellerman 591330a1eb7SMichael Ellerman current->thread.siar = mfspr(SPRN_SIAR); 592330a1eb7SMichael Ellerman current->thread.sier = mfspr(SPRN_SIER); 593330a1eb7SMichael Ellerman current->thread.sdar = mfspr(SPRN_SDAR); 594330a1eb7SMichael Ellerman current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 595330a1eb7SMichael Ellerman current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 596c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 597c718547eSMadhavan Srinivasan current->thread.mmcr3 = mfspr(SPRN_MMCR3); 598c718547eSMadhavan Srinivasan current->thread.sier2 = mfspr(SPRN_SIER2); 599c718547eSMadhavan Srinivasan current->thread.sier3 = mfspr(SPRN_SIER3); 600c718547eSMadhavan Srinivasan } 601330a1eb7SMichael Ellerman } 602330a1eb7SMichael Ellerman 6039de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 604330a1eb7SMichael Ellerman { 60578d76819SAthira Rajeev unsigned long mmcr0 = cpuhw->mmcr.mmcr0; 6069de5cb0fSMichael Ellerman 607330a1eb7SMichael Ellerman if (!ebb) 608330a1eb7SMichael Ellerman goto out; 609330a1eb7SMichael Ellerman 61076cb8a78SMichael Ellerman /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 61176cb8a78SMichael Ellerman mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 612330a1eb7SMichael Ellerman 613c2e37a26SMichael Ellerman /* 614c2e37a26SMichael Ellerman * Add any bits from the user MMCR0, FC or PMAO. This is compatible 615c2e37a26SMichael Ellerman * with pmao_restore_workaround() because we may add PMAO but we never 616c2e37a26SMichael Ellerman * clear it here. 617c2e37a26SMichael Ellerman */ 618330a1eb7SMichael Ellerman mmcr0 |= current->thread.mmcr0; 619330a1eb7SMichael Ellerman 620c2e37a26SMichael Ellerman /* 621c2e37a26SMichael Ellerman * Be careful not to set PMXE if userspace had it cleared. This is also 622c2e37a26SMichael Ellerman * compatible with pmao_restore_workaround() because it has already 623c2e37a26SMichael Ellerman * cleared PMXE and we leave PMAO alone. 624c2e37a26SMichael Ellerman */ 625330a1eb7SMichael Ellerman if (!(current->thread.mmcr0 & MMCR0_PMXE)) 626330a1eb7SMichael Ellerman mmcr0 &= ~MMCR0_PMXE; 627330a1eb7SMichael Ellerman 628330a1eb7SMichael Ellerman mtspr(SPRN_SIAR, current->thread.siar); 629330a1eb7SMichael Ellerman mtspr(SPRN_SIER, current->thread.sier); 630330a1eb7SMichael Ellerman mtspr(SPRN_SDAR, current->thread.sdar); 6319de5cb0fSMichael Ellerman 6329de5cb0fSMichael Ellerman /* 6339de5cb0fSMichael Ellerman * Merge the kernel & user values of MMCR2. The semantics we implement 6349de5cb0fSMichael Ellerman * are that the user MMCR2 can set bits, ie. cause counters to freeze, 6359de5cb0fSMichael Ellerman * but not clear bits. If a task wants to be able to clear bits, ie. 6369de5cb0fSMichael Ellerman * unfreeze counters, it should not set exclude_xxx in its events and 6379de5cb0fSMichael Ellerman * instead manage the MMCR2 entirely by itself. 6389de5cb0fSMichael Ellerman */ 63978d76819SAthira Rajeev mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2); 640c718547eSMadhavan Srinivasan 641c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 642c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, current->thread.mmcr3); 643c718547eSMadhavan Srinivasan mtspr(SPRN_SIER2, current->thread.sier2); 644c718547eSMadhavan Srinivasan mtspr(SPRN_SIER3, current->thread.sier3); 645c718547eSMadhavan Srinivasan } 646330a1eb7SMichael Ellerman out: 647330a1eb7SMichael Ellerman return mmcr0; 648330a1eb7SMichael Ellerman } 649c2e37a26SMichael Ellerman 650c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) 651c2e37a26SMichael Ellerman { 652c2e37a26SMichael Ellerman unsigned pmcs[6]; 653c2e37a26SMichael Ellerman 654c2e37a26SMichael Ellerman if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 655c2e37a26SMichael Ellerman return; 656c2e37a26SMichael Ellerman 657c2e37a26SMichael Ellerman /* 658c2e37a26SMichael Ellerman * On POWER8E there is a hardware defect which affects the PMU context 659c2e37a26SMichael Ellerman * switch logic, ie. power_pmu_disable/enable(). 660c2e37a26SMichael Ellerman * 661c2e37a26SMichael Ellerman * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 662c2e37a26SMichael Ellerman * by the hardware. Sometime later the actual PMU exception is 663c2e37a26SMichael Ellerman * delivered. 664c2e37a26SMichael Ellerman * 665c2e37a26SMichael Ellerman * If we context switch, or simply disable/enable, the PMU prior to the 666c2e37a26SMichael Ellerman * exception arriving, the exception will be lost when we clear PMAO. 667c2e37a26SMichael Ellerman * 668c2e37a26SMichael Ellerman * When we reenable the PMU, we will write the saved MMCR0 with PMAO 669c2e37a26SMichael Ellerman * set, and this _should_ generate an exception. However because of the 670c2e37a26SMichael Ellerman * defect no exception is generated when we write PMAO, and we get 671c2e37a26SMichael Ellerman * stuck with no counters counting but no exception delivered. 672c2e37a26SMichael Ellerman * 673c2e37a26SMichael Ellerman * The workaround is to detect this case and tweak the hardware to 674c2e37a26SMichael Ellerman * create another pending PMU exception. 675c2e37a26SMichael Ellerman * 676c2e37a26SMichael Ellerman * We do that by setting up PMC6 (cycles) for an imminent overflow and 677c2e37a26SMichael Ellerman * enabling the PMU. That causes a new exception to be generated in the 678c2e37a26SMichael Ellerman * chip, but we don't take it yet because we have interrupts hard 679c2e37a26SMichael Ellerman * disabled. We then write back the PMU state as we want it to be seen 680c2e37a26SMichael Ellerman * by the exception handler. When we reenable interrupts the exception 681c2e37a26SMichael Ellerman * handler will be called and see the correct state. 682c2e37a26SMichael Ellerman * 683c2e37a26SMichael Ellerman * The logic is the same for EBB, except that the exception is gated by 684c2e37a26SMichael Ellerman * us having interrupts hard disabled as well as the fact that we are 685c2e37a26SMichael Ellerman * not in userspace. The exception is finally delivered when we return 686c2e37a26SMichael Ellerman * to userspace. 687c2e37a26SMichael Ellerman */ 688c2e37a26SMichael Ellerman 689c2e37a26SMichael Ellerman /* Only if PMAO is set and PMAO_SYNC is clear */ 690c2e37a26SMichael Ellerman if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 691c2e37a26SMichael Ellerman return; 692c2e37a26SMichael Ellerman 693c2e37a26SMichael Ellerman /* If we're doing EBB, only if BESCR[GE] is set */ 694c2e37a26SMichael Ellerman if (ebb && !(current->thread.bescr & BESCR_GE)) 695c2e37a26SMichael Ellerman return; 696c2e37a26SMichael Ellerman 697c2e37a26SMichael Ellerman /* 698c2e37a26SMichael Ellerman * We are already soft-disabled in power_pmu_enable(). We need to hard 69958bffb5bSMadhavan Srinivasan * disable to actually prevent the PMU exception from firing. 700c2e37a26SMichael Ellerman */ 701c2e37a26SMichael Ellerman hard_irq_disable(); 702c2e37a26SMichael Ellerman 703c2e37a26SMichael Ellerman /* 704c2e37a26SMichael Ellerman * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 705c2e37a26SMichael Ellerman * Using read/write_pmc() in a for loop adds 12 function calls and 706c2e37a26SMichael Ellerman * almost doubles our code size. 707c2e37a26SMichael Ellerman */ 708c2e37a26SMichael Ellerman pmcs[0] = mfspr(SPRN_PMC1); 709c2e37a26SMichael Ellerman pmcs[1] = mfspr(SPRN_PMC2); 710c2e37a26SMichael Ellerman pmcs[2] = mfspr(SPRN_PMC3); 711c2e37a26SMichael Ellerman pmcs[3] = mfspr(SPRN_PMC4); 712c2e37a26SMichael Ellerman pmcs[4] = mfspr(SPRN_PMC5); 713c2e37a26SMichael Ellerman pmcs[5] = mfspr(SPRN_PMC6); 714c2e37a26SMichael Ellerman 715c2e37a26SMichael Ellerman /* Ensure all freeze bits are unset */ 716c2e37a26SMichael Ellerman mtspr(SPRN_MMCR2, 0); 717c2e37a26SMichael Ellerman 718c2e37a26SMichael Ellerman /* Set up PMC6 to overflow in one cycle */ 719c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, 0x7FFFFFFE); 720c2e37a26SMichael Ellerman 721c2e37a26SMichael Ellerman /* Enable exceptions and unfreeze PMC6 */ 722c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 723c2e37a26SMichael Ellerman 724c2e37a26SMichael Ellerman /* Now we need to refreeze and restore the PMCs */ 725c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 726c2e37a26SMichael Ellerman 727c2e37a26SMichael Ellerman mtspr(SPRN_PMC1, pmcs[0]); 728c2e37a26SMichael Ellerman mtspr(SPRN_PMC2, pmcs[1]); 729c2e37a26SMichael Ellerman mtspr(SPRN_PMC3, pmcs[2]); 730c2e37a26SMichael Ellerman mtspr(SPRN_PMC4, pmcs[3]); 731c2e37a26SMichael Ellerman mtspr(SPRN_PMC5, pmcs[4]); 732c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, pmcs[5]); 733c2e37a26SMichael Ellerman } 734356d8ce3SMadhavan Srinivasan 735f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 736f2699491SMichael Ellerman 737f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 738f2699491SMichael Ellerman 739f2699491SMichael Ellerman /* 740f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 741f2699491SMichael Ellerman */ 742f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 743f2699491SMichael Ellerman { 744f2699491SMichael Ellerman unsigned long val; 745f2699491SMichael Ellerman 746f2699491SMichael Ellerman switch (idx) { 747f2699491SMichael Ellerman case 1: 748f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 749f2699491SMichael Ellerman break; 750f2699491SMichael Ellerman case 2: 751f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 752f2699491SMichael Ellerman break; 753f2699491SMichael Ellerman case 3: 754f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 755f2699491SMichael Ellerman break; 756f2699491SMichael Ellerman case 4: 757f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 758f2699491SMichael Ellerman break; 759f2699491SMichael Ellerman case 5: 760f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 761f2699491SMichael Ellerman break; 762f2699491SMichael Ellerman case 6: 763f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 764f2699491SMichael Ellerman break; 765f2699491SMichael Ellerman #ifdef CONFIG_PPC64 766f2699491SMichael Ellerman case 7: 767f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 768f2699491SMichael Ellerman break; 769f2699491SMichael Ellerman case 8: 770f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 771f2699491SMichael Ellerman break; 772f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 773f2699491SMichael Ellerman default: 774f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 775f2699491SMichael Ellerman val = 0; 776f2699491SMichael Ellerman } 777f2699491SMichael Ellerman return val; 778f2699491SMichael Ellerman } 779f2699491SMichael Ellerman 780f2699491SMichael Ellerman /* 781f2699491SMichael Ellerman * Write one PMC. 782f2699491SMichael Ellerman */ 783f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 784f2699491SMichael Ellerman { 785f2699491SMichael Ellerman switch (idx) { 786f2699491SMichael Ellerman case 1: 787f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 788f2699491SMichael Ellerman break; 789f2699491SMichael Ellerman case 2: 790f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 791f2699491SMichael Ellerman break; 792f2699491SMichael Ellerman case 3: 793f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 794f2699491SMichael Ellerman break; 795f2699491SMichael Ellerman case 4: 796f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 797f2699491SMichael Ellerman break; 798f2699491SMichael Ellerman case 5: 799f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 800f2699491SMichael Ellerman break; 801f2699491SMichael Ellerman case 6: 802f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 803f2699491SMichael Ellerman break; 804f2699491SMichael Ellerman #ifdef CONFIG_PPC64 805f2699491SMichael Ellerman case 7: 806f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 807f2699491SMichael Ellerman break; 808f2699491SMichael Ellerman case 8: 809f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 810f2699491SMichael Ellerman break; 811f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 812f2699491SMichael Ellerman default: 813f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 814f2699491SMichael Ellerman } 815f2699491SMichael Ellerman } 816f2699491SMichael Ellerman 8175f6d0380SAnshuman Khandual /* Called from sysrq_handle_showregs() */ 8185f6d0380SAnshuman Khandual void perf_event_print_debug(void) 8195f6d0380SAnshuman Khandual { 8205f6d0380SAnshuman Khandual unsigned long sdar, sier, flags; 8215f6d0380SAnshuman Khandual u32 pmcs[MAX_HWEVENTS]; 8225f6d0380SAnshuman Khandual int i; 8235f6d0380SAnshuman Khandual 8244917fcb5SRavi Bangoria if (!ppmu) { 8254917fcb5SRavi Bangoria pr_info("Performance monitor hardware not registered.\n"); 8264917fcb5SRavi Bangoria return; 8274917fcb5SRavi Bangoria } 8284917fcb5SRavi Bangoria 8295f6d0380SAnshuman Khandual if (!ppmu->n_counter) 8305f6d0380SAnshuman Khandual return; 8315f6d0380SAnshuman Khandual 8325f6d0380SAnshuman Khandual local_irq_save(flags); 8335f6d0380SAnshuman Khandual 8345f6d0380SAnshuman Khandual pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 8355f6d0380SAnshuman Khandual smp_processor_id(), ppmu->name, ppmu->n_counter); 8365f6d0380SAnshuman Khandual 8375f6d0380SAnshuman Khandual for (i = 0; i < ppmu->n_counter; i++) 8385f6d0380SAnshuman Khandual pmcs[i] = read_pmc(i + 1); 8395f6d0380SAnshuman Khandual 8405f6d0380SAnshuman Khandual for (; i < MAX_HWEVENTS; i++) 8415f6d0380SAnshuman Khandual pmcs[i] = 0xdeadbeef; 8425f6d0380SAnshuman Khandual 8435f6d0380SAnshuman Khandual pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 8445f6d0380SAnshuman Khandual pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 8455f6d0380SAnshuman Khandual 8465f6d0380SAnshuman Khandual if (ppmu->n_counter > 4) 8475f6d0380SAnshuman Khandual pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 8485f6d0380SAnshuman Khandual pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 8495f6d0380SAnshuman Khandual 8505f6d0380SAnshuman Khandual pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 8515f6d0380SAnshuman Khandual mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 8525f6d0380SAnshuman Khandual 8535f6d0380SAnshuman Khandual sdar = sier = 0; 8545f6d0380SAnshuman Khandual #ifdef CONFIG_PPC64 8555f6d0380SAnshuman Khandual sdar = mfspr(SPRN_SDAR); 8565f6d0380SAnshuman Khandual 8575f6d0380SAnshuman Khandual if (ppmu->flags & PPMU_HAS_SIER) 8585f6d0380SAnshuman Khandual sier = mfspr(SPRN_SIER); 8595f6d0380SAnshuman Khandual 8604d9690ddSJoel Stanley if (ppmu->flags & PPMU_ARCH_207S) { 8615f6d0380SAnshuman Khandual pr_info("MMCR2: %016lx EBBHR: %016lx\n", 8625f6d0380SAnshuman Khandual mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 8635f6d0380SAnshuman Khandual pr_info("EBBRR: %016lx BESCR: %016lx\n", 8645f6d0380SAnshuman Khandual mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 8655f6d0380SAnshuman Khandual } 866c718547eSMadhavan Srinivasan 867c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 868c718547eSMadhavan Srinivasan pr_info("MMCR3: %016lx SIER2: %016lx SIER3: %016lx\n", 869c718547eSMadhavan Srinivasan mfspr(SPRN_MMCR3), mfspr(SPRN_SIER2), mfspr(SPRN_SIER3)); 870c718547eSMadhavan Srinivasan } 8715f6d0380SAnshuman Khandual #endif 8725f6d0380SAnshuman Khandual pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 8735f6d0380SAnshuman Khandual mfspr(SPRN_SIAR), sdar, sier); 8745f6d0380SAnshuman Khandual 8755f6d0380SAnshuman Khandual local_irq_restore(flags); 8765f6d0380SAnshuman Khandual } 8775f6d0380SAnshuman Khandual 878f2699491SMichael Ellerman /* 879f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 880f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 881f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 882f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 883f2699491SMichael Ellerman */ 884f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 885f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 886f2699491SMichael Ellerman int n_ev) 887f2699491SMichael Ellerman { 888f2699491SMichael Ellerman unsigned long mask, value, nv; 889f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 890f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 891f2699491SMichael Ellerman int i, j; 892f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 893f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 89459029136SMadhavan Srinivasan unsigned long grp_mask = ppmu->group_constraint_mask; 89559029136SMadhavan Srinivasan unsigned long grp_val = ppmu->group_constraint_val; 896f2699491SMichael Ellerman 897f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 898f2699491SMichael Ellerman return -1; 899f2699491SMichael Ellerman 900f2699491SMichael Ellerman /* First see if the events will go on as-is */ 901f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 902f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 903f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 904f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 905f2699491SMichael Ellerman cpuhw->alternatives[i]); 906f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 907f2699491SMichael Ellerman } 908f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 909f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 910f2699491SMichael Ellerman return -1; 911f2699491SMichael Ellerman } 912f2699491SMichael Ellerman value = mask = 0; 913f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 914f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 915f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 91659029136SMadhavan Srinivasan 91759029136SMadhavan Srinivasan if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0) 918f2699491SMichael Ellerman break; 91959029136SMadhavan Srinivasan 92059029136SMadhavan Srinivasan if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0]) 92159029136SMadhavan Srinivasan & (~grp_mask)) != 0) 92259029136SMadhavan Srinivasan break; 92359029136SMadhavan Srinivasan 924f2699491SMichael Ellerman value = nv; 925f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 926f2699491SMichael Ellerman } 92759029136SMadhavan Srinivasan if (i == n_ev) { 92859029136SMadhavan Srinivasan if ((value & mask & grp_mask) != (mask & grp_val)) 92959029136SMadhavan Srinivasan return -1; 93059029136SMadhavan Srinivasan else 931f2699491SMichael Ellerman return 0; /* all OK */ 93259029136SMadhavan Srinivasan } 933f2699491SMichael Ellerman 934f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 935f2699491SMichael Ellerman if (!ppmu->get_alternatives) 936f2699491SMichael Ellerman return -1; 937f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 938f2699491SMichael Ellerman choice[i] = 0; 939f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 940f2699491SMichael Ellerman cpuhw->alternatives[i]); 941f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 942f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 943f2699491SMichael Ellerman &cpuhw->amasks[i][j], 944f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 945f2699491SMichael Ellerman } 946f2699491SMichael Ellerman 947f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 948f2699491SMichael Ellerman i = 0; 949f2699491SMichael Ellerman j = -1; 950f2699491SMichael Ellerman value = mask = nv = 0; 951f2699491SMichael Ellerman while (i < n_ev) { 952f2699491SMichael Ellerman if (j >= 0) { 953f2699491SMichael Ellerman /* we're backtracking, restore context */ 954f2699491SMichael Ellerman value = svalues[i]; 955f2699491SMichael Ellerman mask = smasks[i]; 956f2699491SMichael Ellerman j = choice[i]; 957f2699491SMichael Ellerman } 958f2699491SMichael Ellerman /* 959f2699491SMichael Ellerman * See if any alternative k for event_id i, 960f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 961f2699491SMichael Ellerman */ 962f2699491SMichael Ellerman while (++j < n_alt[i]) { 963f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 964f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 965f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 966f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 967f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 968f2699491SMichael Ellerman break; 969f2699491SMichael Ellerman } 970f2699491SMichael Ellerman if (j >= n_alt[i]) { 971f2699491SMichael Ellerman /* 972f2699491SMichael Ellerman * No feasible alternative, backtrack 973f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 974f2699491SMichael Ellerman * alternatives from where we got up to. 975f2699491SMichael Ellerman */ 976f2699491SMichael Ellerman if (--i < 0) 977f2699491SMichael Ellerman return -1; 978f2699491SMichael Ellerman } else { 979f2699491SMichael Ellerman /* 980f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 981f2699491SMichael Ellerman * remember where we got up to with this event_id, 982f2699491SMichael Ellerman * go on to the next event_id, and start with 983f2699491SMichael Ellerman * the first alternative for it. 984f2699491SMichael Ellerman */ 985f2699491SMichael Ellerman choice[i] = j; 986f2699491SMichael Ellerman svalues[i] = value; 987f2699491SMichael Ellerman smasks[i] = mask; 988f2699491SMichael Ellerman value = nv; 989f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 990f2699491SMichael Ellerman ++i; 991f2699491SMichael Ellerman j = -1; 992f2699491SMichael Ellerman } 993f2699491SMichael Ellerman } 994f2699491SMichael Ellerman 995f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 996f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 997f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 998f2699491SMichael Ellerman return 0; 999f2699491SMichael Ellerman } 1000f2699491SMichael Ellerman 1001f2699491SMichael Ellerman /* 1002f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 1003f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 1004f2699491SMichael Ellerman * added events. 1005f2699491SMichael Ellerman */ 1006f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 1007f2699491SMichael Ellerman int n_prev, int n_new) 1008f2699491SMichael Ellerman { 1009f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 1010f2699491SMichael Ellerman int i, n, first; 1011f2699491SMichael Ellerman struct perf_event *event; 1012f2699491SMichael Ellerman 10139de5cb0fSMichael Ellerman /* 10149de5cb0fSMichael Ellerman * If the PMU we're on supports per event exclude settings then we 10159de5cb0fSMichael Ellerman * don't need to do any of this logic. NB. This assumes no PMU has both 10169de5cb0fSMichael Ellerman * per event exclude and limited PMCs. 10179de5cb0fSMichael Ellerman */ 10189de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 10199de5cb0fSMichael Ellerman return 0; 10209de5cb0fSMichael Ellerman 1021f2699491SMichael Ellerman n = n_prev + n_new; 1022f2699491SMichael Ellerman if (n <= 1) 1023f2699491SMichael Ellerman return 0; 1024f2699491SMichael Ellerman 1025f2699491SMichael Ellerman first = 1; 1026f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 1027f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 1028f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 1029f2699491SMichael Ellerman continue; 1030f2699491SMichael Ellerman } 1031f2699491SMichael Ellerman event = ctrs[i]; 1032f2699491SMichael Ellerman if (first) { 1033f2699491SMichael Ellerman eu = event->attr.exclude_user; 1034f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 1035f2699491SMichael Ellerman eh = event->attr.exclude_hv; 1036f2699491SMichael Ellerman first = 0; 1037f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 1038f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 1039f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 1040f2699491SMichael Ellerman return -EAGAIN; 1041f2699491SMichael Ellerman } 1042f2699491SMichael Ellerman } 1043f2699491SMichael Ellerman 1044f2699491SMichael Ellerman if (eu || ek || eh) 1045f2699491SMichael Ellerman for (i = 0; i < n; ++i) 1046f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 1047f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 1048f2699491SMichael Ellerman 1049f2699491SMichael Ellerman return 0; 1050f2699491SMichael Ellerman } 1051f2699491SMichael Ellerman 1052f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 1053f2699491SMichael Ellerman { 1054f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 1055f2699491SMichael Ellerman 1056f2699491SMichael Ellerman /* 1057f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 1058f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 1059f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 1060f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 1061027dfac6SMichael Ellerman * number of events to rollback at once. If we detect a rollback 1062f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 1063f2699491SMichael Ellerman * counters. 1064f2699491SMichael Ellerman */ 1065f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 1066f2699491SMichael Ellerman delta = 0; 1067f2699491SMichael Ellerman 1068f2699491SMichael Ellerman return delta; 1069f2699491SMichael Ellerman } 1070f2699491SMichael Ellerman 1071f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 1072f2699491SMichael Ellerman { 1073f2699491SMichael Ellerman s64 val, delta, prev; 1074f2699491SMichael Ellerman 1075f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1076f2699491SMichael Ellerman return; 1077f2699491SMichael Ellerman 1078f2699491SMichael Ellerman if (!event->hw.idx) 1079f2699491SMichael Ellerman return; 1080330a1eb7SMichael Ellerman 1081330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 1082330a1eb7SMichael Ellerman val = read_pmc(event->hw.idx); 1083330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, val); 1084330a1eb7SMichael Ellerman return; 1085330a1eb7SMichael Ellerman } 1086330a1eb7SMichael Ellerman 1087f2699491SMichael Ellerman /* 1088f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 1089f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 1090f2699491SMichael Ellerman * Therefore we treat them like NMIs. 1091f2699491SMichael Ellerman */ 1092f2699491SMichael Ellerman do { 1093f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1094f2699491SMichael Ellerman barrier(); 1095f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 1096f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1097f2699491SMichael Ellerman if (!delta) 1098f2699491SMichael Ellerman return; 1099f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1100f2699491SMichael Ellerman 1101f2699491SMichael Ellerman local64_add(delta, &event->count); 1102f5602941SAnton Blanchard 1103f5602941SAnton Blanchard /* 1104f5602941SAnton Blanchard * A number of places program the PMC with (0x80000000 - period_left). 1105f5602941SAnton Blanchard * We never want period_left to be less than 1 because we will program 1106f5602941SAnton Blanchard * the PMC with a value >= 0x800000000 and an edge detected PMC will 1107f5602941SAnton Blanchard * roll around to 0 before taking an exception. We have seen this 1108f5602941SAnton Blanchard * on POWER8. 1109f5602941SAnton Blanchard * 1110f5602941SAnton Blanchard * To fix this, clamp the minimum value of period_left to 1. 1111f5602941SAnton Blanchard */ 1112f5602941SAnton Blanchard do { 1113f5602941SAnton Blanchard prev = local64_read(&event->hw.period_left); 1114f5602941SAnton Blanchard val = prev - delta; 1115f5602941SAnton Blanchard if (val < 1) 1116f5602941SAnton Blanchard val = 1; 1117f5602941SAnton Blanchard } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1118f2699491SMichael Ellerman } 1119f2699491SMichael Ellerman 1120f2699491SMichael Ellerman /* 1121f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 1122f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 1123f2699491SMichael Ellerman * us if `event' is using such a PMC. 1124f2699491SMichael Ellerman */ 1125f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 1126f2699491SMichael Ellerman { 1127f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1128f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 1129f2699491SMichael Ellerman } 1130f2699491SMichael Ellerman 1131f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1132f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1133f2699491SMichael Ellerman { 1134f2699491SMichael Ellerman struct perf_event *event; 1135f2699491SMichael Ellerman u64 val, prev, delta; 1136f2699491SMichael Ellerman int i; 1137f2699491SMichael Ellerman 1138f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1139f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1140f2699491SMichael Ellerman if (!event->hw.idx) 1141f2699491SMichael Ellerman continue; 1142f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1143f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1144f2699491SMichael Ellerman event->hw.idx = 0; 1145f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1146f2699491SMichael Ellerman if (delta) 1147f2699491SMichael Ellerman local64_add(delta, &event->count); 1148f2699491SMichael Ellerman } 1149f2699491SMichael Ellerman } 1150f2699491SMichael Ellerman 1151f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1152f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1153f2699491SMichael Ellerman { 1154f2699491SMichael Ellerman struct perf_event *event; 1155f2699491SMichael Ellerman u64 val, prev; 1156f2699491SMichael Ellerman int i; 1157f2699491SMichael Ellerman 1158f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1159f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1160f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 1161f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1162f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1163f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 1164f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1165f2699491SMichael Ellerman perf_event_update_userpage(event); 1166f2699491SMichael Ellerman } 1167f2699491SMichael Ellerman } 1168f2699491SMichael Ellerman 1169f2699491SMichael Ellerman /* 1170f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 1171f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 1172f2699491SMichael Ellerman * other events. We try to keep the values from the limited 1173f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 1174f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 1175f2699491SMichael Ellerman * the limited events as small and consistent as possible. 1176f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 1177f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 1178f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 1179f2699491SMichael Ellerman */ 1180f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1181f2699491SMichael Ellerman { 1182f2699491SMichael Ellerman unsigned long pmc5, pmc6; 1183f2699491SMichael Ellerman 1184f2699491SMichael Ellerman if (!cpuhw->n_limited) { 1185f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1186f2699491SMichael Ellerman return; 1187f2699491SMichael Ellerman } 1188f2699491SMichael Ellerman 1189f2699491SMichael Ellerman /* 1190f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 1191f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 1192f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 1193f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 1194f2699491SMichael Ellerman * interrupt enable bits turned off. 1195f2699491SMichael Ellerman */ 1196f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1197f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 1198f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1199f2699491SMichael Ellerman "i" (SPRN_MMCR0), 1200f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1201f2699491SMichael Ellerman 1202f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 1203f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 1204f2699491SMichael Ellerman else 1205f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 1206f2699491SMichael Ellerman 1207f2699491SMichael Ellerman /* 1208f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 1209f2699491SMichael Ellerman * enable bits, if necessary. 1210f2699491SMichael Ellerman */ 1211f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1212f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1213f2699491SMichael Ellerman } 1214f2699491SMichael Ellerman 1215f2699491SMichael Ellerman /* 1216f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 1217f2699491SMichael Ellerman * events to be added or removed. 1218f2699491SMichael Ellerman */ 1219f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 1220f2699491SMichael Ellerman { 1221f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 12221cade527SAthira Rajeev unsigned long flags, mmcr0, val, mmcra; 1223f2699491SMichael Ellerman 1224f2699491SMichael Ellerman if (!ppmu) 1225f2699491SMichael Ellerman return; 1226f2699491SMichael Ellerman local_irq_save(flags); 122769111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1228f2699491SMichael Ellerman 1229f2699491SMichael Ellerman if (!cpuhw->disabled) { 1230f2699491SMichael Ellerman /* 1231f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 1232f2699491SMichael Ellerman */ 1233f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 1234f2699491SMichael Ellerman ppc_enable_pmcs(); 1235f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 1236f2699491SMichael Ellerman } 1237f2699491SMichael Ellerman 1238f2699491SMichael Ellerman /* 123976cb8a78SMichael Ellerman * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1240378a6ee9SMichael Ellerman */ 1241330a1eb7SMichael Ellerman val = mmcr0 = mfspr(SPRN_MMCR0); 1242378a6ee9SMichael Ellerman val |= MMCR0_FC; 124376cb8a78SMichael Ellerman val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 124476cb8a78SMichael Ellerman MMCR0_FC56); 1245378a6ee9SMichael Ellerman 1246378a6ee9SMichael Ellerman /* 1247378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 1248378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 1249378a6ee9SMichael Ellerman * before we return. 1250378a6ee9SMichael Ellerman */ 1251378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 1252378a6ee9SMichael Ellerman mb(); 1253e1ebd0e5SMichael Ellerman isync(); 1254378a6ee9SMichael Ellerman 12551cade527SAthira Rajeev val = mmcra = cpuhw->mmcr.mmcra; 12561cade527SAthira Rajeev 1257378a6ee9SMichael Ellerman /* 1258f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 1259f2699491SMichael Ellerman */ 12601cade527SAthira Rajeev if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) 12611cade527SAthira Rajeev val &= ~MMCRA_SAMPLE_ENABLE; 12621cade527SAthira Rajeev 12631cade527SAthira Rajeev /* Disable BHRB via mmcra (BHRBRD) for p10 */ 12641cade527SAthira Rajeev if (ppmu->flags & PPMU_ARCH_31) 12651cade527SAthira Rajeev val |= MMCRA_BHRB_DISABLE; 12661cade527SAthira Rajeev 12671cade527SAthira Rajeev /* 12681cade527SAthira Rajeev * Write SPRN_MMCRA if mmcra has either disabled 12691cade527SAthira Rajeev * instruction sampling or BHRB. 12701cade527SAthira Rajeev */ 12711cade527SAthira Rajeev if (val != mmcra) { 12721cade527SAthira Rajeev mtspr(SPRN_MMCRA, mmcra); 1273f2699491SMichael Ellerman mb(); 1274e1ebd0e5SMichael Ellerman isync(); 1275f2699491SMichael Ellerman } 1276f2699491SMichael Ellerman 1277378a6ee9SMichael Ellerman cpuhw->disabled = 1; 1278378a6ee9SMichael Ellerman cpuhw->n_added = 0; 1279330a1eb7SMichael Ellerman 1280330a1eb7SMichael Ellerman ebb_switch_out(mmcr0); 1281e1ebd0e5SMichael Ellerman 1282e1ebd0e5SMichael Ellerman #ifdef CONFIG_PPC64 1283e1ebd0e5SMichael Ellerman /* 1284e1ebd0e5SMichael Ellerman * These are readable by userspace, may contain kernel 1285e1ebd0e5SMichael Ellerman * addresses and are not switched by context switch, so clear 1286e1ebd0e5SMichael Ellerman * them now to avoid leaking anything to userspace in general 1287e1ebd0e5SMichael Ellerman * including to another process. 1288e1ebd0e5SMichael Ellerman */ 1289e1ebd0e5SMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) { 1290e1ebd0e5SMichael Ellerman mtspr(SPRN_SDAR, 0); 1291e1ebd0e5SMichael Ellerman mtspr(SPRN_SIAR, 0); 1292e1ebd0e5SMichael Ellerman } 1293e1ebd0e5SMichael Ellerman #endif 1294f2699491SMichael Ellerman } 1295330a1eb7SMichael Ellerman 1296f2699491SMichael Ellerman local_irq_restore(flags); 1297f2699491SMichael Ellerman } 1298f2699491SMichael Ellerman 1299f2699491SMichael Ellerman /* 1300f2699491SMichael Ellerman * Re-enable all events if disable == 0. 1301f2699491SMichael Ellerman * If we were previously disabled and events were added, then 1302f2699491SMichael Ellerman * put the new config on the PMU. 1303f2699491SMichael Ellerman */ 1304f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 1305f2699491SMichael Ellerman { 1306f2699491SMichael Ellerman struct perf_event *event; 1307f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1308f2699491SMichael Ellerman unsigned long flags; 1309f2699491SMichael Ellerman long i; 1310330a1eb7SMichael Ellerman unsigned long val, mmcr0; 1311f2699491SMichael Ellerman s64 left; 1312f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 1313f2699491SMichael Ellerman int n_lim; 1314f2699491SMichael Ellerman int idx; 1315330a1eb7SMichael Ellerman bool ebb; 1316f2699491SMichael Ellerman 1317f2699491SMichael Ellerman if (!ppmu) 1318f2699491SMichael Ellerman return; 1319f2699491SMichael Ellerman local_irq_save(flags); 13200a48843dSMichael Ellerman 132169111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 13220a48843dSMichael Ellerman if (!cpuhw->disabled) 13230a48843dSMichael Ellerman goto out; 13240a48843dSMichael Ellerman 13254ea355b5SMichael Ellerman if (cpuhw->n_events == 0) { 13264ea355b5SMichael Ellerman ppc_set_pmu_inuse(0); 13274ea355b5SMichael Ellerman goto out; 13284ea355b5SMichael Ellerman } 13294ea355b5SMichael Ellerman 1330f2699491SMichael Ellerman cpuhw->disabled = 0; 1331f2699491SMichael Ellerman 1332f2699491SMichael Ellerman /* 1333330a1eb7SMichael Ellerman * EBB requires an exclusive group and all events must have the EBB 1334330a1eb7SMichael Ellerman * flag set, or not set, so we can just check a single event. Also we 1335330a1eb7SMichael Ellerman * know we have at least one event. 1336330a1eb7SMichael Ellerman */ 1337330a1eb7SMichael Ellerman ebb = is_ebb_event(cpuhw->event[0]); 1338330a1eb7SMichael Ellerman 1339330a1eb7SMichael Ellerman /* 1340f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 1341f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 1342f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 1343f2699491SMichael Ellerman * (possibly updated for removal of events). 1344f2699491SMichael Ellerman */ 1345f2699491SMichael Ellerman if (!cpuhw->n_added) { 134678d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 134778d76819SAthira Rajeev mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 1348c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) 1349c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1350f2699491SMichael Ellerman goto out_enable; 1351f2699491SMichael Ellerman } 1352f2699491SMichael Ellerman 1353f2699491SMichael Ellerman /* 135479a4cb28SMichael Ellerman * Clear all MMCR settings and recompute them for the new set of events. 1355f2699491SMichael Ellerman */ 135678d76819SAthira Rajeev memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 135779a4cb28SMichael Ellerman 1358f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 135978d76819SAthira Rajeev &cpuhw->mmcr, cpuhw->event)) { 1360f2699491SMichael Ellerman /* shouldn't ever get here */ 1361f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 1362f2699491SMichael Ellerman goto out; 1363f2699491SMichael Ellerman } 1364f2699491SMichael Ellerman 13659de5cb0fSMichael Ellerman if (!(ppmu->flags & PPMU_ARCH_207S)) { 1366f2699491SMichael Ellerman /* 13679de5cb0fSMichael Ellerman * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 13689de5cb0fSMichael Ellerman * bits for the first event. We have already checked that all 13699de5cb0fSMichael Ellerman * events have the same value for these bits as the first event. 1370f2699491SMichael Ellerman */ 1371f2699491SMichael Ellerman event = cpuhw->event[0]; 1372f2699491SMichael Ellerman if (event->attr.exclude_user) 137378d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_FCP; 1374f2699491SMichael Ellerman if (event->attr.exclude_kernel) 137578d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= freeze_events_kernel; 1376f2699491SMichael Ellerman if (event->attr.exclude_hv) 137778d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_FCHV; 13789de5cb0fSMichael Ellerman } 1379f2699491SMichael Ellerman 1380f2699491SMichael Ellerman /* 1381f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 1382f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 1383f2699491SMichael Ellerman * Then unfreeze the events. 1384f2699491SMichael Ellerman */ 1385f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 138678d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 138778d76819SAthira Rajeev mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 138878d76819SAthira Rajeev mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1389f2699491SMichael Ellerman | MMCR0_FC); 13909de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 139178d76819SAthira Rajeev mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2); 1392f2699491SMichael Ellerman 1393c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) 1394c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1395f2699491SMichael Ellerman 1396f2699491SMichael Ellerman /* 1397f2699491SMichael Ellerman * Read off any pre-existing events that need to move 1398f2699491SMichael Ellerman * to another PMC. 1399f2699491SMichael Ellerman */ 1400f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1401f2699491SMichael Ellerman event = cpuhw->event[i]; 1402f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1403f2699491SMichael Ellerman power_pmu_read(event); 1404f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1405f2699491SMichael Ellerman event->hw.idx = 0; 1406f2699491SMichael Ellerman } 1407f2699491SMichael Ellerman } 1408f2699491SMichael Ellerman 1409f2699491SMichael Ellerman /* 1410f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 1411f2699491SMichael Ellerman */ 1412f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 1413f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1414f2699491SMichael Ellerman event = cpuhw->event[i]; 1415f2699491SMichael Ellerman if (event->hw.idx) 1416f2699491SMichael Ellerman continue; 1417f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1418f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1419f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1420f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1421f2699491SMichael Ellerman ++n_lim; 1422f2699491SMichael Ellerman continue; 1423f2699491SMichael Ellerman } 1424330a1eb7SMichael Ellerman 1425330a1eb7SMichael Ellerman if (ebb) 1426330a1eb7SMichael Ellerman val = local64_read(&event->hw.prev_count); 1427330a1eb7SMichael Ellerman else { 1428f2699491SMichael Ellerman val = 0; 1429f2699491SMichael Ellerman if (event->hw.sample_period) { 1430f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1431f2699491SMichael Ellerman if (left < 0x80000000L) 1432f2699491SMichael Ellerman val = 0x80000000L - left; 1433f2699491SMichael Ellerman } 1434f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1435330a1eb7SMichael Ellerman } 1436330a1eb7SMichael Ellerman 1437f2699491SMichael Ellerman event->hw.idx = idx; 1438f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1439f2699491SMichael Ellerman val = 0; 1440f2699491SMichael Ellerman write_pmc(idx, val); 1441330a1eb7SMichael Ellerman 1442f2699491SMichael Ellerman perf_event_update_userpage(event); 1443f2699491SMichael Ellerman } 1444f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 144578d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE; 1446f2699491SMichael Ellerman 1447f2699491SMichael Ellerman out_enable: 1448c2e37a26SMichael Ellerman pmao_restore_workaround(ebb); 1449c2e37a26SMichael Ellerman 14509de5cb0fSMichael Ellerman mmcr0 = ebb_switch_in(ebb, cpuhw); 1451330a1eb7SMichael Ellerman 1452f2699491SMichael Ellerman mb(); 1453b4d6c06cSAnshuman Khandual if (cpuhw->bhrb_users) 1454b4d6c06cSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 1455b4d6c06cSAnshuman Khandual 1456330a1eb7SMichael Ellerman write_mmcr0(cpuhw, mmcr0); 1457f2699491SMichael Ellerman 1458f2699491SMichael Ellerman /* 1459f2699491SMichael Ellerman * Enable instruction sampling if necessary 1460f2699491SMichael Ellerman */ 146178d76819SAthira Rajeev if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) { 1462f2699491SMichael Ellerman mb(); 146378d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra); 1464f2699491SMichael Ellerman } 1465f2699491SMichael Ellerman 1466f2699491SMichael Ellerman out: 14673925f46bSAnshuman Khandual 1468f2699491SMichael Ellerman local_irq_restore(flags); 1469f2699491SMichael Ellerman } 1470f2699491SMichael Ellerman 1471f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1472f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1473f2699491SMichael Ellerman unsigned int *flags) 1474f2699491SMichael Ellerman { 1475f2699491SMichael Ellerman int n = 0; 1476f2699491SMichael Ellerman struct perf_event *event; 1477f2699491SMichael Ellerman 14785aa04b3eSRavi Bangoria if (group->pmu->task_ctx_nr == perf_hw_context) { 1479f2699491SMichael Ellerman if (n >= max_count) 1480f2699491SMichael Ellerman return -1; 1481f2699491SMichael Ellerman ctrs[n] = group; 1482f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1483f2699491SMichael Ellerman events[n++] = group->hw.config; 1484f2699491SMichael Ellerman } 1485edb39592SPeter Zijlstra for_each_sibling_event(event, group) { 14865aa04b3eSRavi Bangoria if (event->pmu->task_ctx_nr == perf_hw_context && 1487f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1488f2699491SMichael Ellerman if (n >= max_count) 1489f2699491SMichael Ellerman return -1; 1490f2699491SMichael Ellerman ctrs[n] = event; 1491f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1492f2699491SMichael Ellerman events[n++] = event->hw.config; 1493f2699491SMichael Ellerman } 1494f2699491SMichael Ellerman } 1495f2699491SMichael Ellerman return n; 1496f2699491SMichael Ellerman } 1497f2699491SMichael Ellerman 1498f2699491SMichael Ellerman /* 1499788faab7STobias Tefke * Add an event to the PMU. 1500f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1501f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1502f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1503f2699491SMichael Ellerman */ 1504f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1505f2699491SMichael Ellerman { 1506f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1507f2699491SMichael Ellerman unsigned long flags; 1508f2699491SMichael Ellerman int n0; 1509f2699491SMichael Ellerman int ret = -EAGAIN; 1510f2699491SMichael Ellerman 1511f2699491SMichael Ellerman local_irq_save(flags); 1512f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1513f2699491SMichael Ellerman 1514f2699491SMichael Ellerman /* 1515f2699491SMichael Ellerman * Add the event to the list (if there is room) 1516f2699491SMichael Ellerman * and check whether the total set is still feasible. 1517f2699491SMichael Ellerman */ 151869111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1519f2699491SMichael Ellerman n0 = cpuhw->n_events; 1520f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1521f2699491SMichael Ellerman goto out; 1522f2699491SMichael Ellerman cpuhw->event[n0] = event; 1523f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1524f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1525f2699491SMichael Ellerman 1526f53d168cSsukadev@linux.vnet.ibm.com /* 1527f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1528f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1529f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1530f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1531f53d168cSsukadev@linux.vnet.ibm.com */ 1532f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1533f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1534f53d168cSsukadev@linux.vnet.ibm.com else 1535f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1536f2699491SMichael Ellerman 1537f2699491SMichael Ellerman /* 1538f2699491SMichael Ellerman * If group events scheduling transaction was started, 1539f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1540f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1541f2699491SMichael Ellerman */ 15428f3e5684SSukadev Bhattiprolu if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) 1543f2699491SMichael Ellerman goto nocheck; 1544f2699491SMichael Ellerman 1545f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1546f2699491SMichael Ellerman goto out; 1547f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1548f2699491SMichael Ellerman goto out; 1549f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1550f2699491SMichael Ellerman 1551f2699491SMichael Ellerman nocheck: 1552330a1eb7SMichael Ellerman ebb_event_add(event); 1553330a1eb7SMichael Ellerman 1554f2699491SMichael Ellerman ++cpuhw->n_events; 1555f2699491SMichael Ellerman ++cpuhw->n_added; 1556f2699491SMichael Ellerman 1557f2699491SMichael Ellerman ret = 0; 1558f2699491SMichael Ellerman out: 1559ff3d79dcSAnshuman Khandual if (has_branch_stack(event)) { 15603925f46bSAnshuman Khandual power_pmu_bhrb_enable(event); 1561ff3d79dcSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1562ff3d79dcSAnshuman Khandual event->attr.branch_sample_type); 1563ff3d79dcSAnshuman Khandual } 15643925f46bSAnshuman Khandual 1565f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1566f2699491SMichael Ellerman local_irq_restore(flags); 1567f2699491SMichael Ellerman return ret; 1568f2699491SMichael Ellerman } 1569f2699491SMichael Ellerman 1570f2699491SMichael Ellerman /* 1571788faab7STobias Tefke * Remove an event from the PMU. 1572f2699491SMichael Ellerman */ 1573f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1574f2699491SMichael Ellerman { 1575f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1576f2699491SMichael Ellerman long i; 1577f2699491SMichael Ellerman unsigned long flags; 1578f2699491SMichael Ellerman 1579f2699491SMichael Ellerman local_irq_save(flags); 1580f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1581f2699491SMichael Ellerman 1582f2699491SMichael Ellerman power_pmu_read(event); 1583f2699491SMichael Ellerman 158469111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1585f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1586f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1587f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1588f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1589f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1590f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1591f2699491SMichael Ellerman } 1592f2699491SMichael Ellerman --cpuhw->n_events; 159378d76819SAthira Rajeev ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr); 1594f2699491SMichael Ellerman if (event->hw.idx) { 1595f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1596f2699491SMichael Ellerman event->hw.idx = 0; 1597f2699491SMichael Ellerman } 1598f2699491SMichael Ellerman perf_event_update_userpage(event); 1599f2699491SMichael Ellerman break; 1600f2699491SMichael Ellerman } 1601f2699491SMichael Ellerman } 1602f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1603f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1604f2699491SMichael Ellerman break; 1605f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1606f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1607f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1608f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1609f2699491SMichael Ellerman } 1610f2699491SMichael Ellerman --cpuhw->n_limited; 1611f2699491SMichael Ellerman } 1612f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1613f2699491SMichael Ellerman /* disable exceptions if no events are running */ 161478d76819SAthira Rajeev cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE); 1615f2699491SMichael Ellerman } 1616f2699491SMichael Ellerman 16173925f46bSAnshuman Khandual if (has_branch_stack(event)) 16183925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 16193925f46bSAnshuman Khandual 1620f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1621f2699491SMichael Ellerman local_irq_restore(flags); 1622f2699491SMichael Ellerman } 1623f2699491SMichael Ellerman 1624f2699491SMichael Ellerman /* 1625f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1626f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1627f2699491SMichael Ellerman */ 1628f2699491SMichael Ellerman 1629f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1630f2699491SMichael Ellerman { 1631f2699491SMichael Ellerman unsigned long flags; 1632f2699491SMichael Ellerman s64 left; 1633f2699491SMichael Ellerman unsigned long val; 1634f2699491SMichael Ellerman 1635f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1636f2699491SMichael Ellerman return; 1637f2699491SMichael Ellerman 1638f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1639f2699491SMichael Ellerman return; 1640f2699491SMichael Ellerman 1641f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1642f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1643f2699491SMichael Ellerman 1644f2699491SMichael Ellerman local_irq_save(flags); 1645f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1646f2699491SMichael Ellerman 1647f2699491SMichael Ellerman event->hw.state = 0; 1648f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1649f2699491SMichael Ellerman 1650f2699491SMichael Ellerman val = 0; 1651f2699491SMichael Ellerman if (left < 0x80000000L) 1652f2699491SMichael Ellerman val = 0x80000000L - left; 1653f2699491SMichael Ellerman 1654f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1655f2699491SMichael Ellerman 1656f2699491SMichael Ellerman perf_event_update_userpage(event); 1657f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1658f2699491SMichael Ellerman local_irq_restore(flags); 1659f2699491SMichael Ellerman } 1660f2699491SMichael Ellerman 1661f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1662f2699491SMichael Ellerman { 1663f2699491SMichael Ellerman unsigned long flags; 1664f2699491SMichael Ellerman 1665f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1666f2699491SMichael Ellerman return; 1667f2699491SMichael Ellerman 1668f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1669f2699491SMichael Ellerman return; 1670f2699491SMichael Ellerman 1671f2699491SMichael Ellerman local_irq_save(flags); 1672f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1673f2699491SMichael Ellerman 1674f2699491SMichael Ellerman power_pmu_read(event); 1675f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1676f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1677f2699491SMichael Ellerman 1678f2699491SMichael Ellerman perf_event_update_userpage(event); 1679f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1680f2699491SMichael Ellerman local_irq_restore(flags); 1681f2699491SMichael Ellerman } 1682f2699491SMichael Ellerman 1683f2699491SMichael Ellerman /* 1684f2699491SMichael Ellerman * Start group events scheduling transaction 1685f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1686f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1687fbbe0701SSukadev Bhattiprolu * 1688fbbe0701SSukadev Bhattiprolu * We only support PERF_PMU_TXN_ADD transactions. Save the 1689fbbe0701SSukadev Bhattiprolu * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1690fbbe0701SSukadev Bhattiprolu * transactions. 1691f2699491SMichael Ellerman */ 1692fbbe0701SSukadev Bhattiprolu static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1693f2699491SMichael Ellerman { 169469111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1695f2699491SMichael Ellerman 1696fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1697fbbe0701SSukadev Bhattiprolu 1698fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = txn_flags; 1699fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1700fbbe0701SSukadev Bhattiprolu return; 1701fbbe0701SSukadev Bhattiprolu 1702f2699491SMichael Ellerman perf_pmu_disable(pmu); 1703f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1704f2699491SMichael Ellerman } 1705f2699491SMichael Ellerman 1706f2699491SMichael Ellerman /* 1707f2699491SMichael Ellerman * Stop group events scheduling transaction 1708f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1709f2699491SMichael Ellerman * schedulability test. 1710f2699491SMichael Ellerman */ 1711e51df2c1SAnton Blanchard static void power_pmu_cancel_txn(struct pmu *pmu) 1712f2699491SMichael Ellerman { 171369111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1714fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 1715fbbe0701SSukadev Bhattiprolu 1716fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1717fbbe0701SSukadev Bhattiprolu 1718fbbe0701SSukadev Bhattiprolu txn_flags = cpuhw->txn_flags; 1719fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1720fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1721fbbe0701SSukadev Bhattiprolu return; 1722f2699491SMichael Ellerman 1723f2699491SMichael Ellerman perf_pmu_enable(pmu); 1724f2699491SMichael Ellerman } 1725f2699491SMichael Ellerman 1726f2699491SMichael Ellerman /* 1727f2699491SMichael Ellerman * Commit group events scheduling transaction 1728f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1729f2699491SMichael Ellerman * Return 0 if success 1730f2699491SMichael Ellerman */ 1731e51df2c1SAnton Blanchard static int power_pmu_commit_txn(struct pmu *pmu) 1732f2699491SMichael Ellerman { 1733f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1734f2699491SMichael Ellerman long i, n; 1735f2699491SMichael Ellerman 1736f2699491SMichael Ellerman if (!ppmu) 1737f2699491SMichael Ellerman return -EAGAIN; 1738fbbe0701SSukadev Bhattiprolu 173969111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1740fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1741fbbe0701SSukadev Bhattiprolu 1742fbbe0701SSukadev Bhattiprolu if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 1743fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1744fbbe0701SSukadev Bhattiprolu return 0; 1745fbbe0701SSukadev Bhattiprolu } 1746fbbe0701SSukadev Bhattiprolu 1747f2699491SMichael Ellerman n = cpuhw->n_events; 1748f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1749f2699491SMichael Ellerman return -EAGAIN; 1750f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1751f2699491SMichael Ellerman if (i < 0) 1752f2699491SMichael Ellerman return -EAGAIN; 1753f2699491SMichael Ellerman 1754f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1755f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1756f2699491SMichael Ellerman 1757fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1758f2699491SMichael Ellerman perf_pmu_enable(pmu); 1759f2699491SMichael Ellerman return 0; 1760f2699491SMichael Ellerman } 1761f2699491SMichael Ellerman 1762f2699491SMichael Ellerman /* 1763f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1764f2699491SMichael Ellerman * or 0 if not. 1765788faab7STobias Tefke * An event can only go on a limited PMC if it counts something 1766f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1767f2699491SMichael Ellerman * doesn't exclude any processor mode. 1768f2699491SMichael Ellerman */ 1769f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1770f2699491SMichael Ellerman unsigned int flags) 1771f2699491SMichael Ellerman { 1772f2699491SMichael Ellerman int n; 1773f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1774f2699491SMichael Ellerman 1775f2699491SMichael Ellerman if (event->attr.exclude_user 1776f2699491SMichael Ellerman || event->attr.exclude_kernel 1777f2699491SMichael Ellerman || event->attr.exclude_hv 1778f2699491SMichael Ellerman || event->attr.sample_period) 1779f2699491SMichael Ellerman return 0; 1780f2699491SMichael Ellerman 1781f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1782f2699491SMichael Ellerman return 1; 1783f2699491SMichael Ellerman 1784f2699491SMichael Ellerman /* 1785f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1786f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1787f2699491SMichael Ellerman */ 1788f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1789f2699491SMichael Ellerman return 0; 1790f2699491SMichael Ellerman 1791f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1792f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1793f2699491SMichael Ellerman 1794f2699491SMichael Ellerman return n > 0; 1795f2699491SMichael Ellerman } 1796f2699491SMichael Ellerman 1797f2699491SMichael Ellerman /* 1798f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1799f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1800f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1801f2699491SMichael Ellerman */ 1802f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1803f2699491SMichael Ellerman { 1804f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1805f2699491SMichael Ellerman int n; 1806f2699491SMichael Ellerman 1807f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1808f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1809f2699491SMichael Ellerman if (!n) 1810f2699491SMichael Ellerman return 0; 1811f2699491SMichael Ellerman return alt[0]; 1812f2699491SMichael Ellerman } 1813f2699491SMichael Ellerman 1814f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1815f2699491SMichael Ellerman static atomic_t num_events; 1816f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1817f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1818f2699491SMichael Ellerman 1819f2699491SMichael Ellerman /* 1820f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1821f2699491SMichael Ellerman */ 1822f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1823f2699491SMichael Ellerman { 1824f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1825f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1826f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1827f2699491SMichael Ellerman release_pmc_hardware(); 1828f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1829f2699491SMichael Ellerman } 1830f2699491SMichael Ellerman } 1831f2699491SMichael Ellerman 1832f2699491SMichael Ellerman /* 1833f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1834f2699491SMichael Ellerman */ 1835f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1836f2699491SMichael Ellerman { 1837f2699491SMichael Ellerman unsigned long type, op, result; 18389d4fc86dSAthira Rajeev u64 ev; 1839f2699491SMichael Ellerman 1840f2699491SMichael Ellerman if (!ppmu->cache_events) 1841f2699491SMichael Ellerman return -EINVAL; 1842f2699491SMichael Ellerman 1843f2699491SMichael Ellerman /* unpack config */ 1844f2699491SMichael Ellerman type = config & 0xff; 1845f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1846f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1847f2699491SMichael Ellerman 1848f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1849f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1850f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1851f2699491SMichael Ellerman return -EINVAL; 1852f2699491SMichael Ellerman 1853f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1854f2699491SMichael Ellerman if (ev == 0) 1855f2699491SMichael Ellerman return -EOPNOTSUPP; 1856f2699491SMichael Ellerman if (ev == -1) 1857f2699491SMichael Ellerman return -EINVAL; 1858f2699491SMichael Ellerman *eventp = ev; 1859f2699491SMichael Ellerman return 0; 1860f2699491SMichael Ellerman } 1861f2699491SMichael Ellerman 1862b58064daSMadhavan Srinivasan static bool is_event_blacklisted(u64 ev) 1863b58064daSMadhavan Srinivasan { 1864b58064daSMadhavan Srinivasan int i; 1865b58064daSMadhavan Srinivasan 1866b58064daSMadhavan Srinivasan for (i=0; i < ppmu->n_blacklist_ev; i++) { 1867b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev[i] == ev) 1868b58064daSMadhavan Srinivasan return true; 1869b58064daSMadhavan Srinivasan } 1870b58064daSMadhavan Srinivasan 1871b58064daSMadhavan Srinivasan return false; 1872b58064daSMadhavan Srinivasan } 1873b58064daSMadhavan Srinivasan 1874f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1875f2699491SMichael Ellerman { 1876f2699491SMichael Ellerman u64 ev; 1877f2699491SMichael Ellerman unsigned long flags; 1878f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1879f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1880f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1881f2699491SMichael Ellerman int n; 1882f2699491SMichael Ellerman int err; 1883f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 18843202e35eSRavi Bangoria u64 bhrb_filter; 1885f2699491SMichael Ellerman 1886f2699491SMichael Ellerman if (!ppmu) 1887f2699491SMichael Ellerman return -ENOENT; 1888f2699491SMichael Ellerman 18893925f46bSAnshuman Khandual if (has_branch_stack(event)) { 18903925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 18914d9690ddSJoel Stanley if (!(ppmu->flags & PPMU_ARCH_207S)) 18925375871dSLinus Torvalds return -EOPNOTSUPP; 18933925f46bSAnshuman Khandual } 18945375871dSLinus Torvalds 1895f2699491SMichael Ellerman switch (event->attr.type) { 1896f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1897f2699491SMichael Ellerman ev = event->attr.config; 1898f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1899f2699491SMichael Ellerman return -EOPNOTSUPP; 1900b58064daSMadhavan Srinivasan 1901b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1902b58064daSMadhavan Srinivasan return -EINVAL; 1903f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1904f2699491SMichael Ellerman break; 1905f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1906f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1907f2699491SMichael Ellerman if (err) 1908f2699491SMichael Ellerman return err; 1909b58064daSMadhavan Srinivasan 1910b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1911b58064daSMadhavan Srinivasan return -EINVAL; 1912f2699491SMichael Ellerman break; 1913f2699491SMichael Ellerman case PERF_TYPE_RAW: 1914f2699491SMichael Ellerman ev = event->attr.config; 1915b58064daSMadhavan Srinivasan 1916b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 1917b58064daSMadhavan Srinivasan return -EINVAL; 1918f2699491SMichael Ellerman break; 1919f2699491SMichael Ellerman default: 1920f2699491SMichael Ellerman return -ENOENT; 1921f2699491SMichael Ellerman } 1922f2699491SMichael Ellerman 1923f2699491SMichael Ellerman event->hw.config_base = ev; 1924f2699491SMichael Ellerman event->hw.idx = 0; 1925f2699491SMichael Ellerman 1926f2699491SMichael Ellerman /* 1927f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1928f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1929f2699491SMichael Ellerman * the user set it to. 1930f2699491SMichael Ellerman */ 1931f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1932f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1933f2699491SMichael Ellerman 1934f2699491SMichael Ellerman /* 1935f2699491SMichael Ellerman * If this is a per-task event, then we can use 1936f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1937f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1938f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1939f2699491SMichael Ellerman */ 1940f2699491SMichael Ellerman flags = 0; 1941f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1942f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1943f2699491SMichael Ellerman 1944f2699491SMichael Ellerman /* 1945f2699491SMichael Ellerman * If this machine has limited events, check whether this 1946f2699491SMichael Ellerman * event_id could go on a limited event. 1947f2699491SMichael Ellerman */ 1948f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1949f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1950f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1951f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1952f2699491SMichael Ellerman /* 1953f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1954f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1955f2699491SMichael Ellerman * alternative goes on a normal PMC. 1956f2699491SMichael Ellerman */ 1957f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1958f2699491SMichael Ellerman if (!ev) 1959f2699491SMichael Ellerman return -EINVAL; 1960f2699491SMichael Ellerman } 1961f2699491SMichael Ellerman } 1962f2699491SMichael Ellerman 1963330a1eb7SMichael Ellerman /* Extra checks for EBB */ 1964330a1eb7SMichael Ellerman err = ebb_event_check(event); 1965330a1eb7SMichael Ellerman if (err) 1966330a1eb7SMichael Ellerman return err; 1967330a1eb7SMichael Ellerman 1968f2699491SMichael Ellerman /* 1969f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1970f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1971f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1972f2699491SMichael Ellerman */ 1973f2699491SMichael Ellerman n = 0; 1974f2699491SMichael Ellerman if (event->group_leader != event) { 1975f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1976f2699491SMichael Ellerman ctrs, events, cflags); 1977f2699491SMichael Ellerman if (n < 0) 1978f2699491SMichael Ellerman return -EINVAL; 1979f2699491SMichael Ellerman } 1980f2699491SMichael Ellerman events[n] = ev; 1981f2699491SMichael Ellerman ctrs[n] = event; 1982f2699491SMichael Ellerman cflags[n] = flags; 1983f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1984f2699491SMichael Ellerman return -EINVAL; 1985f2699491SMichael Ellerman 1986f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1987f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 19883925f46bSAnshuman Khandual 19893925f46bSAnshuman Khandual if (has_branch_stack(event)) { 19903202e35eSRavi Bangoria bhrb_filter = ppmu->bhrb_filter_map( 19913925f46bSAnshuman Khandual event->attr.branch_sample_type); 19923925f46bSAnshuman Khandual 19933202e35eSRavi Bangoria if (bhrb_filter == -1) { 199468de8867SJan Stancek put_cpu_var(cpu_hw_events); 19953925f46bSAnshuman Khandual return -EOPNOTSUPP; 19963925f46bSAnshuman Khandual } 19973202e35eSRavi Bangoria cpuhw->bhrb_filter = bhrb_filter; 199868de8867SJan Stancek } 19993925f46bSAnshuman Khandual 2000f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 2001f2699491SMichael Ellerman if (err) 2002f2699491SMichael Ellerman return -EINVAL; 2003f2699491SMichael Ellerman 2004f2699491SMichael Ellerman event->hw.config = events[n]; 2005f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 2006f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2007f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 2008f2699491SMichael Ellerman 2009f2699491SMichael Ellerman /* 2010330a1eb7SMichael Ellerman * For EBB events we just context switch the PMC value, we don't do any 2011330a1eb7SMichael Ellerman * of the sample_period logic. We use hw.prev_count for this. 2012330a1eb7SMichael Ellerman */ 2013330a1eb7SMichael Ellerman if (is_ebb_event(event)) 2014330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, 0); 2015330a1eb7SMichael Ellerman 2016330a1eb7SMichael Ellerman /* 2017f2699491SMichael Ellerman * See if we need to reserve the PMU. 2018f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 2019f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 2020f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 2021f2699491SMichael Ellerman */ 2022f2699491SMichael Ellerman err = 0; 2023f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 2024f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 2025f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 2026f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 2027f2699491SMichael Ellerman err = -EBUSY; 2028f2699491SMichael Ellerman else 2029f2699491SMichael Ellerman atomic_inc(&num_events); 2030f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 2031f2699491SMichael Ellerman } 2032f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 2033f2699491SMichael Ellerman 2034f2699491SMichael Ellerman return err; 2035f2699491SMichael Ellerman } 2036f2699491SMichael Ellerman 20375375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 20385375871dSLinus Torvalds { 20395375871dSLinus Torvalds return event->hw.idx; 20405375871dSLinus Torvalds } 20415375871dSLinus Torvalds 20421c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 20431c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 20441c53a270SSukadev Bhattiprolu { 20451c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 20461c53a270SSukadev Bhattiprolu 20471c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 20481c53a270SSukadev Bhattiprolu 20491c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 20501c53a270SSukadev Bhattiprolu } 20511c53a270SSukadev Bhattiprolu 2052e51df2c1SAnton Blanchard static struct pmu power_pmu = { 2053f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 2054f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 2055f2699491SMichael Ellerman .event_init = power_pmu_event_init, 2056f2699491SMichael Ellerman .add = power_pmu_add, 2057f2699491SMichael Ellerman .del = power_pmu_del, 2058f2699491SMichael Ellerman .start = power_pmu_start, 2059f2699491SMichael Ellerman .stop = power_pmu_stop, 2060f2699491SMichael Ellerman .read = power_pmu_read, 2061f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 2062f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 2063f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 20645375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 2065acba3c7eSPeter Zijlstra .sched_task = power_pmu_sched_task, 2066f2699491SMichael Ellerman }; 2067f2699491SMichael Ellerman 2068*4cb6a42eSKan Liang #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \ 2069*4cb6a42eSKan Liang PERF_SAMPLE_PHYS_ADDR | \ 2070*4cb6a42eSKan Liang PERF_SAMPLE_DATA_PAGE_SIZE) 2071f2699491SMichael Ellerman /* 2072f2699491SMichael Ellerman * A counter has overflowed; update its count and record 2073f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 2074f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 2075f2699491SMichael Ellerman */ 2076f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 2077f2699491SMichael Ellerman struct pt_regs *regs) 2078f2699491SMichael Ellerman { 2079f2699491SMichael Ellerman u64 period = event->hw.sample_period; 2080f2699491SMichael Ellerman s64 prev, delta, left; 2081f2699491SMichael Ellerman int record = 0; 2082f2699491SMichael Ellerman 2083f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 2084f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 2085f2699491SMichael Ellerman return; 2086f2699491SMichael Ellerman } 2087f2699491SMichael Ellerman 2088f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 2089f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 2090f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 2091f2699491SMichael Ellerman local64_add(delta, &event->count); 2092f2699491SMichael Ellerman 2093f2699491SMichael Ellerman /* 2094f2699491SMichael Ellerman * See if the total period for this event has expired, 2095f2699491SMichael Ellerman * and update for the next period. 2096f2699491SMichael Ellerman */ 2097f2699491SMichael Ellerman val = 0; 2098f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 2099e13e895fSMichael Neuling if (delta == 0) 2100e13e895fSMichael Neuling left++; 2101f2699491SMichael Ellerman if (period) { 2102f2699491SMichael Ellerman if (left <= 0) { 2103f2699491SMichael Ellerman left += period; 2104f2699491SMichael Ellerman if (left <= 0) 2105f2699491SMichael Ellerman left = period; 2106e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 2107f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2108f2699491SMichael Ellerman } 2109f2699491SMichael Ellerman if (left < 0x80000000LL) 2110f2699491SMichael Ellerman val = 0x80000000LL - left; 2111f2699491SMichael Ellerman } 2112f2699491SMichael Ellerman 2113f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 2114f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 2115f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 2116f2699491SMichael Ellerman perf_event_update_userpage(event); 2117f2699491SMichael Ellerman 2118f2699491SMichael Ellerman /* 2119f2699491SMichael Ellerman * Finally record data if requested. 2120f2699491SMichael Ellerman */ 2121f2699491SMichael Ellerman if (record) { 2122f2699491SMichael Ellerman struct perf_sample_data data; 2123f2699491SMichael Ellerman 2124fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 2125f2699491SMichael Ellerman 2126*4cb6a42eSKan Liang if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE) 2127da97e184SJoel Fernandes (Google) perf_get_data_addr(event, regs, &data.addr); 2128f2699491SMichael Ellerman 21293925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 21303925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 213169111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 2132da97e184SJoel Fernandes (Google) power_pmu_bhrb_read(event, cpuhw); 21333925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 21343925f46bSAnshuman Khandual } 21353925f46bSAnshuman Khandual 213679e96f8fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && 213779e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src) 213879e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); 213979e96f8fSMadhavan Srinivasan 2140170a315fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_WEIGHT && 2141170a315fSMadhavan Srinivasan ppmu->get_mem_weight) 2142170a315fSMadhavan Srinivasan ppmu->get_mem_weight(&data.weight); 2143170a315fSMadhavan Srinivasan 2144f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 2145f2699491SMichael Ellerman power_pmu_stop(event, 0); 2146f2699491SMichael Ellerman } 2147f2699491SMichael Ellerman } 2148f2699491SMichael Ellerman 2149f2699491SMichael Ellerman /* 2150f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 2151f2699491SMichael Ellerman * for an event_id. 2152f2699491SMichael Ellerman */ 2153f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 2154f2699491SMichael Ellerman { 2155f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 2156f2699491SMichael Ellerman 2157f2699491SMichael Ellerman if (flags) 2158f2699491SMichael Ellerman return flags; 2159f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 2160f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 2161f2699491SMichael Ellerman } 2162f2699491SMichael Ellerman 2163f2699491SMichael Ellerman /* 2164f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 2165f2699491SMichael Ellerman * for an event_id. 2166f2699491SMichael Ellerman */ 2167f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 2168f2699491SMichael Ellerman { 216933904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 2170f2699491SMichael Ellerman 2171e6878835Ssukadev@linux.vnet.ibm.com if (use_siar && siar_valid(regs)) 21721ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 2173e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 2174e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 217575382aa7SAnton Blanchard else 217675382aa7SAnton Blanchard return regs->nip; 2177f2699491SMichael Ellerman } 2178f2699491SMichael Ellerman 2179bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 2180f2699491SMichael Ellerman { 2181f2699491SMichael Ellerman /* 2182f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 2183f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 2184f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 2185f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 2186f2699491SMichael Ellerman * cycles from overflow. 2187f2699491SMichael Ellerman * 2188f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 2189f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 2190f2699491SMichael Ellerman * don't want to mistakenly reset them. 2191f2699491SMichael Ellerman */ 2192bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 2193bc09c219SMichael Neuling return true; 2194bc09c219SMichael Neuling 2195bc09c219SMichael Neuling return false; 2196bc09c219SMichael Neuling } 2197bc09c219SMichael Neuling 2198bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 2199bc09c219SMichael Neuling { 2200bc09c219SMichael Neuling if ((int)val < 0) 2201f2699491SMichael Ellerman return true; 2202f2699491SMichael Ellerman 2203f2699491SMichael Ellerman return false; 2204f2699491SMichael Ellerman } 2205f2699491SMichael Ellerman 2206f2699491SMichael Ellerman /* 2207f2699491SMichael Ellerman * Performance monitor interrupt stuff 2208f2699491SMichael Ellerman */ 22090c9108b0SRavi Bangoria static void __perf_event_interrupt(struct pt_regs *regs) 2210f2699491SMichael Ellerman { 2211bc09c219SMichael Neuling int i, j; 221269111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2213f2699491SMichael Ellerman struct perf_event *event; 2214bc09c219SMichael Neuling unsigned long val[8]; 2215bc09c219SMichael Neuling int found, active; 2216f2699491SMichael Ellerman int nmi; 2217f2699491SMichael Ellerman 2218f2699491SMichael Ellerman if (cpuhw->n_limited) 2219f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2220f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 2221f2699491SMichael Ellerman 2222f2699491SMichael Ellerman perf_read_regs(regs); 2223f2699491SMichael Ellerman 2224909adfc6SNicholas Piggin /* 2225909adfc6SNicholas Piggin * If perf interrupts hit in a local_irq_disable (soft-masked) region, 2226909adfc6SNicholas Piggin * we consider them as NMIs. This is required to prevent hash faults on 2227909adfc6SNicholas Piggin * user addresses when reading callchains. See the NMI test in 2228909adfc6SNicholas Piggin * do_hash_page. 2229909adfc6SNicholas Piggin */ 2230f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 2231f2699491SMichael Ellerman if (nmi) 2232f2699491SMichael Ellerman nmi_enter(); 2233f2699491SMichael Ellerman else 2234f2699491SMichael Ellerman irq_enter(); 2235f2699491SMichael Ellerman 2236bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 2237bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 2238bc09c219SMichael Neuling val[i] = read_pmc(i + 1); 2239bc09c219SMichael Neuling 2240bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 2241bc09c219SMichael Neuling found = 0; 2242bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 2243bc09c219SMichael Neuling if (!pmc_overflow(val[i])) 2244bc09c219SMichael Neuling continue; 2245bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 2246bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 2247bc09c219SMichael Neuling /* 2248bc09c219SMichael Neuling * We've found one that's overflowed. For active 2249bc09c219SMichael Neuling * counters we need to log this. For inactive 2250bc09c219SMichael Neuling * counters, we need to reset it anyway 2251bc09c219SMichael Neuling */ 2252bc09c219SMichael Neuling found = 1; 2253bc09c219SMichael Neuling active = 0; 2254bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 2255bc09c219SMichael Neuling event = cpuhw->event[j]; 2256bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 2257bc09c219SMichael Neuling active = 1; 2258bc09c219SMichael Neuling record_and_restart(event, val[i], regs); 2259bc09c219SMichael Neuling break; 2260bc09c219SMichael Neuling } 2261bc09c219SMichael Neuling } 2262bc09c219SMichael Neuling if (!active) 2263bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 2264bc09c219SMichael Neuling write_pmc(i + 1, 0); 2265bc09c219SMichael Neuling } 2266bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 2267bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 2268f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 2269f2699491SMichael Ellerman event = cpuhw->event[i]; 2270f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2271f2699491SMichael Ellerman continue; 2272bc09c219SMichael Neuling if (pmc_overflow_power7(val[event->hw.idx - 1])) { 2273bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 2274f2699491SMichael Ellerman found = 1; 2275bc09c219SMichael Neuling record_and_restart(event, 2276bc09c219SMichael Neuling val[event->hw.idx - 1], 2277bc09c219SMichael Neuling regs); 2278f2699491SMichael Ellerman } 2279f2699491SMichael Ellerman } 2280f2699491SMichael Ellerman } 22816772faa1SMichael Ellerman if (!found && !nmi && printk_ratelimit()) 2282bc09c219SMichael Neuling printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2283f2699491SMichael Ellerman 2284f2699491SMichael Ellerman /* 2285f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 2286f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2287f2699491SMichael Ellerman * and thus allow interrupts to occur again. 2288f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 2289f2699491SMichael Ellerman * we get back out of this interrupt. 2290f2699491SMichael Ellerman */ 229178d76819SAthira Rajeev write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0); 2292f2699491SMichael Ellerman 2293f2699491SMichael Ellerman if (nmi) 2294f2699491SMichael Ellerman nmi_exit(); 2295f2699491SMichael Ellerman else 2296f2699491SMichael Ellerman irq_exit(); 2297f2699491SMichael Ellerman } 2298f2699491SMichael Ellerman 22990c9108b0SRavi Bangoria static void perf_event_interrupt(struct pt_regs *regs) 23000c9108b0SRavi Bangoria { 23010c9108b0SRavi Bangoria u64 start_clock = sched_clock(); 23020c9108b0SRavi Bangoria 23030c9108b0SRavi Bangoria __perf_event_interrupt(regs); 23040c9108b0SRavi Bangoria perf_sample_event_took(sched_clock() - start_clock); 23050c9108b0SRavi Bangoria } 23060c9108b0SRavi Bangoria 23077c98bd72SDaniel Axtens static int power_pmu_prepare_cpu(unsigned int cpu) 2308f2699491SMichael Ellerman { 2309f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2310f2699491SMichael Ellerman 231157ecde42SThomas Gleixner if (ppmu) { 2312f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 231378d76819SAthira Rajeev cpuhw->mmcr.mmcr0 = MMCR0_FC; 2314f2699491SMichael Ellerman } 231557ecde42SThomas Gleixner return 0; 2316f2699491SMichael Ellerman } 2317f2699491SMichael Ellerman 2318061d19f2SPaul Gortmaker int register_power_pmu(struct power_pmu *pmu) 2319f2699491SMichael Ellerman { 2320f2699491SMichael Ellerman if (ppmu) 2321f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 2322f2699491SMichael Ellerman 2323f2699491SMichael Ellerman ppmu = pmu; 2324f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 2325f2699491SMichael Ellerman pmu->name); 2326f2699491SMichael Ellerman 23271c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 23281c53a270SSukadev Bhattiprolu 2329f2699491SMichael Ellerman #ifdef MSR_HV 2330f2699491SMichael Ellerman /* 2331f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 2332f2699491SMichael Ellerman */ 2333f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 2334f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 2335f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 2336f2699491SMichael Ellerman 2337f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 233873c1b41eSThomas Gleixner cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", 233957ecde42SThomas Gleixner power_pmu_prepare_cpu, NULL); 2340f2699491SMichael Ellerman return 0; 2341f2699491SMichael Ellerman } 2342708597daSMadhavan Srinivasan 2343708597daSMadhavan Srinivasan #ifdef CONFIG_PPC64 2344708597daSMadhavan Srinivasan static int __init init_ppc64_pmu(void) 2345708597daSMadhavan Srinivasan { 2346708597daSMadhavan Srinivasan /* run through all the pmu drivers one at a time */ 2347708597daSMadhavan Srinivasan if (!init_power5_pmu()) 2348708597daSMadhavan Srinivasan return 0; 2349708597daSMadhavan Srinivasan else if (!init_power5p_pmu()) 2350708597daSMadhavan Srinivasan return 0; 2351708597daSMadhavan Srinivasan else if (!init_power6_pmu()) 2352708597daSMadhavan Srinivasan return 0; 2353708597daSMadhavan Srinivasan else if (!init_power7_pmu()) 2354708597daSMadhavan Srinivasan return 0; 2355708597daSMadhavan Srinivasan else if (!init_power8_pmu()) 2356708597daSMadhavan Srinivasan return 0; 2357708597daSMadhavan Srinivasan else if (!init_power9_pmu()) 2358708597daSMadhavan Srinivasan return 0; 2359a64e697cSAthira Rajeev else if (!init_power10_pmu()) 2360a64e697cSAthira Rajeev return 0; 2361708597daSMadhavan Srinivasan else if (!init_ppc970_pmu()) 2362708597daSMadhavan Srinivasan return 0; 2363708597daSMadhavan Srinivasan else 2364be80e758SMadhavan Srinivasan return init_generic_compat_pmu(); 2365708597daSMadhavan Srinivasan } 2366708597daSMadhavan Srinivasan early_initcall(init_ppc64_pmu); 2367708597daSMadhavan Srinivasan #endif 2368