12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2f2699491SMichael Ellerman /* 3f2699491SMichael Ellerman * Performance event support - powerpc architecture code 4f2699491SMichael Ellerman * 5f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 6f2699491SMichael Ellerman */ 7f2699491SMichael Ellerman #include <linux/kernel.h> 8f2699491SMichael Ellerman #include <linux/sched.h> 90c9108b0SRavi Bangoria #include <linux/sched/clock.h> 10f2699491SMichael Ellerman #include <linux/perf_event.h> 11f2699491SMichael Ellerman #include <linux/percpu.h> 12f2699491SMichael Ellerman #include <linux/hardirq.h> 1369123184SMichael Neuling #include <linux/uaccess.h> 14f2699491SMichael Ellerman #include <asm/reg.h> 15f2699491SMichael Ellerman #include <asm/pmc.h> 16f2699491SMichael Ellerman #include <asm/machdep.h> 17f2699491SMichael Ellerman #include <asm/firmware.h> 18f2699491SMichael Ellerman #include <asm/ptrace.h> 1969123184SMichael Neuling #include <asm/code-patching.h> 205a7745b9SNicholas Piggin #include <asm/hw_irq.h> 217153d4bfSXiongwei Song #include <asm/interrupt.h> 22f2699491SMichael Ellerman 23708597daSMadhavan Srinivasan #ifdef CONFIG_PPC64 24708597daSMadhavan Srinivasan #include "internal.h" 25708597daSMadhavan Srinivasan #endif 26708597daSMadhavan Srinivasan 273925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 283925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 293925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 30b0d436c7SAnton Blanchard #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 313925f46bSAnshuman Khandual 32f2699491SMichael Ellerman struct cpu_hw_events { 33f2699491SMichael Ellerman int n_events; 34f2699491SMichael Ellerman int n_percpu; 35f2699491SMichael Ellerman int disabled; 36f2699491SMichael Ellerman int n_added; 37f2699491SMichael Ellerman int n_limited; 38f2699491SMichael Ellerman u8 pmcs_enabled; 39f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 40f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 41f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 4278d76819SAthira Rajeev struct mmcr_regs mmcr; 43f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 44f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 45f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 46f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 47f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 48f2699491SMichael Ellerman 49fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 50f2699491SMichael Ellerman int n_txn_start; 513925f46bSAnshuman Khandual 523925f46bSAnshuman Khandual /* BHRB bits */ 533925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 54f0322f7fSAnshuman Khandual unsigned int bhrb_users; 553925f46bSAnshuman Khandual void *bhrb_context; 563925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 573925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 58356d8ce3SMadhavan Srinivasan u64 ic_init; 5991f3469aSAthira Rajeev 6091f3469aSAthira Rajeev /* Store the PMC values */ 6191f3469aSAthira Rajeev unsigned long pmcs[MAX_HWEVENTS]; 62f2699491SMichael Ellerman }; 633925f46bSAnshuman Khandual 64e51df2c1SAnton Blanchard static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 65f2699491SMichael Ellerman 66e51df2c1SAnton Blanchard static struct power_pmu *ppmu; 67f2699491SMichael Ellerman 68f2699491SMichael Ellerman /* 69f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 70f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 71f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 72f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 73f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 74f2699491SMichael Ellerman */ 75f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 76f2699491SMichael Ellerman 77f2699491SMichael Ellerman /* 78f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 79f2699491SMichael Ellerman * and a few other names are different. 80c718547eSMadhavan Srinivasan * Also 32-bit doesn't have MMCR3, SIER2 and SIER3. 81c718547eSMadhavan Srinivasan * Define them as zero knowing that any code path accessing 82c718547eSMadhavan Srinivasan * these registers (via mtspr/mfspr) are done under ppmu flag 83c718547eSMadhavan Srinivasan * check for PPMU_ARCH_31 and we will not enter that code path 84c718547eSMadhavan Srinivasan * for 32-bit. 85f2699491SMichael Ellerman */ 86f2699491SMichael Ellerman #ifdef CONFIG_PPC32 87f2699491SMichael Ellerman 88f2699491SMichael Ellerman #define MMCR0_FCHV 0 89f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 907a7a41f9SMichael Ellerman #define MMCR0_FC56 0 91378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 92330a1eb7SMichael Ellerman #define MMCR0_EBE 0 9376cb8a78SMichael Ellerman #define MMCR0_BHRBA 0 94330a1eb7SMichael Ellerman #define MMCR0_PMCC 0 95330a1eb7SMichael Ellerman #define MMCR0_PMCC_U6 0 96f2699491SMichael Ellerman 97f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 98c718547eSMadhavan Srinivasan #define SPRN_MMCR3 0 99c718547eSMadhavan Srinivasan #define SPRN_SIER2 0 100c718547eSMadhavan Srinivasan #define SPRN_SIER3 0 101f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 1029908c826SMadhavan Srinivasan #define MMCRA_BHRB_DISABLE 0 10391668ab7SAthira Rajeev #define MMCR0_PMCCEXT 0 104f2699491SMichael Ellerman 105f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 106f2699491SMichael Ellerman { 107f2699491SMichael Ellerman return 0; 108f2699491SMichael Ellerman } 109da97e184SJoel Fernandes (Google) static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) { } 110f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 111f2699491SMichael Ellerman { 112f2699491SMichael Ellerman return 0; 113f2699491SMichael Ellerman } 11475382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 11575382aa7SAnton Blanchard { 11675382aa7SAnton Blanchard regs->result = 0; 11775382aa7SAnton Blanchard } 118f2699491SMichael Ellerman 119e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 120e6878835Ssukadev@linux.vnet.ibm.com { 121e6878835Ssukadev@linux.vnet.ibm.com return 1; 122e6878835Ssukadev@linux.vnet.ibm.com } 123e6878835Ssukadev@linux.vnet.ibm.com 124330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) { return false; } 125330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) { return 0; } 126330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) { } 127330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) { } 1289de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 129330a1eb7SMichael Ellerman { 13078d76819SAthira Rajeev return cpuhw->mmcr.mmcr0; 131330a1eb7SMichael Ellerman } 132330a1eb7SMichael Ellerman 133d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 134d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 135acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 136da97e184SJoel Fernandes (Google) static inline void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) {} 137c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) { } 138f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 139f2699491SMichael Ellerman 140333804dcSMadhavan Srinivasan bool is_sier_available(void) 141333804dcSMadhavan Srinivasan { 142f75e7d73SAthira Rajeev if (!ppmu) 143f75e7d73SAthira Rajeev return false; 144f75e7d73SAthira Rajeev 145333804dcSMadhavan Srinivasan if (ppmu->flags & PPMU_HAS_SIER) 146333804dcSMadhavan Srinivasan return true; 147333804dcSMadhavan Srinivasan 148333804dcSMadhavan Srinivasan return false; 149333804dcSMadhavan Srinivasan } 150333804dcSMadhavan Srinivasan 151e79b76e0SAthira Rajeev /* 152e79b76e0SAthira Rajeev * Return PMC value corresponding to the 153e79b76e0SAthira Rajeev * index passed. 154e79b76e0SAthira Rajeev */ 155e79b76e0SAthira Rajeev unsigned long get_pmcs_ext_regs(int idx) 156e79b76e0SAthira Rajeev { 157e79b76e0SAthira Rajeev struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 158e79b76e0SAthira Rajeev 159e79b76e0SAthira Rajeev return cpuhw->pmcs[idx]; 160e79b76e0SAthira Rajeev } 161e79b76e0SAthira Rajeev 16233904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 16333904054SMichael Ellerman { 16472e349f1SAnton Blanchard /* 16572e349f1SAnton Blanchard * When we take a performance monitor exception the regs are setup 16672e349f1SAnton Blanchard * using perf_read_regs() which overloads some fields, in particular 16772e349f1SAnton Blanchard * regs->result to tell us whether to use SIAR. 16872e349f1SAnton Blanchard * 16972e349f1SAnton Blanchard * However if the regs are from another exception, eg. a syscall, then 17072e349f1SAnton Blanchard * they have not been setup using perf_read_regs() and so regs->result 17172e349f1SAnton Blanchard * is something random. 17272e349f1SAnton Blanchard */ 1737153d4bfSXiongwei Song return ((TRAP(regs) == INTERRUPT_PERFMON) && regs->result); 17433904054SMichael Ellerman } 17533904054SMichael Ellerman 176f2699491SMichael Ellerman /* 177f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 178f2699491SMichael Ellerman */ 179f2699491SMichael Ellerman #ifdef CONFIG_PPC64 180f2699491SMichael Ellerman 181f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 182f2699491SMichael Ellerman { 183f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 184f2699491SMichael Ellerman 1857a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 186f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 187f2699491SMichael Ellerman if (slot > 1) 188f2699491SMichael Ellerman return 4 * (slot - 1); 189f2699491SMichael Ellerman } 1907a786832SMichael Ellerman 191f2699491SMichael Ellerman return 0; 192f2699491SMichael Ellerman } 193f2699491SMichael Ellerman 194f2699491SMichael Ellerman /* 195f2699491SMichael Ellerman * The user wants a data address recorded. 196f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 197f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 198f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 19958a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 20058a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 201f2699491SMichael Ellerman */ 202da97e184SJoel Fernandes (Google) static inline void perf_get_data_addr(struct perf_event *event, struct pt_regs *regs, u64 *addrp) 203f2699491SMichael Ellerman { 204f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 20558a032c3SMichael Ellerman bool sdar_valid; 20658a032c3SMichael Ellerman 20758a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 20858a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 20958a032c3SMichael Ellerman else { 210e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 211e6878835Ssukadev@linux.vnet.ibm.com 212e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 213e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 214e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 215e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 216f04d1080SMadhavan Srinivasan else if (ppmu->flags & PPMU_NO_SIAR) 217f04d1080SMadhavan Srinivasan sdsync = MMCRA_SAMPLE_ENABLE; 218e6878835Ssukadev@linux.vnet.ibm.com else 219e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 220f2699491SMichael Ellerman 22158a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 22258a032c3SMichael Ellerman } 22358a032c3SMichael Ellerman 22458a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 225f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 226cd1231d7SMadhavan Srinivasan 2275ae5fbd2SAthira Rajeev if (is_kernel_addr(mfspr(SPRN_SDAR)) && event->attr.exclude_kernel) 228cd1231d7SMadhavan Srinivasan *addrp = 0; 229f2699491SMichael Ellerman } 230f2699491SMichael Ellerman 2315682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 23268b30bb9SAnton Blanchard { 23368b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 23468b30bb9SAnton Blanchard 2358f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2368f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 2378f61aa32SMichael Ellerman 23868b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 23968b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 24068b30bb9SAnton Blanchard 2415682c460SMichael Ellerman return !!(regs->dsisr & sihv); 24268b30bb9SAnton Blanchard } 24368b30bb9SAnton Blanchard 2445682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 24568b30bb9SAnton Blanchard { 24668b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 24768b30bb9SAnton Blanchard 2488f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2498f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 2508f61aa32SMichael Ellerman 25168b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 25268b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 25368b30bb9SAnton Blanchard 2545682c460SMichael Ellerman return !!(regs->dsisr & sipr); 25568b30bb9SAnton Blanchard } 25668b30bb9SAnton Blanchard 2571ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 2581ce447b9SBenjamin Herrenschmidt { 2591ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 2601ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2611ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 2621ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2631ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2641ce447b9SBenjamin Herrenschmidt } 2651ce447b9SBenjamin Herrenschmidt 266f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 267f2699491SMichael Ellerman { 26833904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 269d9f7088dSAthira Rajeev unsigned long mmcra = regs->dsisr; 270d9f7088dSAthira Rajeev int marked = mmcra & MMCRA_SAMPLE_ENABLE; 271f2699491SMichael Ellerman 27275382aa7SAnton Blanchard if (!use_siar) 2731ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2741ce447b9SBenjamin Herrenschmidt 2751ce447b9SBenjamin Herrenschmidt /* 276d9f7088dSAthira Rajeev * Check the address in SIAR to identify the 277d9f7088dSAthira Rajeev * privilege levels since the SIER[MSR_HV, MSR_PR] 278d9f7088dSAthira Rajeev * bits are not set for marked events in power10 279d9f7088dSAthira Rajeev * DD1. 280d9f7088dSAthira Rajeev */ 281d9f7088dSAthira Rajeev if (marked && (ppmu->flags & PPMU_P10_DD1)) { 2822ca13a4cSMadhavan Srinivasan unsigned long siar = mfspr(SPRN_SIAR); 2832ca13a4cSMadhavan Srinivasan if (siar) { 2842ca13a4cSMadhavan Srinivasan if (is_kernel_addr(siar)) 285d9f7088dSAthira Rajeev return PERF_RECORD_MISC_KERNEL; 286d9f7088dSAthira Rajeev return PERF_RECORD_MISC_USER; 2872ca13a4cSMadhavan Srinivasan } else { 2882ca13a4cSMadhavan Srinivasan if (is_kernel_addr(regs->nip)) 2892ca13a4cSMadhavan Srinivasan return PERF_RECORD_MISC_KERNEL; 2902ca13a4cSMadhavan Srinivasan return PERF_RECORD_MISC_USER; 2912ca13a4cSMadhavan Srinivasan } 292d9f7088dSAthira Rajeev } 293d9f7088dSAthira Rajeev 294d9f7088dSAthira Rajeev /* 2951ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2961ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2971ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2981ce447b9SBenjamin Herrenschmidt * results 2991ce447b9SBenjamin Herrenschmidt */ 300cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 3011ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 302a2391b35SMadhavan Srinivasan if (is_kernel_addr(siar)) 3031ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 3041ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 3051ce447b9SBenjamin Herrenschmidt } 306f2699491SMichael Ellerman 307f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 3085682c460SMichael Ellerman if (regs_sipr(regs)) 309f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 3105682c460SMichael Ellerman 3115682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 312f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 3135682c460SMichael Ellerman 314f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 315f2699491SMichael Ellerman } 316f2699491SMichael Ellerman 317f2699491SMichael Ellerman /* 318f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 319f2699491SMichael Ellerman * on each interrupt. 3208f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 32175382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 32275382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 323f2699491SMichael Ellerman */ 324f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 325f2699491SMichael Ellerman { 32675382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 32775382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 32875382aa7SAnton Blanchard int use_siar; 32975382aa7SAnton Blanchard 3305682c460SMichael Ellerman regs->dsisr = mmcra; 331860aad71SMichael Ellerman 332cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 3338f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 3348f61aa32SMichael Ellerman 3358f61aa32SMichael Ellerman /* 3365c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 3375c093efaSAnton Blanchard * not valid. Use pt_regs. 3385c093efaSAnton Blanchard * 3395c093efaSAnton Blanchard * If it is a marked event use the SIAR. 3405c093efaSAnton Blanchard * 3415c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 3425c093efaSAnton Blanchard * pt_regs. 3435c093efaSAnton Blanchard * 344cf9c615cSNicholas Piggin * If regs is a kernel interrupt, always use SIAR. Some PMUs have an 345cf9c615cSNicholas Piggin * issue with regs_sipr not being in synch with SIAR in interrupt entry 346cf9c615cSNicholas Piggin * and return sequences, which can result in regs_sipr being true for 347cf9c615cSNicholas Piggin * kernel interrupts and SIAR, which has the effect of causing samples 348cf9c615cSNicholas Piggin * to pile up at mtmsrd MSR[EE] 0->1 or pending irq replay around 349cf9c615cSNicholas Piggin * interrupt entry/exit. 350cf9c615cSNicholas Piggin * 3515c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 3525c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 3535c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 3545c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 3555c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 3565c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 3575c093efaSAnton Blanchard * interrupts off hence the userspace check. 3585c093efaSAnton Blanchard */ 3597153d4bfSXiongwei Song if (TRAP(regs) != INTERRUPT_PERFMON) 36075382aa7SAnton Blanchard use_siar = 0; 36127593d72SMadhavan Srinivasan else if ((ppmu->flags & PPMU_NO_SIAR)) 36227593d72SMadhavan Srinivasan use_siar = 0; 3635c093efaSAnton Blanchard else if (marked) 3645c093efaSAnton Blanchard use_siar = 1; 3655c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 3665c093efaSAnton Blanchard use_siar = 0; 367cf9c615cSNicholas Piggin else if (!user_mode(regs)) 368cf9c615cSNicholas Piggin use_siar = 1; 369cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 37075382aa7SAnton Blanchard use_siar = 0; 37175382aa7SAnton Blanchard else 37275382aa7SAnton Blanchard use_siar = 1; 37375382aa7SAnton Blanchard 374cbda6aa1SMichael Ellerman regs->result = use_siar; 375f2699491SMichael Ellerman } 376f2699491SMichael Ellerman 377f2699491SMichael Ellerman /* 378e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 379e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 380e6878835Ssukadev@linux.vnet.ibm.com * 381e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 382e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 383e6878835Ssukadev@linux.vnet.ibm.com */ 384e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 385e6878835Ssukadev@linux.vnet.ibm.com { 386e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 387e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 388e6878835Ssukadev@linux.vnet.ibm.com 38958a032c3SMichael Ellerman if (marked) { 390fdf13a65SAthira Rajeev /* 391fdf13a65SAthira Rajeev * SIER[SIAR_VALID] is not set for some 392fdf13a65SAthira Rajeev * marked events on power10 DD1, so drop 393fdf13a65SAthira Rajeev * the check for SIER[SIAR_VALID] and return true. 394fdf13a65SAthira Rajeev */ 395fdf13a65SAthira Rajeev if (ppmu->flags & PPMU_P10_DD1) 396fdf13a65SAthira Rajeev return 0x1; 397fdf13a65SAthira Rajeev else if (ppmu->flags & PPMU_HAS_SIER) 39858a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 39958a032c3SMichael Ellerman 40058a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 401e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 40258a032c3SMichael Ellerman } 403e6878835Ssukadev@linux.vnet.ibm.com 404e6878835Ssukadev@linux.vnet.ibm.com return 1; 405e6878835Ssukadev@linux.vnet.ibm.com } 406e6878835Ssukadev@linux.vnet.ibm.com 407d52f2dc4SMichael Neuling 408d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 409d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 410d52f2dc4SMichael Neuling { 411d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 412d52f2dc4SMichael Neuling } 413d52f2dc4SMichael Neuling 414d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 415d52f2dc4SMichael Neuling { 41669111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 417d52f2dc4SMichael Neuling 418d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 419d52f2dc4SMichael Neuling return; 420d52f2dc4SMichael Neuling 421d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 422d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 423d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 424d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 425d52f2dc4SMichael Neuling } 426d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 427acba3c7eSPeter Zijlstra perf_sched_cb_inc(event->ctx->pmu); 428d52f2dc4SMichael Neuling } 429d52f2dc4SMichael Neuling 430d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 431d52f2dc4SMichael Neuling { 43269111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 433d52f2dc4SMichael Neuling 434d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 435d52f2dc4SMichael Neuling return; 436d52f2dc4SMichael Neuling 437f0322f7fSAnshuman Khandual WARN_ON_ONCE(!cpuhw->bhrb_users); 438d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 439acba3c7eSPeter Zijlstra perf_sched_cb_dec(event->ctx->pmu); 440d52f2dc4SMichael Neuling 441d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 442d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 443d52f2dc4SMichael Neuling * events are active on the PMU. 444d52f2dc4SMichael Neuling */ 445d52f2dc4SMichael Neuling 446d52f2dc4SMichael Neuling /* avoid stale pointer */ 447d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 448d52f2dc4SMichael Neuling } 449d52f2dc4SMichael Neuling } 450d52f2dc4SMichael Neuling 451d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 452d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 453d52f2dc4SMichael Neuling */ 454acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 455d52f2dc4SMichael Neuling { 456acba3c7eSPeter Zijlstra if (!ppmu->bhrb_nr) 457acba3c7eSPeter Zijlstra return; 458acba3c7eSPeter Zijlstra 459acba3c7eSPeter Zijlstra if (sched_in) 460d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 461d52f2dc4SMichael Neuling } 46269123184SMichael Neuling /* Calculate the to address for a branch */ 46369123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 46469123184SMichael Neuling { 46569123184SMichael Neuling unsigned int instr; 46669123184SMichael Neuling __u64 target; 46769123184SMichael Neuling 468f41d84ddSRavi Bangoria if (is_kernel_addr(addr)) { 469fe557319SChristoph Hellwig if (copy_from_kernel_nofault(&instr, (void *)addr, 470fe557319SChristoph Hellwig sizeof(instr))) 471f41d84ddSRavi Bangoria return 0; 472f41d84ddSRavi Bangoria 47369d4d6e5SChristophe Leroy return branch_target(&instr); 474f41d84ddSRavi Bangoria } 47569123184SMichael Neuling 47669123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 477c0ee37e8SChristoph Hellwig if (copy_from_user_nofault(&instr, (unsigned int __user *)addr, 478c0ee37e8SChristoph Hellwig sizeof(instr))) 47969123184SMichael Neuling return 0; 48069123184SMichael Neuling 48169d4d6e5SChristophe Leroy target = branch_target(&instr); 48269123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 48369123184SMichael Neuling return target; 48469123184SMichael Neuling 48569123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 48669123184SMichael Neuling return target - (unsigned long)&instr + addr; 48769123184SMichael Neuling } 488d52f2dc4SMichael Neuling 489d52f2dc4SMichael Neuling /* Processing BHRB entries */ 490da97e184SJoel Fernandes (Google) static void power_pmu_bhrb_read(struct perf_event *event, struct cpu_hw_events *cpuhw) 491d52f2dc4SMichael Neuling { 492d52f2dc4SMichael Neuling u64 val; 493d52f2dc4SMichael Neuling u64 addr; 494506e70d1SMichael Neuling int r_index, u_index, pred; 495d52f2dc4SMichael Neuling 496d52f2dc4SMichael Neuling r_index = 0; 497d52f2dc4SMichael Neuling u_index = 0; 498d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 499d52f2dc4SMichael Neuling /* Assembly read function */ 500506e70d1SMichael Neuling val = read_bhrb(r_index++); 501506e70d1SMichael Neuling if (!val) 502d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 503d52f2dc4SMichael Neuling break; 504506e70d1SMichael Neuling else { 505d52f2dc4SMichael Neuling addr = val & BHRB_EA; 506d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 507d52f2dc4SMichael Neuling 508506e70d1SMichael Neuling if (!addr) 509506e70d1SMichael Neuling /* invalid entry */ 510d52f2dc4SMichael Neuling continue; 511d52f2dc4SMichael Neuling 512bb19af81SMadhavan Srinivasan /* 513bb19af81SMadhavan Srinivasan * BHRB rolling buffer could very much contain the kernel 514bb19af81SMadhavan Srinivasan * addresses at this point. Check the privileges before 515bb19af81SMadhavan Srinivasan * exporting it to userspace (avoid exposure of regions 516bb19af81SMadhavan Srinivasan * where we could have speculative execution) 517bfe3b194SAthira Rajeev * Incase of ISA v3.1, BHRB will capture only user-space 518bfe3b194SAthira Rajeev * addresses, hence include a check before filtering code 519bb19af81SMadhavan Srinivasan */ 520bfe3b194SAthira Rajeev if (!(ppmu->flags & PPMU_ARCH_31) && 5215ae5fbd2SAthira Rajeev is_kernel_addr(addr) && event->attr.exclude_kernel) 522bb19af81SMadhavan Srinivasan continue; 523bb19af81SMadhavan Srinivasan 524506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 525506e70d1SMichael Neuling * the most recent branch). 526506e70d1SMichael Neuling * There are two types of valid entries: 527506e70d1SMichael Neuling * 1) a target entry which is the to address of a 528506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 529506e70d1SMichael Neuling * entry read from the bhrb will be branch 530506e70d1SMichael Neuling * corresponding to this target (ie. the actual 531506e70d1SMichael Neuling * blr/bctr/btar instruction). 532506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 533506e70d1SMichael Neuling * target entry proceeds this, then this is the 534506e70d1SMichael Neuling * matching branch for that target. If this is not 535506e70d1SMichael Neuling * following a target entry, then this is a branch 536506e70d1SMichael Neuling * where the target is given as an immediate field 537506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 538506e70d1SMichael Neuling * In this case we need to read the instruction from 539506e70d1SMichael Neuling * memory to determine the target/to address. 540506e70d1SMichael Neuling */ 541d52f2dc4SMichael Neuling 542d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 543506e70d1SMichael Neuling /* Target branches use two entries 544506e70d1SMichael Neuling * (ie. computed gotos/XL form) 545506e70d1SMichael Neuling */ 546506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 547d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 548d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 549d52f2dc4SMichael Neuling 550506e70d1SMichael Neuling /* Get from address in next entry */ 551506e70d1SMichael Neuling val = read_bhrb(r_index++); 552506e70d1SMichael Neuling addr = val & BHRB_EA; 553506e70d1SMichael Neuling if (val & BHRB_TARGET) { 554506e70d1SMichael Neuling /* Shouldn't have two targets in a 555506e70d1SMichael Neuling row.. Reset index and try again */ 556506e70d1SMichael Neuling r_index--; 557506e70d1SMichael Neuling addr = 0; 558d52f2dc4SMichael Neuling } 559506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 560506e70d1SMichael Neuling } else { 561506e70d1SMichael Neuling /* Branches to immediate field 562506e70d1SMichael Neuling (ie I or B form) */ 563506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 56469123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 56569123184SMichael Neuling power_pmu_bhrb_to(addr); 566506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 567506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 568506e70d1SMichael Neuling } 569506e70d1SMichael Neuling u_index++; 570506e70d1SMichael Neuling 571d52f2dc4SMichael Neuling } 572d52f2dc4SMichael Neuling } 573d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 574bbfd5e4fSKan Liang cpuhw->bhrb_stack.hw_idx = -1ULL; 575d52f2dc4SMichael Neuling return; 576d52f2dc4SMichael Neuling } 577d52f2dc4SMichael Neuling 578330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) 579330a1eb7SMichael Ellerman { 580330a1eb7SMichael Ellerman /* 581330a1eb7SMichael Ellerman * This could be a per-PMU callback, but we'd rather avoid the cost. We 582330a1eb7SMichael Ellerman * check that the PMU supports EBB, meaning those that don't can still 583330a1eb7SMichael Ellerman * use bit 63 of the event code for something else if they wish. 584330a1eb7SMichael Ellerman */ 5854d9690ddSJoel Stanley return (ppmu->flags & PPMU_ARCH_207S) && 5868d7c55d0SMichael Ellerman ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 587330a1eb7SMichael Ellerman } 588330a1eb7SMichael Ellerman 589330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) 590330a1eb7SMichael Ellerman { 591330a1eb7SMichael Ellerman struct perf_event *leader = event->group_leader; 592330a1eb7SMichael Ellerman 593330a1eb7SMichael Ellerman /* Event and group leader must agree on EBB */ 594330a1eb7SMichael Ellerman if (is_ebb_event(leader) != is_ebb_event(event)) 595330a1eb7SMichael Ellerman return -EINVAL; 596330a1eb7SMichael Ellerman 597330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 598330a1eb7SMichael Ellerman if (!(event->attach_state & PERF_ATTACH_TASK)) 599330a1eb7SMichael Ellerman return -EINVAL; 600330a1eb7SMichael Ellerman 601330a1eb7SMichael Ellerman if (!leader->attr.pinned || !leader->attr.exclusive) 602330a1eb7SMichael Ellerman return -EINVAL; 603330a1eb7SMichael Ellerman 60458b5fb00SMichael Ellerman if (event->attr.freq || 60558b5fb00SMichael Ellerman event->attr.inherit || 60658b5fb00SMichael Ellerman event->attr.sample_type || 60758b5fb00SMichael Ellerman event->attr.sample_period || 60858b5fb00SMichael Ellerman event->attr.enable_on_exec) 609330a1eb7SMichael Ellerman return -EINVAL; 610330a1eb7SMichael Ellerman } 611330a1eb7SMichael Ellerman 612330a1eb7SMichael Ellerman return 0; 613330a1eb7SMichael Ellerman } 614330a1eb7SMichael Ellerman 615330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) 616330a1eb7SMichael Ellerman { 617330a1eb7SMichael Ellerman if (!is_ebb_event(event) || current->thread.used_ebb) 618330a1eb7SMichael Ellerman return; 619330a1eb7SMichael Ellerman 620330a1eb7SMichael Ellerman /* 621330a1eb7SMichael Ellerman * IFF this is the first time we've added an EBB event, set 622330a1eb7SMichael Ellerman * PMXE in the user MMCR0 so we can detect when it's cleared by 623330a1eb7SMichael Ellerman * userspace. We need this so that we can context switch while 624330a1eb7SMichael Ellerman * userspace is in the EBB handler (where PMXE is 0). 625330a1eb7SMichael Ellerman */ 626330a1eb7SMichael Ellerman current->thread.used_ebb = 1; 627330a1eb7SMichael Ellerman current->thread.mmcr0 |= MMCR0_PMXE; 628330a1eb7SMichael Ellerman } 629330a1eb7SMichael Ellerman 630330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) 631330a1eb7SMichael Ellerman { 632330a1eb7SMichael Ellerman if (!(mmcr0 & MMCR0_EBE)) 633330a1eb7SMichael Ellerman return; 634330a1eb7SMichael Ellerman 635330a1eb7SMichael Ellerman current->thread.siar = mfspr(SPRN_SIAR); 636330a1eb7SMichael Ellerman current->thread.sier = mfspr(SPRN_SIER); 637330a1eb7SMichael Ellerman current->thread.sdar = mfspr(SPRN_SDAR); 638330a1eb7SMichael Ellerman current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 639330a1eb7SMichael Ellerman current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 640c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 641c718547eSMadhavan Srinivasan current->thread.mmcr3 = mfspr(SPRN_MMCR3); 642c718547eSMadhavan Srinivasan current->thread.sier2 = mfspr(SPRN_SIER2); 643c718547eSMadhavan Srinivasan current->thread.sier3 = mfspr(SPRN_SIER3); 644c718547eSMadhavan Srinivasan } 645330a1eb7SMichael Ellerman } 646330a1eb7SMichael Ellerman 6479de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 648330a1eb7SMichael Ellerman { 64978d76819SAthira Rajeev unsigned long mmcr0 = cpuhw->mmcr.mmcr0; 6509de5cb0fSMichael Ellerman 651330a1eb7SMichael Ellerman if (!ebb) 652330a1eb7SMichael Ellerman goto out; 653330a1eb7SMichael Ellerman 65476cb8a78SMichael Ellerman /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 65576cb8a78SMichael Ellerman mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 656330a1eb7SMichael Ellerman 657c2e37a26SMichael Ellerman /* 658c2e37a26SMichael Ellerman * Add any bits from the user MMCR0, FC or PMAO. This is compatible 659c2e37a26SMichael Ellerman * with pmao_restore_workaround() because we may add PMAO but we never 660c2e37a26SMichael Ellerman * clear it here. 661c2e37a26SMichael Ellerman */ 662330a1eb7SMichael Ellerman mmcr0 |= current->thread.mmcr0; 663330a1eb7SMichael Ellerman 664c2e37a26SMichael Ellerman /* 665c2e37a26SMichael Ellerman * Be careful not to set PMXE if userspace had it cleared. This is also 666c2e37a26SMichael Ellerman * compatible with pmao_restore_workaround() because it has already 667c2e37a26SMichael Ellerman * cleared PMXE and we leave PMAO alone. 668c2e37a26SMichael Ellerman */ 669330a1eb7SMichael Ellerman if (!(current->thread.mmcr0 & MMCR0_PMXE)) 670330a1eb7SMichael Ellerman mmcr0 &= ~MMCR0_PMXE; 671330a1eb7SMichael Ellerman 672330a1eb7SMichael Ellerman mtspr(SPRN_SIAR, current->thread.siar); 673330a1eb7SMichael Ellerman mtspr(SPRN_SIER, current->thread.sier); 674330a1eb7SMichael Ellerman mtspr(SPRN_SDAR, current->thread.sdar); 6759de5cb0fSMichael Ellerman 6769de5cb0fSMichael Ellerman /* 6779de5cb0fSMichael Ellerman * Merge the kernel & user values of MMCR2. The semantics we implement 6789de5cb0fSMichael Ellerman * are that the user MMCR2 can set bits, ie. cause counters to freeze, 6799de5cb0fSMichael Ellerman * but not clear bits. If a task wants to be able to clear bits, ie. 6809de5cb0fSMichael Ellerman * unfreeze counters, it should not set exclude_xxx in its events and 6819de5cb0fSMichael Ellerman * instead manage the MMCR2 entirely by itself. 6829de5cb0fSMichael Ellerman */ 68378d76819SAthira Rajeev mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2 | current->thread.mmcr2); 684c718547eSMadhavan Srinivasan 685c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 686c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, current->thread.mmcr3); 687c718547eSMadhavan Srinivasan mtspr(SPRN_SIER2, current->thread.sier2); 688c718547eSMadhavan Srinivasan mtspr(SPRN_SIER3, current->thread.sier3); 689c718547eSMadhavan Srinivasan } 690330a1eb7SMichael Ellerman out: 691330a1eb7SMichael Ellerman return mmcr0; 692330a1eb7SMichael Ellerman } 693c2e37a26SMichael Ellerman 694c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) 695c2e37a26SMichael Ellerman { 696c2e37a26SMichael Ellerman unsigned pmcs[6]; 697c2e37a26SMichael Ellerman 698c2e37a26SMichael Ellerman if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 699c2e37a26SMichael Ellerman return; 700c2e37a26SMichael Ellerman 701c2e37a26SMichael Ellerman /* 702c2e37a26SMichael Ellerman * On POWER8E there is a hardware defect which affects the PMU context 703c2e37a26SMichael Ellerman * switch logic, ie. power_pmu_disable/enable(). 704c2e37a26SMichael Ellerman * 705c2e37a26SMichael Ellerman * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 706c2e37a26SMichael Ellerman * by the hardware. Sometime later the actual PMU exception is 707c2e37a26SMichael Ellerman * delivered. 708c2e37a26SMichael Ellerman * 709c2e37a26SMichael Ellerman * If we context switch, or simply disable/enable, the PMU prior to the 710c2e37a26SMichael Ellerman * exception arriving, the exception will be lost when we clear PMAO. 711c2e37a26SMichael Ellerman * 712c2e37a26SMichael Ellerman * When we reenable the PMU, we will write the saved MMCR0 with PMAO 713c2e37a26SMichael Ellerman * set, and this _should_ generate an exception. However because of the 714c2e37a26SMichael Ellerman * defect no exception is generated when we write PMAO, and we get 715c2e37a26SMichael Ellerman * stuck with no counters counting but no exception delivered. 716c2e37a26SMichael Ellerman * 717c2e37a26SMichael Ellerman * The workaround is to detect this case and tweak the hardware to 718c2e37a26SMichael Ellerman * create another pending PMU exception. 719c2e37a26SMichael Ellerman * 720c2e37a26SMichael Ellerman * We do that by setting up PMC6 (cycles) for an imminent overflow and 721c2e37a26SMichael Ellerman * enabling the PMU. That causes a new exception to be generated in the 722c2e37a26SMichael Ellerman * chip, but we don't take it yet because we have interrupts hard 723c2e37a26SMichael Ellerman * disabled. We then write back the PMU state as we want it to be seen 724c2e37a26SMichael Ellerman * by the exception handler. When we reenable interrupts the exception 725c2e37a26SMichael Ellerman * handler will be called and see the correct state. 726c2e37a26SMichael Ellerman * 727c2e37a26SMichael Ellerman * The logic is the same for EBB, except that the exception is gated by 728c2e37a26SMichael Ellerman * us having interrupts hard disabled as well as the fact that we are 729c2e37a26SMichael Ellerman * not in userspace. The exception is finally delivered when we return 730c2e37a26SMichael Ellerman * to userspace. 731c2e37a26SMichael Ellerman */ 732c2e37a26SMichael Ellerman 733c2e37a26SMichael Ellerman /* Only if PMAO is set and PMAO_SYNC is clear */ 734c2e37a26SMichael Ellerman if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 735c2e37a26SMichael Ellerman return; 736c2e37a26SMichael Ellerman 737c2e37a26SMichael Ellerman /* If we're doing EBB, only if BESCR[GE] is set */ 738c2e37a26SMichael Ellerman if (ebb && !(current->thread.bescr & BESCR_GE)) 739c2e37a26SMichael Ellerman return; 740c2e37a26SMichael Ellerman 741c2e37a26SMichael Ellerman /* 742c2e37a26SMichael Ellerman * We are already soft-disabled in power_pmu_enable(). We need to hard 74358bffb5bSMadhavan Srinivasan * disable to actually prevent the PMU exception from firing. 744c2e37a26SMichael Ellerman */ 745c2e37a26SMichael Ellerman hard_irq_disable(); 746c2e37a26SMichael Ellerman 747c2e37a26SMichael Ellerman /* 748c2e37a26SMichael Ellerman * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 749c2e37a26SMichael Ellerman * Using read/write_pmc() in a for loop adds 12 function calls and 750c2e37a26SMichael Ellerman * almost doubles our code size. 751c2e37a26SMichael Ellerman */ 752c2e37a26SMichael Ellerman pmcs[0] = mfspr(SPRN_PMC1); 753c2e37a26SMichael Ellerman pmcs[1] = mfspr(SPRN_PMC2); 754c2e37a26SMichael Ellerman pmcs[2] = mfspr(SPRN_PMC3); 755c2e37a26SMichael Ellerman pmcs[3] = mfspr(SPRN_PMC4); 756c2e37a26SMichael Ellerman pmcs[4] = mfspr(SPRN_PMC5); 757c2e37a26SMichael Ellerman pmcs[5] = mfspr(SPRN_PMC6); 758c2e37a26SMichael Ellerman 759c2e37a26SMichael Ellerman /* Ensure all freeze bits are unset */ 760c2e37a26SMichael Ellerman mtspr(SPRN_MMCR2, 0); 761c2e37a26SMichael Ellerman 762c2e37a26SMichael Ellerman /* Set up PMC6 to overflow in one cycle */ 763c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, 0x7FFFFFFE); 764c2e37a26SMichael Ellerman 765c2e37a26SMichael Ellerman /* Enable exceptions and unfreeze PMC6 */ 766c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 767c2e37a26SMichael Ellerman 768c2e37a26SMichael Ellerman /* Now we need to refreeze and restore the PMCs */ 769c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 770c2e37a26SMichael Ellerman 771c2e37a26SMichael Ellerman mtspr(SPRN_PMC1, pmcs[0]); 772c2e37a26SMichael Ellerman mtspr(SPRN_PMC2, pmcs[1]); 773c2e37a26SMichael Ellerman mtspr(SPRN_PMC3, pmcs[2]); 774c2e37a26SMichael Ellerman mtspr(SPRN_PMC4, pmcs[3]); 775c2e37a26SMichael Ellerman mtspr(SPRN_PMC5, pmcs[4]); 776c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, pmcs[5]); 777c2e37a26SMichael Ellerman } 778356d8ce3SMadhavan Srinivasan 779*429a64f6SAthira Rajeev /* 780*429a64f6SAthira Rajeev * If the perf subsystem wants performance monitor interrupts as soon as 781*429a64f6SAthira Rajeev * possible (e.g., to sample the instruction address and stack chain), 782*429a64f6SAthira Rajeev * this should return true. The IRQ masking code can then enable MSR[EE] 783*429a64f6SAthira Rajeev * in some places (e.g., interrupt handlers) that allows PMI interrupts 784*429a64f6SAthira Rajeev * through to improve accuracy of profiles, at the cost of some performance. 785*429a64f6SAthira Rajeev * 786*429a64f6SAthira Rajeev * The PMU counters can be enabled by other means (e.g., sysfs raw SPR 787*429a64f6SAthira Rajeev * access), but in that case there is no need for prompt PMI handling. 788*429a64f6SAthira Rajeev * 789*429a64f6SAthira Rajeev * This currently returns true if any perf counter is being used. It 790*429a64f6SAthira Rajeev * could possibly return false if only events are being counted rather than 791*429a64f6SAthira Rajeev * samples being taken, but for now this is good enough. 792*429a64f6SAthira Rajeev */ 793*429a64f6SAthira Rajeev bool power_pmu_wants_prompt_pmi(void) 794*429a64f6SAthira Rajeev { 795*429a64f6SAthira Rajeev struct cpu_hw_events *cpuhw; 796*429a64f6SAthira Rajeev 797*429a64f6SAthira Rajeev /* 798*429a64f6SAthira Rajeev * This could simply test local_paca->pmcregs_in_use if that were not 799*429a64f6SAthira Rajeev * under ifdef KVM. 800*429a64f6SAthira Rajeev */ 801*429a64f6SAthira Rajeev if (!ppmu) 802*429a64f6SAthira Rajeev return false; 803*429a64f6SAthira Rajeev 804*429a64f6SAthira Rajeev cpuhw = this_cpu_ptr(&cpu_hw_events); 805*429a64f6SAthira Rajeev return cpuhw->n_events; 806*429a64f6SAthira Rajeev } 807f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 808f2699491SMichael Ellerman 809f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 810f2699491SMichael Ellerman 811f2699491SMichael Ellerman /* 812f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 813f2699491SMichael Ellerman */ 814f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 815f2699491SMichael Ellerman { 816f2699491SMichael Ellerman unsigned long val; 817f2699491SMichael Ellerman 818f2699491SMichael Ellerman switch (idx) { 819f2699491SMichael Ellerman case 1: 820f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 821f2699491SMichael Ellerman break; 822f2699491SMichael Ellerman case 2: 823f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 824f2699491SMichael Ellerman break; 825f2699491SMichael Ellerman case 3: 826f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 827f2699491SMichael Ellerman break; 828f2699491SMichael Ellerman case 4: 829f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 830f2699491SMichael Ellerman break; 831f2699491SMichael Ellerman case 5: 832f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 833f2699491SMichael Ellerman break; 834f2699491SMichael Ellerman case 6: 835f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 836f2699491SMichael Ellerman break; 837f2699491SMichael Ellerman #ifdef CONFIG_PPC64 838f2699491SMichael Ellerman case 7: 839f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 840f2699491SMichael Ellerman break; 841f2699491SMichael Ellerman case 8: 842f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 843f2699491SMichael Ellerman break; 844f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 845f2699491SMichael Ellerman default: 846f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 847f2699491SMichael Ellerman val = 0; 848f2699491SMichael Ellerman } 849f2699491SMichael Ellerman return val; 850f2699491SMichael Ellerman } 851f2699491SMichael Ellerman 852f2699491SMichael Ellerman /* 853f2699491SMichael Ellerman * Write one PMC. 854f2699491SMichael Ellerman */ 855f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 856f2699491SMichael Ellerman { 857f2699491SMichael Ellerman switch (idx) { 858f2699491SMichael Ellerman case 1: 859f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 860f2699491SMichael Ellerman break; 861f2699491SMichael Ellerman case 2: 862f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 863f2699491SMichael Ellerman break; 864f2699491SMichael Ellerman case 3: 865f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 866f2699491SMichael Ellerman break; 867f2699491SMichael Ellerman case 4: 868f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 869f2699491SMichael Ellerman break; 870f2699491SMichael Ellerman case 5: 871f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 872f2699491SMichael Ellerman break; 873f2699491SMichael Ellerman case 6: 874f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 875f2699491SMichael Ellerman break; 876f2699491SMichael Ellerman #ifdef CONFIG_PPC64 877f2699491SMichael Ellerman case 7: 878f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 879f2699491SMichael Ellerman break; 880f2699491SMichael Ellerman case 8: 881f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 882f2699491SMichael Ellerman break; 883f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 884f2699491SMichael Ellerman default: 885f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 886f2699491SMichael Ellerman } 887f2699491SMichael Ellerman } 888f2699491SMichael Ellerman 8892c9ac51bSAthira Rajeev static int any_pmc_overflown(struct cpu_hw_events *cpuhw) 8902c9ac51bSAthira Rajeev { 8912c9ac51bSAthira Rajeev int i, idx; 8922c9ac51bSAthira Rajeev 8932c9ac51bSAthira Rajeev for (i = 0; i < cpuhw->n_events; i++) { 8942c9ac51bSAthira Rajeev idx = cpuhw->event[i]->hw.idx; 8952c9ac51bSAthira Rajeev if ((idx) && ((int)read_pmc(idx) < 0)) 8962c9ac51bSAthira Rajeev return idx; 8972c9ac51bSAthira Rajeev } 8982c9ac51bSAthira Rajeev 8992c9ac51bSAthira Rajeev return 0; 9002c9ac51bSAthira Rajeev } 9012c9ac51bSAthira Rajeev 9025f6d0380SAnshuman Khandual /* Called from sysrq_handle_showregs() */ 9035f6d0380SAnshuman Khandual void perf_event_print_debug(void) 9045f6d0380SAnshuman Khandual { 9055f6d0380SAnshuman Khandual unsigned long sdar, sier, flags; 9065f6d0380SAnshuman Khandual u32 pmcs[MAX_HWEVENTS]; 9075f6d0380SAnshuman Khandual int i; 9085f6d0380SAnshuman Khandual 9094917fcb5SRavi Bangoria if (!ppmu) { 9104917fcb5SRavi Bangoria pr_info("Performance monitor hardware not registered.\n"); 9114917fcb5SRavi Bangoria return; 9124917fcb5SRavi Bangoria } 9134917fcb5SRavi Bangoria 9145f6d0380SAnshuman Khandual if (!ppmu->n_counter) 9155f6d0380SAnshuman Khandual return; 9165f6d0380SAnshuman Khandual 9175f6d0380SAnshuman Khandual local_irq_save(flags); 9185f6d0380SAnshuman Khandual 9195f6d0380SAnshuman Khandual pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 9205f6d0380SAnshuman Khandual smp_processor_id(), ppmu->name, ppmu->n_counter); 9215f6d0380SAnshuman Khandual 9225f6d0380SAnshuman Khandual for (i = 0; i < ppmu->n_counter; i++) 9235f6d0380SAnshuman Khandual pmcs[i] = read_pmc(i + 1); 9245f6d0380SAnshuman Khandual 9255f6d0380SAnshuman Khandual for (; i < MAX_HWEVENTS; i++) 9265f6d0380SAnshuman Khandual pmcs[i] = 0xdeadbeef; 9275f6d0380SAnshuman Khandual 9285f6d0380SAnshuman Khandual pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 9295f6d0380SAnshuman Khandual pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 9305f6d0380SAnshuman Khandual 9315f6d0380SAnshuman Khandual if (ppmu->n_counter > 4) 9325f6d0380SAnshuman Khandual pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 9335f6d0380SAnshuman Khandual pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 9345f6d0380SAnshuman Khandual 9355f6d0380SAnshuman Khandual pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 9365f6d0380SAnshuman Khandual mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 9375f6d0380SAnshuman Khandual 9385f6d0380SAnshuman Khandual sdar = sier = 0; 9395f6d0380SAnshuman Khandual #ifdef CONFIG_PPC64 9405f6d0380SAnshuman Khandual sdar = mfspr(SPRN_SDAR); 9415f6d0380SAnshuman Khandual 9425f6d0380SAnshuman Khandual if (ppmu->flags & PPMU_HAS_SIER) 9435f6d0380SAnshuman Khandual sier = mfspr(SPRN_SIER); 9445f6d0380SAnshuman Khandual 9454d9690ddSJoel Stanley if (ppmu->flags & PPMU_ARCH_207S) { 9465f6d0380SAnshuman Khandual pr_info("MMCR2: %016lx EBBHR: %016lx\n", 9475f6d0380SAnshuman Khandual mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 9485f6d0380SAnshuman Khandual pr_info("EBBRR: %016lx BESCR: %016lx\n", 9495f6d0380SAnshuman Khandual mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 9505f6d0380SAnshuman Khandual } 951c718547eSMadhavan Srinivasan 952c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) { 953c718547eSMadhavan Srinivasan pr_info("MMCR3: %016lx SIER2: %016lx SIER3: %016lx\n", 954c718547eSMadhavan Srinivasan mfspr(SPRN_MMCR3), mfspr(SPRN_SIER2), mfspr(SPRN_SIER3)); 955c718547eSMadhavan Srinivasan } 9565f6d0380SAnshuman Khandual #endif 9575f6d0380SAnshuman Khandual pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 9585f6d0380SAnshuman Khandual mfspr(SPRN_SIAR), sdar, sier); 9595f6d0380SAnshuman Khandual 9605f6d0380SAnshuman Khandual local_irq_restore(flags); 9615f6d0380SAnshuman Khandual } 9625f6d0380SAnshuman Khandual 963f2699491SMichael Ellerman /* 964f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 965f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 966f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 967f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 968f2699491SMichael Ellerman */ 969f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 970f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 97182d2c16bSKajol Jain int n_ev, struct perf_event **event) 972f2699491SMichael Ellerman { 973f2699491SMichael Ellerman unsigned long mask, value, nv; 974f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 975f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 976f2699491SMichael Ellerman int i, j; 977f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 978f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 97959029136SMadhavan Srinivasan unsigned long grp_mask = ppmu->group_constraint_mask; 98059029136SMadhavan Srinivasan unsigned long grp_val = ppmu->group_constraint_val; 981f2699491SMichael Ellerman 982f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 983f2699491SMichael Ellerman return -1; 984f2699491SMichael Ellerman 985f2699491SMichael Ellerman /* First see if the events will go on as-is */ 986f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 987f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 988f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 989f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 990f2699491SMichael Ellerman cpuhw->alternatives[i]); 991f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 992f2699491SMichael Ellerman } 993f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 99482d2c16bSKajol Jain &cpuhw->avalues[i][0], event[i]->attr.config1)) 995f2699491SMichael Ellerman return -1; 996f2699491SMichael Ellerman } 997f2699491SMichael Ellerman value = mask = 0; 998f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 999f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 1000f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 100159029136SMadhavan Srinivasan 100259029136SMadhavan Srinivasan if (((((nv + tadd) ^ value) & mask) & (~grp_mask)) != 0) 1003f2699491SMichael Ellerman break; 100459029136SMadhavan Srinivasan 100559029136SMadhavan Srinivasan if (((((nv + tadd) ^ cpuhw->avalues[i][0]) & cpuhw->amasks[i][0]) 100659029136SMadhavan Srinivasan & (~grp_mask)) != 0) 100759029136SMadhavan Srinivasan break; 100859029136SMadhavan Srinivasan 1009f2699491SMichael Ellerman value = nv; 1010f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 1011f2699491SMichael Ellerman } 101259029136SMadhavan Srinivasan if (i == n_ev) { 101359029136SMadhavan Srinivasan if ((value & mask & grp_mask) != (mask & grp_val)) 101459029136SMadhavan Srinivasan return -1; 101559029136SMadhavan Srinivasan else 1016f2699491SMichael Ellerman return 0; /* all OK */ 101759029136SMadhavan Srinivasan } 1018f2699491SMichael Ellerman 1019f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 1020f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1021f2699491SMichael Ellerman return -1; 1022f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 1023f2699491SMichael Ellerman choice[i] = 0; 1024f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 1025f2699491SMichael Ellerman cpuhw->alternatives[i]); 1026f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 1027f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 1028f2699491SMichael Ellerman &cpuhw->amasks[i][j], 102982d2c16bSKajol Jain &cpuhw->avalues[i][j], 103082d2c16bSKajol Jain event[i]->attr.config1); 1031f2699491SMichael Ellerman } 1032f2699491SMichael Ellerman 1033f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 1034f2699491SMichael Ellerman i = 0; 1035f2699491SMichael Ellerman j = -1; 1036f2699491SMichael Ellerman value = mask = nv = 0; 1037f2699491SMichael Ellerman while (i < n_ev) { 1038f2699491SMichael Ellerman if (j >= 0) { 1039f2699491SMichael Ellerman /* we're backtracking, restore context */ 1040f2699491SMichael Ellerman value = svalues[i]; 1041f2699491SMichael Ellerman mask = smasks[i]; 1042f2699491SMichael Ellerman j = choice[i]; 1043f2699491SMichael Ellerman } 1044f2699491SMichael Ellerman /* 1045f2699491SMichael Ellerman * See if any alternative k for event_id i, 1046f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 1047f2699491SMichael Ellerman */ 1048f2699491SMichael Ellerman while (++j < n_alt[i]) { 1049f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 1050f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 1051f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 1052f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 1053f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 1054f2699491SMichael Ellerman break; 1055f2699491SMichael Ellerman } 1056f2699491SMichael Ellerman if (j >= n_alt[i]) { 1057f2699491SMichael Ellerman /* 1058f2699491SMichael Ellerman * No feasible alternative, backtrack 1059f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 1060f2699491SMichael Ellerman * alternatives from where we got up to. 1061f2699491SMichael Ellerman */ 1062f2699491SMichael Ellerman if (--i < 0) 1063f2699491SMichael Ellerman return -1; 1064f2699491SMichael Ellerman } else { 1065f2699491SMichael Ellerman /* 1066f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 1067f2699491SMichael Ellerman * remember where we got up to with this event_id, 1068f2699491SMichael Ellerman * go on to the next event_id, and start with 1069f2699491SMichael Ellerman * the first alternative for it. 1070f2699491SMichael Ellerman */ 1071f2699491SMichael Ellerman choice[i] = j; 1072f2699491SMichael Ellerman svalues[i] = value; 1073f2699491SMichael Ellerman smasks[i] = mask; 1074f2699491SMichael Ellerman value = nv; 1075f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 1076f2699491SMichael Ellerman ++i; 1077f2699491SMichael Ellerman j = -1; 1078f2699491SMichael Ellerman } 1079f2699491SMichael Ellerman } 1080f2699491SMichael Ellerman 1081f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 1082f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 1083f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 1084f2699491SMichael Ellerman return 0; 1085f2699491SMichael Ellerman } 1086f2699491SMichael Ellerman 1087f2699491SMichael Ellerman /* 1088f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 1089f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 1090f2699491SMichael Ellerman * added events. 1091f2699491SMichael Ellerman */ 1092f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 1093f2699491SMichael Ellerman int n_prev, int n_new) 1094f2699491SMichael Ellerman { 1095f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 1096f2699491SMichael Ellerman int i, n, first; 1097f2699491SMichael Ellerman struct perf_event *event; 1098f2699491SMichael Ellerman 10999de5cb0fSMichael Ellerman /* 11009de5cb0fSMichael Ellerman * If the PMU we're on supports per event exclude settings then we 11019de5cb0fSMichael Ellerman * don't need to do any of this logic. NB. This assumes no PMU has both 11029de5cb0fSMichael Ellerman * per event exclude and limited PMCs. 11039de5cb0fSMichael Ellerman */ 11049de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 11059de5cb0fSMichael Ellerman return 0; 11069de5cb0fSMichael Ellerman 1107f2699491SMichael Ellerman n = n_prev + n_new; 1108f2699491SMichael Ellerman if (n <= 1) 1109f2699491SMichael Ellerman return 0; 1110f2699491SMichael Ellerman 1111f2699491SMichael Ellerman first = 1; 1112f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 1113f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 1114f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 1115f2699491SMichael Ellerman continue; 1116f2699491SMichael Ellerman } 1117f2699491SMichael Ellerman event = ctrs[i]; 1118f2699491SMichael Ellerman if (first) { 1119f2699491SMichael Ellerman eu = event->attr.exclude_user; 1120f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 1121f2699491SMichael Ellerman eh = event->attr.exclude_hv; 1122f2699491SMichael Ellerman first = 0; 1123f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 1124f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 1125f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 1126f2699491SMichael Ellerman return -EAGAIN; 1127f2699491SMichael Ellerman } 1128f2699491SMichael Ellerman } 1129f2699491SMichael Ellerman 1130f2699491SMichael Ellerman if (eu || ek || eh) 1131f2699491SMichael Ellerman for (i = 0; i < n; ++i) 1132f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 1133f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 1134f2699491SMichael Ellerman 1135f2699491SMichael Ellerman return 0; 1136f2699491SMichael Ellerman } 1137f2699491SMichael Ellerman 1138f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 1139f2699491SMichael Ellerman { 1140f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 1141f2699491SMichael Ellerman 1142f2699491SMichael Ellerman /* 1143f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 1144f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 1145f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 1146f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 1147027dfac6SMichael Ellerman * number of events to rollback at once. If we detect a rollback 1148f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 1149f2699491SMichael Ellerman * counters. 1150f2699491SMichael Ellerman */ 1151f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 1152f2699491SMichael Ellerman delta = 0; 1153f2699491SMichael Ellerman 1154f2699491SMichael Ellerman return delta; 1155f2699491SMichael Ellerman } 1156f2699491SMichael Ellerman 1157f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 1158f2699491SMichael Ellerman { 1159f2699491SMichael Ellerman s64 val, delta, prev; 1160f2699491SMichael Ellerman 1161f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1162f2699491SMichael Ellerman return; 1163f2699491SMichael Ellerman 1164f2699491SMichael Ellerman if (!event->hw.idx) 1165f2699491SMichael Ellerman return; 1166330a1eb7SMichael Ellerman 1167330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 1168330a1eb7SMichael Ellerman val = read_pmc(event->hw.idx); 1169330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, val); 1170330a1eb7SMichael Ellerman return; 1171330a1eb7SMichael Ellerman } 1172330a1eb7SMichael Ellerman 1173f2699491SMichael Ellerman /* 1174f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 1175f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 1176f2699491SMichael Ellerman * Therefore we treat them like NMIs. 1177f2699491SMichael Ellerman */ 1178f2699491SMichael Ellerman do { 1179f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1180f2699491SMichael Ellerman barrier(); 1181f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 1182f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1183f2699491SMichael Ellerman if (!delta) 1184f2699491SMichael Ellerman return; 1185f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1186f2699491SMichael Ellerman 1187f2699491SMichael Ellerman local64_add(delta, &event->count); 1188f5602941SAnton Blanchard 1189f5602941SAnton Blanchard /* 1190f5602941SAnton Blanchard * A number of places program the PMC with (0x80000000 - period_left). 1191f5602941SAnton Blanchard * We never want period_left to be less than 1 because we will program 1192f5602941SAnton Blanchard * the PMC with a value >= 0x800000000 and an edge detected PMC will 1193f5602941SAnton Blanchard * roll around to 0 before taking an exception. We have seen this 1194f5602941SAnton Blanchard * on POWER8. 1195f5602941SAnton Blanchard * 1196f5602941SAnton Blanchard * To fix this, clamp the minimum value of period_left to 1. 1197f5602941SAnton Blanchard */ 1198f5602941SAnton Blanchard do { 1199f5602941SAnton Blanchard prev = local64_read(&event->hw.period_left); 1200f5602941SAnton Blanchard val = prev - delta; 1201f5602941SAnton Blanchard if (val < 1) 1202f5602941SAnton Blanchard val = 1; 1203f5602941SAnton Blanchard } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1204f2699491SMichael Ellerman } 1205f2699491SMichael Ellerman 1206f2699491SMichael Ellerman /* 1207f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 1208f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 1209f2699491SMichael Ellerman * us if `event' is using such a PMC. 1210f2699491SMichael Ellerman */ 1211f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 1212f2699491SMichael Ellerman { 1213f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1214f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 1215f2699491SMichael Ellerman } 1216f2699491SMichael Ellerman 1217f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1218f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1219f2699491SMichael Ellerman { 1220f2699491SMichael Ellerman struct perf_event *event; 1221f2699491SMichael Ellerman u64 val, prev, delta; 1222f2699491SMichael Ellerman int i; 1223f2699491SMichael Ellerman 1224f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1225f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1226f2699491SMichael Ellerman if (!event->hw.idx) 1227f2699491SMichael Ellerman continue; 1228f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1229f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1230f2699491SMichael Ellerman event->hw.idx = 0; 1231f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1232f2699491SMichael Ellerman if (delta) 1233f2699491SMichael Ellerman local64_add(delta, &event->count); 1234f2699491SMichael Ellerman } 1235f2699491SMichael Ellerman } 1236f2699491SMichael Ellerman 1237f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1238f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1239f2699491SMichael Ellerman { 1240f2699491SMichael Ellerman struct perf_event *event; 1241f2699491SMichael Ellerman u64 val, prev; 1242f2699491SMichael Ellerman int i; 1243f2699491SMichael Ellerman 1244f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1245f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1246f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 1247f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1248f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1249f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 1250f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1251f2699491SMichael Ellerman perf_event_update_userpage(event); 1252f2699491SMichael Ellerman } 1253f2699491SMichael Ellerman } 1254f2699491SMichael Ellerman 1255f2699491SMichael Ellerman /* 1256f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 1257f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 1258f2699491SMichael Ellerman * other events. We try to keep the values from the limited 1259f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 1260f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 1261f2699491SMichael Ellerman * the limited events as small and consistent as possible. 1262f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 1263f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 1264f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 1265f2699491SMichael Ellerman */ 1266f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1267f2699491SMichael Ellerman { 1268f2699491SMichael Ellerman unsigned long pmc5, pmc6; 1269f2699491SMichael Ellerman 1270f2699491SMichael Ellerman if (!cpuhw->n_limited) { 1271f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1272f2699491SMichael Ellerman return; 1273f2699491SMichael Ellerman } 1274f2699491SMichael Ellerman 1275f2699491SMichael Ellerman /* 1276f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 1277f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 1278f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 1279f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 1280f2699491SMichael Ellerman * interrupt enable bits turned off. 1281f2699491SMichael Ellerman */ 1282f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1283f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 1284f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1285f2699491SMichael Ellerman "i" (SPRN_MMCR0), 1286f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1287f2699491SMichael Ellerman 1288f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 1289f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 1290f2699491SMichael Ellerman else 1291f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 1292f2699491SMichael Ellerman 1293f2699491SMichael Ellerman /* 1294f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 1295f2699491SMichael Ellerman * enable bits, if necessary. 1296f2699491SMichael Ellerman */ 1297f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1298f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1299f2699491SMichael Ellerman } 1300f2699491SMichael Ellerman 1301f2699491SMichael Ellerman /* 1302f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 1303f2699491SMichael Ellerman * events to be added or removed. 1304f2699491SMichael Ellerman */ 1305f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 1306f2699491SMichael Ellerman { 1307f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 13081cade527SAthira Rajeev unsigned long flags, mmcr0, val, mmcra; 1309f2699491SMichael Ellerman 1310f2699491SMichael Ellerman if (!ppmu) 1311f2699491SMichael Ellerman return; 1312f2699491SMichael Ellerman local_irq_save(flags); 131369111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1314f2699491SMichael Ellerman 1315f2699491SMichael Ellerman if (!cpuhw->disabled) { 1316f2699491SMichael Ellerman /* 1317f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 1318f2699491SMichael Ellerman */ 1319f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 1320f2699491SMichael Ellerman ppc_enable_pmcs(); 1321f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 1322f2699491SMichael Ellerman } 1323f2699491SMichael Ellerman 1324f2699491SMichael Ellerman /* 132576cb8a78SMichael Ellerman * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 13262c9ac51bSAthira Rajeev * Also clear PMXE to disable PMI's getting triggered in some 13272c9ac51bSAthira Rajeev * corner cases during PMU disable. 1328378a6ee9SMichael Ellerman */ 1329330a1eb7SMichael Ellerman val = mmcr0 = mfspr(SPRN_MMCR0); 1330378a6ee9SMichael Ellerman val |= MMCR0_FC; 133176cb8a78SMichael Ellerman val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 13322c9ac51bSAthira Rajeev MMCR0_PMXE | MMCR0_FC56); 133391668ab7SAthira Rajeev /* Set mmcr0 PMCCEXT for p10 */ 133491668ab7SAthira Rajeev if (ppmu->flags & PPMU_ARCH_31) 133591668ab7SAthira Rajeev val |= MMCR0_PMCCEXT; 1336378a6ee9SMichael Ellerman 1337378a6ee9SMichael Ellerman /* 1338378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 1339378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 1340378a6ee9SMichael Ellerman * before we return. 1341378a6ee9SMichael Ellerman */ 1342378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 1343378a6ee9SMichael Ellerman mb(); 1344e1ebd0e5SMichael Ellerman isync(); 1345378a6ee9SMichael Ellerman 13462c9ac51bSAthira Rajeev /* 13472c9ac51bSAthira Rajeev * Some corner cases could clear the PMU counter overflow 13482c9ac51bSAthira Rajeev * while a masked PMI is pending. One such case is when 13492c9ac51bSAthira Rajeev * a PMI happens during interrupt replay and perf counter 13502c9ac51bSAthira Rajeev * values are cleared by PMU callbacks before replay. 13512c9ac51bSAthira Rajeev * 13522c9ac51bSAthira Rajeev * If any PMC corresponding to the active PMU events are 13532c9ac51bSAthira Rajeev * overflown, disable the interrupt by clearing the paca 13542c9ac51bSAthira Rajeev * bit for PMI since we are disabling the PMU now. 13552c9ac51bSAthira Rajeev * Otherwise provide a warning if there is PMI pending, but 13562c9ac51bSAthira Rajeev * no counter is found overflown. 13572c9ac51bSAthira Rajeev */ 13582c9ac51bSAthira Rajeev if (any_pmc_overflown(cpuhw)) 13592c9ac51bSAthira Rajeev clear_pmi_irq_pending(); 13602c9ac51bSAthira Rajeev else 13612c9ac51bSAthira Rajeev WARN_ON(pmi_irq_pending()); 13622c9ac51bSAthira Rajeev 13631cade527SAthira Rajeev val = mmcra = cpuhw->mmcr.mmcra; 13641cade527SAthira Rajeev 1365378a6ee9SMichael Ellerman /* 1366f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 1367f2699491SMichael Ellerman */ 13681cade527SAthira Rajeev if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) 13691cade527SAthira Rajeev val &= ~MMCRA_SAMPLE_ENABLE; 13701cade527SAthira Rajeev 13711cade527SAthira Rajeev /* Disable BHRB via mmcra (BHRBRD) for p10 */ 13721cade527SAthira Rajeev if (ppmu->flags & PPMU_ARCH_31) 13731cade527SAthira Rajeev val |= MMCRA_BHRB_DISABLE; 13741cade527SAthira Rajeev 13751cade527SAthira Rajeev /* 13761cade527SAthira Rajeev * Write SPRN_MMCRA if mmcra has either disabled 13771cade527SAthira Rajeev * instruction sampling or BHRB. 13781cade527SAthira Rajeev */ 13791cade527SAthira Rajeev if (val != mmcra) { 13801cade527SAthira Rajeev mtspr(SPRN_MMCRA, mmcra); 1381f2699491SMichael Ellerman mb(); 1382e1ebd0e5SMichael Ellerman isync(); 1383f2699491SMichael Ellerman } 1384f2699491SMichael Ellerman 1385378a6ee9SMichael Ellerman cpuhw->disabled = 1; 1386378a6ee9SMichael Ellerman cpuhw->n_added = 0; 1387330a1eb7SMichael Ellerman 1388330a1eb7SMichael Ellerman ebb_switch_out(mmcr0); 1389e1ebd0e5SMichael Ellerman 1390e1ebd0e5SMichael Ellerman #ifdef CONFIG_PPC64 1391e1ebd0e5SMichael Ellerman /* 1392e1ebd0e5SMichael Ellerman * These are readable by userspace, may contain kernel 1393e1ebd0e5SMichael Ellerman * addresses and are not switched by context switch, so clear 1394e1ebd0e5SMichael Ellerman * them now to avoid leaking anything to userspace in general 1395e1ebd0e5SMichael Ellerman * including to another process. 1396e1ebd0e5SMichael Ellerman */ 1397e1ebd0e5SMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) { 1398e1ebd0e5SMichael Ellerman mtspr(SPRN_SDAR, 0); 1399e1ebd0e5SMichael Ellerman mtspr(SPRN_SIAR, 0); 1400e1ebd0e5SMichael Ellerman } 1401e1ebd0e5SMichael Ellerman #endif 1402f2699491SMichael Ellerman } 1403330a1eb7SMichael Ellerman 1404f2699491SMichael Ellerman local_irq_restore(flags); 1405f2699491SMichael Ellerman } 1406f2699491SMichael Ellerman 1407f2699491SMichael Ellerman /* 1408f2699491SMichael Ellerman * Re-enable all events if disable == 0. 1409f2699491SMichael Ellerman * If we were previously disabled and events were added, then 1410f2699491SMichael Ellerman * put the new config on the PMU. 1411f2699491SMichael Ellerman */ 1412f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 1413f2699491SMichael Ellerman { 1414f2699491SMichael Ellerman struct perf_event *event; 1415f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1416f2699491SMichael Ellerman unsigned long flags; 1417f2699491SMichael Ellerman long i; 1418330a1eb7SMichael Ellerman unsigned long val, mmcr0; 1419f2699491SMichael Ellerman s64 left; 1420f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 1421f2699491SMichael Ellerman int n_lim; 1422f2699491SMichael Ellerman int idx; 1423330a1eb7SMichael Ellerman bool ebb; 1424f2699491SMichael Ellerman 1425f2699491SMichael Ellerman if (!ppmu) 1426f2699491SMichael Ellerman return; 1427f2699491SMichael Ellerman local_irq_save(flags); 14280a48843dSMichael Ellerman 142969111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 14300a48843dSMichael Ellerman if (!cpuhw->disabled) 14310a48843dSMichael Ellerman goto out; 14320a48843dSMichael Ellerman 14334ea355b5SMichael Ellerman if (cpuhw->n_events == 0) { 14344ea355b5SMichael Ellerman ppc_set_pmu_inuse(0); 14354ea355b5SMichael Ellerman goto out; 14364ea355b5SMichael Ellerman } 14374ea355b5SMichael Ellerman 1438f2699491SMichael Ellerman cpuhw->disabled = 0; 1439f2699491SMichael Ellerman 1440f2699491SMichael Ellerman /* 1441330a1eb7SMichael Ellerman * EBB requires an exclusive group and all events must have the EBB 1442330a1eb7SMichael Ellerman * flag set, or not set, so we can just check a single event. Also we 1443330a1eb7SMichael Ellerman * know we have at least one event. 1444330a1eb7SMichael Ellerman */ 1445330a1eb7SMichael Ellerman ebb = is_ebb_event(cpuhw->event[0]); 1446330a1eb7SMichael Ellerman 1447330a1eb7SMichael Ellerman /* 1448f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 1449f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 1450f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 1451f2699491SMichael Ellerman * (possibly updated for removal of events). 1452f2699491SMichael Ellerman */ 1453f2699491SMichael Ellerman if (!cpuhw->n_added) { 14542c9ac51bSAthira Rajeev /* 14552c9ac51bSAthira Rajeev * If there is any active event with an overflown PMC 14562c9ac51bSAthira Rajeev * value, set back PACA_IRQ_PMI which would have been 14572c9ac51bSAthira Rajeev * cleared in power_pmu_disable(). 14582c9ac51bSAthira Rajeev */ 14592c9ac51bSAthira Rajeev hard_irq_disable(); 14602c9ac51bSAthira Rajeev if (any_pmc_overflown(cpuhw)) 14612c9ac51bSAthira Rajeev set_pmi_irq_pending(); 14622c9ac51bSAthira Rajeev 146378d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 146478d76819SAthira Rajeev mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 1465c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) 1466c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1467f2699491SMichael Ellerman goto out_enable; 1468f2699491SMichael Ellerman } 1469f2699491SMichael Ellerman 1470f2699491SMichael Ellerman /* 147179a4cb28SMichael Ellerman * Clear all MMCR settings and recompute them for the new set of events. 1472f2699491SMichael Ellerman */ 147378d76819SAthira Rajeev memset(&cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 147479a4cb28SMichael Ellerman 1475f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 147682d2c16bSKajol Jain &cpuhw->mmcr, cpuhw->event, ppmu->flags)) { 1477f2699491SMichael Ellerman /* shouldn't ever get here */ 1478f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 1479f2699491SMichael Ellerman goto out; 1480f2699491SMichael Ellerman } 1481f2699491SMichael Ellerman 14829de5cb0fSMichael Ellerman if (!(ppmu->flags & PPMU_ARCH_207S)) { 1483f2699491SMichael Ellerman /* 14849de5cb0fSMichael Ellerman * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 14859de5cb0fSMichael Ellerman * bits for the first event. We have already checked that all 14869de5cb0fSMichael Ellerman * events have the same value for these bits as the first event. 1487f2699491SMichael Ellerman */ 1488f2699491SMichael Ellerman event = cpuhw->event[0]; 1489f2699491SMichael Ellerman if (event->attr.exclude_user) 149078d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_FCP; 1491f2699491SMichael Ellerman if (event->attr.exclude_kernel) 149278d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= freeze_events_kernel; 1493f2699491SMichael Ellerman if (event->attr.exclude_hv) 149478d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_FCHV; 14959de5cb0fSMichael Ellerman } 1496f2699491SMichael Ellerman 1497f2699491SMichael Ellerman /* 1498f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 1499f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 1500f2699491SMichael Ellerman * Then unfreeze the events. 1501f2699491SMichael Ellerman */ 1502f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 150378d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra & ~MMCRA_SAMPLE_ENABLE); 150478d76819SAthira Rajeev mtspr(SPRN_MMCR1, cpuhw->mmcr.mmcr1); 150578d76819SAthira Rajeev mtspr(SPRN_MMCR0, (cpuhw->mmcr.mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1506f2699491SMichael Ellerman | MMCR0_FC); 15079de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 150878d76819SAthira Rajeev mtspr(SPRN_MMCR2, cpuhw->mmcr.mmcr2); 1509f2699491SMichael Ellerman 1510c718547eSMadhavan Srinivasan if (ppmu->flags & PPMU_ARCH_31) 1511c718547eSMadhavan Srinivasan mtspr(SPRN_MMCR3, cpuhw->mmcr.mmcr3); 1512f2699491SMichael Ellerman 1513f2699491SMichael Ellerman /* 1514f2699491SMichael Ellerman * Read off any pre-existing events that need to move 1515f2699491SMichael Ellerman * to another PMC. 1516f2699491SMichael Ellerman */ 1517f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1518f2699491SMichael Ellerman event = cpuhw->event[i]; 1519f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1520f2699491SMichael Ellerman power_pmu_read(event); 1521f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1522f2699491SMichael Ellerman event->hw.idx = 0; 1523f2699491SMichael Ellerman } 1524f2699491SMichael Ellerman } 1525f2699491SMichael Ellerman 1526f2699491SMichael Ellerman /* 1527f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 1528f2699491SMichael Ellerman */ 1529f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 1530f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1531f2699491SMichael Ellerman event = cpuhw->event[i]; 1532f2699491SMichael Ellerman if (event->hw.idx) 1533f2699491SMichael Ellerman continue; 1534f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1535f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1536f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1537f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1538f2699491SMichael Ellerman ++n_lim; 1539f2699491SMichael Ellerman continue; 1540f2699491SMichael Ellerman } 1541330a1eb7SMichael Ellerman 1542330a1eb7SMichael Ellerman if (ebb) 1543330a1eb7SMichael Ellerman val = local64_read(&event->hw.prev_count); 1544330a1eb7SMichael Ellerman else { 1545f2699491SMichael Ellerman val = 0; 1546f2699491SMichael Ellerman if (event->hw.sample_period) { 1547f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1548f2699491SMichael Ellerman if (left < 0x80000000L) 1549f2699491SMichael Ellerman val = 0x80000000L - left; 1550f2699491SMichael Ellerman } 1551f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1552330a1eb7SMichael Ellerman } 1553330a1eb7SMichael Ellerman 1554f2699491SMichael Ellerman event->hw.idx = idx; 1555f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1556f2699491SMichael Ellerman val = 0; 1557f2699491SMichael Ellerman write_pmc(idx, val); 1558330a1eb7SMichael Ellerman 1559f2699491SMichael Ellerman perf_event_update_userpage(event); 1560f2699491SMichael Ellerman } 1561f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 156278d76819SAthira Rajeev cpuhw->mmcr.mmcr0 |= MMCR0_PMXE | MMCR0_FCECE; 1563f2699491SMichael Ellerman 1564f2699491SMichael Ellerman out_enable: 1565c2e37a26SMichael Ellerman pmao_restore_workaround(ebb); 1566c2e37a26SMichael Ellerman 15679de5cb0fSMichael Ellerman mmcr0 = ebb_switch_in(ebb, cpuhw); 1568330a1eb7SMichael Ellerman 1569f2699491SMichael Ellerman mb(); 1570b4d6c06cSAnshuman Khandual if (cpuhw->bhrb_users) 1571b4d6c06cSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 1572b4d6c06cSAnshuman Khandual 1573330a1eb7SMichael Ellerman write_mmcr0(cpuhw, mmcr0); 1574f2699491SMichael Ellerman 1575f2699491SMichael Ellerman /* 1576f2699491SMichael Ellerman * Enable instruction sampling if necessary 1577f2699491SMichael Ellerman */ 157878d76819SAthira Rajeev if (cpuhw->mmcr.mmcra & MMCRA_SAMPLE_ENABLE) { 1579f2699491SMichael Ellerman mb(); 158078d76819SAthira Rajeev mtspr(SPRN_MMCRA, cpuhw->mmcr.mmcra); 1581f2699491SMichael Ellerman } 1582f2699491SMichael Ellerman 1583f2699491SMichael Ellerman out: 15843925f46bSAnshuman Khandual 1585f2699491SMichael Ellerman local_irq_restore(flags); 1586f2699491SMichael Ellerman } 1587f2699491SMichael Ellerman 1588f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1589f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1590f2699491SMichael Ellerman unsigned int *flags) 1591f2699491SMichael Ellerman { 1592f2699491SMichael Ellerman int n = 0; 1593f2699491SMichael Ellerman struct perf_event *event; 1594f2699491SMichael Ellerman 15955aa04b3eSRavi Bangoria if (group->pmu->task_ctx_nr == perf_hw_context) { 1596f2699491SMichael Ellerman if (n >= max_count) 1597f2699491SMichael Ellerman return -1; 1598f2699491SMichael Ellerman ctrs[n] = group; 1599f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1600f2699491SMichael Ellerman events[n++] = group->hw.config; 1601f2699491SMichael Ellerman } 1602edb39592SPeter Zijlstra for_each_sibling_event(event, group) { 16035aa04b3eSRavi Bangoria if (event->pmu->task_ctx_nr == perf_hw_context && 1604f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1605f2699491SMichael Ellerman if (n >= max_count) 1606f2699491SMichael Ellerman return -1; 1607f2699491SMichael Ellerman ctrs[n] = event; 1608f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1609f2699491SMichael Ellerman events[n++] = event->hw.config; 1610f2699491SMichael Ellerman } 1611f2699491SMichael Ellerman } 1612f2699491SMichael Ellerman return n; 1613f2699491SMichael Ellerman } 1614f2699491SMichael Ellerman 1615f2699491SMichael Ellerman /* 1616788faab7STobias Tefke * Add an event to the PMU. 1617f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1618f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1619f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1620f2699491SMichael Ellerman */ 1621f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1622f2699491SMichael Ellerman { 1623f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1624f2699491SMichael Ellerman unsigned long flags; 1625f2699491SMichael Ellerman int n0; 1626f2699491SMichael Ellerman int ret = -EAGAIN; 1627f2699491SMichael Ellerman 1628f2699491SMichael Ellerman local_irq_save(flags); 1629f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1630f2699491SMichael Ellerman 1631f2699491SMichael Ellerman /* 1632f2699491SMichael Ellerman * Add the event to the list (if there is room) 1633f2699491SMichael Ellerman * and check whether the total set is still feasible. 1634f2699491SMichael Ellerman */ 163569111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1636f2699491SMichael Ellerman n0 = cpuhw->n_events; 1637f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1638f2699491SMichael Ellerman goto out; 1639f2699491SMichael Ellerman cpuhw->event[n0] = event; 1640f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1641f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1642f2699491SMichael Ellerman 1643f53d168cSsukadev@linux.vnet.ibm.com /* 1644f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1645f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1646f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1647f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1648f53d168cSsukadev@linux.vnet.ibm.com */ 1649f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1650f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1651f53d168cSsukadev@linux.vnet.ibm.com else 1652f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1653f2699491SMichael Ellerman 1654f2699491SMichael Ellerman /* 1655f2699491SMichael Ellerman * If group events scheduling transaction was started, 1656f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1657f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1658f2699491SMichael Ellerman */ 16598f3e5684SSukadev Bhattiprolu if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) 1660f2699491SMichael Ellerman goto nocheck; 1661f2699491SMichael Ellerman 1662f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1663f2699491SMichael Ellerman goto out; 166482d2c16bSKajol Jain if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1, cpuhw->event)) 1665f2699491SMichael Ellerman goto out; 1666f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1667f2699491SMichael Ellerman 1668f2699491SMichael Ellerman nocheck: 1669330a1eb7SMichael Ellerman ebb_event_add(event); 1670330a1eb7SMichael Ellerman 1671f2699491SMichael Ellerman ++cpuhw->n_events; 1672f2699491SMichael Ellerman ++cpuhw->n_added; 1673f2699491SMichael Ellerman 1674f2699491SMichael Ellerman ret = 0; 1675f2699491SMichael Ellerman out: 1676ff3d79dcSAnshuman Khandual if (has_branch_stack(event)) { 1677b460b512SAlexey Kardashevskiy u64 bhrb_filter = -1; 1678b460b512SAlexey Kardashevskiy 1679b460b512SAlexey Kardashevskiy if (ppmu->bhrb_filter_map) 1680b460b512SAlexey Kardashevskiy bhrb_filter = ppmu->bhrb_filter_map( 1681ff3d79dcSAnshuman Khandual event->attr.branch_sample_type); 1682b460b512SAlexey Kardashevskiy 1683b460b512SAlexey Kardashevskiy if (bhrb_filter != -1) { 1684b460b512SAlexey Kardashevskiy cpuhw->bhrb_filter = bhrb_filter; 1685b460b512SAlexey Kardashevskiy power_pmu_bhrb_enable(event); 1686b460b512SAlexey Kardashevskiy } 1687ff3d79dcSAnshuman Khandual } 16883925f46bSAnshuman Khandual 1689f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1690f2699491SMichael Ellerman local_irq_restore(flags); 1691f2699491SMichael Ellerman return ret; 1692f2699491SMichael Ellerman } 1693f2699491SMichael Ellerman 1694f2699491SMichael Ellerman /* 1695788faab7STobias Tefke * Remove an event from the PMU. 1696f2699491SMichael Ellerman */ 1697f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1698f2699491SMichael Ellerman { 1699f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1700f2699491SMichael Ellerman long i; 1701f2699491SMichael Ellerman unsigned long flags; 1702f2699491SMichael Ellerman 1703f2699491SMichael Ellerman local_irq_save(flags); 1704f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1705f2699491SMichael Ellerman 1706f2699491SMichael Ellerman power_pmu_read(event); 1707f2699491SMichael Ellerman 170869111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1709f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1710f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1711f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1712f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1713f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1714f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1715f2699491SMichael Ellerman } 1716f2699491SMichael Ellerman --cpuhw->n_events; 171778d76819SAthira Rajeev ppmu->disable_pmc(event->hw.idx - 1, &cpuhw->mmcr); 1718f2699491SMichael Ellerman if (event->hw.idx) { 1719f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1720f2699491SMichael Ellerman event->hw.idx = 0; 1721f2699491SMichael Ellerman } 1722f2699491SMichael Ellerman perf_event_update_userpage(event); 1723f2699491SMichael Ellerman break; 1724f2699491SMichael Ellerman } 1725f2699491SMichael Ellerman } 1726f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1727f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1728f2699491SMichael Ellerman break; 1729f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1730f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1731f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1732f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1733f2699491SMichael Ellerman } 1734f2699491SMichael Ellerman --cpuhw->n_limited; 1735f2699491SMichael Ellerman } 1736f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1737f2699491SMichael Ellerman /* disable exceptions if no events are running */ 173878d76819SAthira Rajeev cpuhw->mmcr.mmcr0 &= ~(MMCR0_PMXE | MMCR0_FCECE); 1739f2699491SMichael Ellerman } 1740f2699491SMichael Ellerman 17413925f46bSAnshuman Khandual if (has_branch_stack(event)) 17423925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 17433925f46bSAnshuman Khandual 1744f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1745f2699491SMichael Ellerman local_irq_restore(flags); 1746f2699491SMichael Ellerman } 1747f2699491SMichael Ellerman 1748f2699491SMichael Ellerman /* 1749f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1750f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1751f2699491SMichael Ellerman */ 1752f2699491SMichael Ellerman 1753f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1754f2699491SMichael Ellerman { 1755f2699491SMichael Ellerman unsigned long flags; 1756f2699491SMichael Ellerman s64 left; 1757f2699491SMichael Ellerman unsigned long val; 1758f2699491SMichael Ellerman 1759f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1760f2699491SMichael Ellerman return; 1761f2699491SMichael Ellerman 1762f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1763f2699491SMichael Ellerman return; 1764f2699491SMichael Ellerman 1765f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1766f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1767f2699491SMichael Ellerman 1768f2699491SMichael Ellerman local_irq_save(flags); 1769f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1770f2699491SMichael Ellerman 1771f2699491SMichael Ellerman event->hw.state = 0; 1772f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1773f2699491SMichael Ellerman 1774f2699491SMichael Ellerman val = 0; 1775f2699491SMichael Ellerman if (left < 0x80000000L) 1776f2699491SMichael Ellerman val = 0x80000000L - left; 1777f2699491SMichael Ellerman 1778f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1779f2699491SMichael Ellerman 1780f2699491SMichael Ellerman perf_event_update_userpage(event); 1781f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1782f2699491SMichael Ellerman local_irq_restore(flags); 1783f2699491SMichael Ellerman } 1784f2699491SMichael Ellerman 1785f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1786f2699491SMichael Ellerman { 1787f2699491SMichael Ellerman unsigned long flags; 1788f2699491SMichael Ellerman 1789f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1790f2699491SMichael Ellerman return; 1791f2699491SMichael Ellerman 1792f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1793f2699491SMichael Ellerman return; 1794f2699491SMichael Ellerman 1795f2699491SMichael Ellerman local_irq_save(flags); 1796f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1797f2699491SMichael Ellerman 1798f2699491SMichael Ellerman power_pmu_read(event); 1799f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1800f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1801f2699491SMichael Ellerman 1802f2699491SMichael Ellerman perf_event_update_userpage(event); 1803f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1804f2699491SMichael Ellerman local_irq_restore(flags); 1805f2699491SMichael Ellerman } 1806f2699491SMichael Ellerman 1807f2699491SMichael Ellerman /* 1808f2699491SMichael Ellerman * Start group events scheduling transaction 1809f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1810f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1811fbbe0701SSukadev Bhattiprolu * 1812fbbe0701SSukadev Bhattiprolu * We only support PERF_PMU_TXN_ADD transactions. Save the 1813fbbe0701SSukadev Bhattiprolu * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1814fbbe0701SSukadev Bhattiprolu * transactions. 1815f2699491SMichael Ellerman */ 1816fbbe0701SSukadev Bhattiprolu static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1817f2699491SMichael Ellerman { 181869111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1819f2699491SMichael Ellerman 1820fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1821fbbe0701SSukadev Bhattiprolu 1822fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = txn_flags; 1823fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1824fbbe0701SSukadev Bhattiprolu return; 1825fbbe0701SSukadev Bhattiprolu 1826f2699491SMichael Ellerman perf_pmu_disable(pmu); 1827f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1828f2699491SMichael Ellerman } 1829f2699491SMichael Ellerman 1830f2699491SMichael Ellerman /* 1831f2699491SMichael Ellerman * Stop group events scheduling transaction 1832f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1833f2699491SMichael Ellerman * schedulability test. 1834f2699491SMichael Ellerman */ 1835e51df2c1SAnton Blanchard static void power_pmu_cancel_txn(struct pmu *pmu) 1836f2699491SMichael Ellerman { 183769111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1838fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 1839fbbe0701SSukadev Bhattiprolu 1840fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1841fbbe0701SSukadev Bhattiprolu 1842fbbe0701SSukadev Bhattiprolu txn_flags = cpuhw->txn_flags; 1843fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1844fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1845fbbe0701SSukadev Bhattiprolu return; 1846f2699491SMichael Ellerman 1847f2699491SMichael Ellerman perf_pmu_enable(pmu); 1848f2699491SMichael Ellerman } 1849f2699491SMichael Ellerman 1850f2699491SMichael Ellerman /* 1851f2699491SMichael Ellerman * Commit group events scheduling transaction 1852f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1853f2699491SMichael Ellerman * Return 0 if success 1854f2699491SMichael Ellerman */ 1855e51df2c1SAnton Blanchard static int power_pmu_commit_txn(struct pmu *pmu) 1856f2699491SMichael Ellerman { 1857f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1858f2699491SMichael Ellerman long i, n; 1859f2699491SMichael Ellerman 1860f2699491SMichael Ellerman if (!ppmu) 1861f2699491SMichael Ellerman return -EAGAIN; 1862fbbe0701SSukadev Bhattiprolu 186369111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1864fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1865fbbe0701SSukadev Bhattiprolu 1866fbbe0701SSukadev Bhattiprolu if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 1867fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1868fbbe0701SSukadev Bhattiprolu return 0; 1869fbbe0701SSukadev Bhattiprolu } 1870fbbe0701SSukadev Bhattiprolu 1871f2699491SMichael Ellerman n = cpuhw->n_events; 1872f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1873f2699491SMichael Ellerman return -EAGAIN; 187482d2c16bSKajol Jain i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n, cpuhw->event); 1875f2699491SMichael Ellerman if (i < 0) 1876f2699491SMichael Ellerman return -EAGAIN; 1877f2699491SMichael Ellerman 1878f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1879f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1880f2699491SMichael Ellerman 1881fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1882f2699491SMichael Ellerman perf_pmu_enable(pmu); 1883f2699491SMichael Ellerman return 0; 1884f2699491SMichael Ellerman } 1885f2699491SMichael Ellerman 1886f2699491SMichael Ellerman /* 1887f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1888f2699491SMichael Ellerman * or 0 if not. 1889788faab7STobias Tefke * An event can only go on a limited PMC if it counts something 1890f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1891f2699491SMichael Ellerman * doesn't exclude any processor mode. 1892f2699491SMichael Ellerman */ 1893f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1894f2699491SMichael Ellerman unsigned int flags) 1895f2699491SMichael Ellerman { 1896f2699491SMichael Ellerman int n; 1897f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1898f2699491SMichael Ellerman 1899f2699491SMichael Ellerman if (event->attr.exclude_user 1900f2699491SMichael Ellerman || event->attr.exclude_kernel 1901f2699491SMichael Ellerman || event->attr.exclude_hv 1902f2699491SMichael Ellerman || event->attr.sample_period) 1903f2699491SMichael Ellerman return 0; 1904f2699491SMichael Ellerman 1905f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1906f2699491SMichael Ellerman return 1; 1907f2699491SMichael Ellerman 1908f2699491SMichael Ellerman /* 1909f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1910f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1911f2699491SMichael Ellerman */ 1912f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1913f2699491SMichael Ellerman return 0; 1914f2699491SMichael Ellerman 1915f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1916f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1917f2699491SMichael Ellerman 1918f2699491SMichael Ellerman return n > 0; 1919f2699491SMichael Ellerman } 1920f2699491SMichael Ellerman 1921f2699491SMichael Ellerman /* 1922f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1923f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1924f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1925f2699491SMichael Ellerman */ 1926f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1927f2699491SMichael Ellerman { 1928f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1929f2699491SMichael Ellerman int n; 1930f2699491SMichael Ellerman 1931f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1932f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1933f2699491SMichael Ellerman if (!n) 1934f2699491SMichael Ellerman return 0; 1935f2699491SMichael Ellerman return alt[0]; 1936f2699491SMichael Ellerman } 1937f2699491SMichael Ellerman 1938f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1939f2699491SMichael Ellerman static atomic_t num_events; 1940f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1941f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1942f2699491SMichael Ellerman 1943f2699491SMichael Ellerman /* 1944f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1945f2699491SMichael Ellerman */ 1946f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1947f2699491SMichael Ellerman { 1948f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1949f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1950f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1951f2699491SMichael Ellerman release_pmc_hardware(); 1952f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1953f2699491SMichael Ellerman } 1954f2699491SMichael Ellerman } 1955f2699491SMichael Ellerman 1956f2699491SMichael Ellerman /* 1957f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1958f2699491SMichael Ellerman */ 1959f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1960f2699491SMichael Ellerman { 1961f2699491SMichael Ellerman unsigned long type, op, result; 19629d4fc86dSAthira Rajeev u64 ev; 1963f2699491SMichael Ellerman 1964f2699491SMichael Ellerman if (!ppmu->cache_events) 1965f2699491SMichael Ellerman return -EINVAL; 1966f2699491SMichael Ellerman 1967f2699491SMichael Ellerman /* unpack config */ 1968f2699491SMichael Ellerman type = config & 0xff; 1969f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1970f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1971f2699491SMichael Ellerman 1972f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1973f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1974f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1975f2699491SMichael Ellerman return -EINVAL; 1976f2699491SMichael Ellerman 1977f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1978f2699491SMichael Ellerman if (ev == 0) 1979f2699491SMichael Ellerman return -EOPNOTSUPP; 1980f2699491SMichael Ellerman if (ev == -1) 1981f2699491SMichael Ellerman return -EINVAL; 1982f2699491SMichael Ellerman *eventp = ev; 1983f2699491SMichael Ellerman return 0; 1984f2699491SMichael Ellerman } 1985f2699491SMichael Ellerman 1986b58064daSMadhavan Srinivasan static bool is_event_blacklisted(u64 ev) 1987b58064daSMadhavan Srinivasan { 1988b58064daSMadhavan Srinivasan int i; 1989b58064daSMadhavan Srinivasan 1990b58064daSMadhavan Srinivasan for (i=0; i < ppmu->n_blacklist_ev; i++) { 1991b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev[i] == ev) 1992b58064daSMadhavan Srinivasan return true; 1993b58064daSMadhavan Srinivasan } 1994b58064daSMadhavan Srinivasan 1995b58064daSMadhavan Srinivasan return false; 1996b58064daSMadhavan Srinivasan } 1997b58064daSMadhavan Srinivasan 1998f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1999f2699491SMichael Ellerman { 2000f2699491SMichael Ellerman u64 ev; 2001f66de7acSAthira Rajeev unsigned long flags, irq_flags; 2002f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 2003f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 2004f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 2005f2699491SMichael Ellerman int n; 2006f2699491SMichael Ellerman int err; 2007f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 2008f2699491SMichael Ellerman 2009f2699491SMichael Ellerman if (!ppmu) 2010f2699491SMichael Ellerman return -ENOENT; 2011f2699491SMichael Ellerman 20123925f46bSAnshuman Khandual if (has_branch_stack(event)) { 20133925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 20144d9690ddSJoel Stanley if (!(ppmu->flags & PPMU_ARCH_207S)) 20155375871dSLinus Torvalds return -EOPNOTSUPP; 20163925f46bSAnshuman Khandual } 20175375871dSLinus Torvalds 2018f2699491SMichael Ellerman switch (event->attr.type) { 2019f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 2020f2699491SMichael Ellerman ev = event->attr.config; 2021f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 2022f2699491SMichael Ellerman return -EOPNOTSUPP; 2023b58064daSMadhavan Srinivasan 2024b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 2025b58064daSMadhavan Srinivasan return -EINVAL; 2026f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 2027f2699491SMichael Ellerman break; 2028f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 2029f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 2030f2699491SMichael Ellerman if (err) 2031f2699491SMichael Ellerman return err; 2032b58064daSMadhavan Srinivasan 2033b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 2034b58064daSMadhavan Srinivasan return -EINVAL; 2035f2699491SMichael Ellerman break; 2036f2699491SMichael Ellerman case PERF_TYPE_RAW: 2037f2699491SMichael Ellerman ev = event->attr.config; 2038b58064daSMadhavan Srinivasan 2039b58064daSMadhavan Srinivasan if (ppmu->blacklist_ev && is_event_blacklisted(ev)) 2040b58064daSMadhavan Srinivasan return -EINVAL; 2041f2699491SMichael Ellerman break; 2042f2699491SMichael Ellerman default: 2043f2699491SMichael Ellerman return -ENOENT; 2044f2699491SMichael Ellerman } 2045f2699491SMichael Ellerman 20462e2a441dSMadhavan Srinivasan /* 20472e2a441dSMadhavan Srinivasan * PMU config registers have fields that are 20482e2a441dSMadhavan Srinivasan * reserved and some specific values for bit fields are reserved. 20492e2a441dSMadhavan Srinivasan * For ex., MMCRA[61:62] is Randome Sampling Mode (SM) 20502e2a441dSMadhavan Srinivasan * and value of 0b11 to this field is reserved. 20512e2a441dSMadhavan Srinivasan * Check for invalid values in attr.config. 20522e2a441dSMadhavan Srinivasan */ 20532e2a441dSMadhavan Srinivasan if (ppmu->check_attr_config && 20542e2a441dSMadhavan Srinivasan ppmu->check_attr_config(event)) 20552e2a441dSMadhavan Srinivasan return -EINVAL; 20562e2a441dSMadhavan Srinivasan 2057f2699491SMichael Ellerman event->hw.config_base = ev; 2058f2699491SMichael Ellerman event->hw.idx = 0; 2059f2699491SMichael Ellerman 2060f2699491SMichael Ellerman /* 2061f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 2062f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 2063f2699491SMichael Ellerman * the user set it to. 2064f2699491SMichael Ellerman */ 2065f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 2066f2699491SMichael Ellerman event->attr.exclude_hv = 0; 2067f2699491SMichael Ellerman 2068f2699491SMichael Ellerman /* 2069f2699491SMichael Ellerman * If this is a per-task event, then we can use 2070f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 2071f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 2072f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 2073f2699491SMichael Ellerman */ 2074f2699491SMichael Ellerman flags = 0; 2075f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 2076f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 2077f2699491SMichael Ellerman 2078f2699491SMichael Ellerman /* 2079f2699491SMichael Ellerman * If this machine has limited events, check whether this 2080f2699491SMichael Ellerman * event_id could go on a limited event. 2081f2699491SMichael Ellerman */ 2082f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 2083f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 2084f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 2085f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 2086f2699491SMichael Ellerman /* 2087f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 2088f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 2089f2699491SMichael Ellerman * alternative goes on a normal PMC. 2090f2699491SMichael Ellerman */ 2091f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 2092f2699491SMichael Ellerman if (!ev) 2093f2699491SMichael Ellerman return -EINVAL; 2094f2699491SMichael Ellerman } 2095f2699491SMichael Ellerman } 2096f2699491SMichael Ellerman 2097330a1eb7SMichael Ellerman /* Extra checks for EBB */ 2098330a1eb7SMichael Ellerman err = ebb_event_check(event); 2099330a1eb7SMichael Ellerman if (err) 2100330a1eb7SMichael Ellerman return err; 2101330a1eb7SMichael Ellerman 2102f2699491SMichael Ellerman /* 2103f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 2104f2699491SMichael Ellerman * other hardware events in the group. We assume the event 2105f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 2106f2699491SMichael Ellerman */ 2107f2699491SMichael Ellerman n = 0; 2108f2699491SMichael Ellerman if (event->group_leader != event) { 2109f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 2110f2699491SMichael Ellerman ctrs, events, cflags); 2111f2699491SMichael Ellerman if (n < 0) 2112f2699491SMichael Ellerman return -EINVAL; 2113f2699491SMichael Ellerman } 2114f2699491SMichael Ellerman events[n] = ev; 2115f2699491SMichael Ellerman ctrs[n] = event; 2116f2699491SMichael Ellerman cflags[n] = flags; 2117f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 2118f2699491SMichael Ellerman return -EINVAL; 2119f2699491SMichael Ellerman 2120f66de7acSAthira Rajeev local_irq_save(irq_flags); 2121f66de7acSAthira Rajeev cpuhw = this_cpu_ptr(&cpu_hw_events); 2122f66de7acSAthira Rajeev 212382d2c16bSKajol Jain err = power_check_constraints(cpuhw, events, cflags, n + 1, ctrs); 21243925f46bSAnshuman Khandual 21253925f46bSAnshuman Khandual if (has_branch_stack(event)) { 2126b460b512SAlexey Kardashevskiy u64 bhrb_filter = -1; 2127b460b512SAlexey Kardashevskiy 2128b460b512SAlexey Kardashevskiy if (ppmu->bhrb_filter_map) 21293202e35eSRavi Bangoria bhrb_filter = ppmu->bhrb_filter_map( 21303925f46bSAnshuman Khandual event->attr.branch_sample_type); 21313925f46bSAnshuman Khandual 21323202e35eSRavi Bangoria if (bhrb_filter == -1) { 2133f66de7acSAthira Rajeev local_irq_restore(irq_flags); 21343925f46bSAnshuman Khandual return -EOPNOTSUPP; 21353925f46bSAnshuman Khandual } 21363202e35eSRavi Bangoria cpuhw->bhrb_filter = bhrb_filter; 213768de8867SJan Stancek } 21383925f46bSAnshuman Khandual 2139f66de7acSAthira Rajeev local_irq_restore(irq_flags); 2140f2699491SMichael Ellerman if (err) 2141f2699491SMichael Ellerman return -EINVAL; 2142f2699491SMichael Ellerman 2143f2699491SMichael Ellerman event->hw.config = events[n]; 2144f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 2145f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2146f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 2147f2699491SMichael Ellerman 2148f2699491SMichael Ellerman /* 2149330a1eb7SMichael Ellerman * For EBB events we just context switch the PMC value, we don't do any 2150330a1eb7SMichael Ellerman * of the sample_period logic. We use hw.prev_count for this. 2151330a1eb7SMichael Ellerman */ 2152330a1eb7SMichael Ellerman if (is_ebb_event(event)) 2153330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, 0); 2154330a1eb7SMichael Ellerman 2155330a1eb7SMichael Ellerman /* 2156f2699491SMichael Ellerman * See if we need to reserve the PMU. 2157f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 2158f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 2159f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 2160f2699491SMichael Ellerman */ 2161f2699491SMichael Ellerman err = 0; 2162f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 2163f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 2164f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 2165f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 2166f2699491SMichael Ellerman err = -EBUSY; 2167f2699491SMichael Ellerman else 2168f2699491SMichael Ellerman atomic_inc(&num_events); 2169f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 2170f2699491SMichael Ellerman } 2171f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 2172f2699491SMichael Ellerman 2173f2699491SMichael Ellerman return err; 2174f2699491SMichael Ellerman } 2175f2699491SMichael Ellerman 21765375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 21775375871dSLinus Torvalds { 21785375871dSLinus Torvalds return event->hw.idx; 21795375871dSLinus Torvalds } 21805375871dSLinus Torvalds 21811c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 21821c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 21831c53a270SSukadev Bhattiprolu { 21841c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 21851c53a270SSukadev Bhattiprolu 21861c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 21871c53a270SSukadev Bhattiprolu 21881c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 21891c53a270SSukadev Bhattiprolu } 21901c53a270SSukadev Bhattiprolu 2191e51df2c1SAnton Blanchard static struct pmu power_pmu = { 2192f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 2193f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 2194f2699491SMichael Ellerman .event_init = power_pmu_event_init, 2195f2699491SMichael Ellerman .add = power_pmu_add, 2196f2699491SMichael Ellerman .del = power_pmu_del, 2197f2699491SMichael Ellerman .start = power_pmu_start, 2198f2699491SMichael Ellerman .stop = power_pmu_stop, 2199f2699491SMichael Ellerman .read = power_pmu_read, 2200f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 2201f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 2202f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 22035375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 2204acba3c7eSPeter Zijlstra .sched_task = power_pmu_sched_task, 2205f2699491SMichael Ellerman }; 2206f2699491SMichael Ellerman 22074cb6a42eSKan Liang #define PERF_SAMPLE_ADDR_TYPE (PERF_SAMPLE_ADDR | \ 22084cb6a42eSKan Liang PERF_SAMPLE_PHYS_ADDR | \ 22094cb6a42eSKan Liang PERF_SAMPLE_DATA_PAGE_SIZE) 2210f2699491SMichael Ellerman /* 2211f2699491SMichael Ellerman * A counter has overflowed; update its count and record 2212f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 2213f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 2214f2699491SMichael Ellerman */ 2215f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 2216f2699491SMichael Ellerman struct pt_regs *regs) 2217f2699491SMichael Ellerman { 2218f2699491SMichael Ellerman u64 period = event->hw.sample_period; 2219f2699491SMichael Ellerman s64 prev, delta, left; 2220f2699491SMichael Ellerman int record = 0; 2221f2699491SMichael Ellerman 2222f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 2223f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 2224f2699491SMichael Ellerman return; 2225f2699491SMichael Ellerman } 2226f2699491SMichael Ellerman 2227f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 2228f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 2229f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 2230f2699491SMichael Ellerman local64_add(delta, &event->count); 2231f2699491SMichael Ellerman 2232f2699491SMichael Ellerman /* 2233f2699491SMichael Ellerman * See if the total period for this event has expired, 2234f2699491SMichael Ellerman * and update for the next period. 2235f2699491SMichael Ellerman */ 2236f2699491SMichael Ellerman val = 0; 2237f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 2238e13e895fSMichael Neuling if (delta == 0) 2239e13e895fSMichael Neuling left++; 2240f2699491SMichael Ellerman if (period) { 2241f2699491SMichael Ellerman if (left <= 0) { 2242f2699491SMichael Ellerman left += period; 2243f2699491SMichael Ellerman if (left <= 0) 2244f2699491SMichael Ellerman left = period; 2245d137845cSAthira Rajeev 2246d137845cSAthira Rajeev /* 2247d137845cSAthira Rajeev * If address is not requested in the sample via 2248d137845cSAthira Rajeev * PERF_SAMPLE_IP, just record that sample irrespective 2249d137845cSAthira Rajeev * of SIAR valid check. 2250d137845cSAthira Rajeev */ 2251d137845cSAthira Rajeev if (event->attr.sample_type & PERF_SAMPLE_IP) 2252e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 2253d137845cSAthira Rajeev else 2254d137845cSAthira Rajeev record = 1; 2255d137845cSAthira Rajeev 2256f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2257f2699491SMichael Ellerman } 2258f2699491SMichael Ellerman if (left < 0x80000000LL) 2259f2699491SMichael Ellerman val = 0x80000000LL - left; 2260f2699491SMichael Ellerman } 2261f2699491SMichael Ellerman 2262f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 2263f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 2264f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 2265f2699491SMichael Ellerman perf_event_update_userpage(event); 2266f2699491SMichael Ellerman 2267f2699491SMichael Ellerman /* 2268aa8e21c0SAthira Rajeev * Due to hardware limitation, sometimes SIAR could sample a kernel 2269aa8e21c0SAthira Rajeev * address even when freeze on supervisor state (kernel) is set in 2270aa8e21c0SAthira Rajeev * MMCR2. Check attr.exclude_kernel and address to drop the sample in 2271aa8e21c0SAthira Rajeev * these cases. 2272aa8e21c0SAthira Rajeev */ 2273d137845cSAthira Rajeev if (event->attr.exclude_kernel && 2274d137845cSAthira Rajeev (event->attr.sample_type & PERF_SAMPLE_IP) && 2275d137845cSAthira Rajeev is_kernel_addr(mfspr(SPRN_SIAR))) 2276aa8e21c0SAthira Rajeev record = 0; 2277aa8e21c0SAthira Rajeev 2278aa8e21c0SAthira Rajeev /* 2279f2699491SMichael Ellerman * Finally record data if requested. 2280f2699491SMichael Ellerman */ 2281f2699491SMichael Ellerman if (record) { 2282f2699491SMichael Ellerman struct perf_sample_data data; 2283f2699491SMichael Ellerman 2284fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 2285f2699491SMichael Ellerman 22864cb6a42eSKan Liang if (event->attr.sample_type & PERF_SAMPLE_ADDR_TYPE) 2287da97e184SJoel Fernandes (Google) perf_get_data_addr(event, regs, &data.addr); 2288f2699491SMichael Ellerman 22893925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 22903925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 229169111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 2292da97e184SJoel Fernandes (Google) power_pmu_bhrb_read(event, cpuhw); 22933925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 22943925f46bSAnshuman Khandual } 22953925f46bSAnshuman Khandual 229679e96f8fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && 229779e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src) 229879e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); 229979e96f8fSMadhavan Srinivasan 2300af31fd0cSAthira Rajeev if (event->attr.sample_type & PERF_SAMPLE_WEIGHT_TYPE && 2301170a315fSMadhavan Srinivasan ppmu->get_mem_weight) 2302af31fd0cSAthira Rajeev ppmu->get_mem_weight(&data.weight.full, event->attr.sample_type); 2303170a315fSMadhavan Srinivasan 2304f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 2305f2699491SMichael Ellerman power_pmu_stop(event, 0); 230617899eafSAthira Rajeev } else if (period) { 230717899eafSAthira Rajeev /* Account for interrupt in case of invalid SIAR */ 230817899eafSAthira Rajeev if (perf_event_account_interrupt(event)) 230917899eafSAthira Rajeev power_pmu_stop(event, 0); 2310f2699491SMichael Ellerman } 2311f2699491SMichael Ellerman } 2312f2699491SMichael Ellerman 2313f2699491SMichael Ellerman /* 2314f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 2315f2699491SMichael Ellerman * for an event_id. 2316f2699491SMichael Ellerman */ 2317f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 2318f2699491SMichael Ellerman { 2319f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 2320f2699491SMichael Ellerman 2321f2699491SMichael Ellerman if (flags) 2322f2699491SMichael Ellerman return flags; 2323f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 2324f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 2325f2699491SMichael Ellerman } 2326f2699491SMichael Ellerman 2327f2699491SMichael Ellerman /* 2328f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 2329f2699491SMichael Ellerman * for an event_id. 2330f2699491SMichael Ellerman */ 2331f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 2332f2699491SMichael Ellerman { 23332ca13a4cSMadhavan Srinivasan unsigned long siar = mfspr(SPRN_SIAR); 2334f2699491SMichael Ellerman 23353c69a5f2SKajol Jain if (regs_use_siar(regs) && siar_valid(regs) && siar) 2336b1643084SKajol Jain return siar + perf_ip_adjust(regs); 233775382aa7SAnton Blanchard else 233875382aa7SAnton Blanchard return regs->nip; 2339f2699491SMichael Ellerman } 2340f2699491SMichael Ellerman 2341bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 2342f2699491SMichael Ellerman { 2343f2699491SMichael Ellerman /* 2344f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 2345f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 2346f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 2347f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 2348f2699491SMichael Ellerman * cycles from overflow. 2349f2699491SMichael Ellerman * 2350f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 2351f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 2352f2699491SMichael Ellerman * don't want to mistakenly reset them. 2353f2699491SMichael Ellerman */ 2354bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 2355bc09c219SMichael Neuling return true; 2356bc09c219SMichael Neuling 2357bc09c219SMichael Neuling return false; 2358bc09c219SMichael Neuling } 2359bc09c219SMichael Neuling 2360bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 2361bc09c219SMichael Neuling { 2362bc09c219SMichael Neuling if ((int)val < 0) 2363f2699491SMichael Ellerman return true; 2364f2699491SMichael Ellerman 2365f2699491SMichael Ellerman return false; 2366f2699491SMichael Ellerman } 2367f2699491SMichael Ellerman 2368f2699491SMichael Ellerman /* 2369f2699491SMichael Ellerman * Performance monitor interrupt stuff 2370f2699491SMichael Ellerman */ 23710c9108b0SRavi Bangoria static void __perf_event_interrupt(struct pt_regs *regs) 2372f2699491SMichael Ellerman { 2373bc09c219SMichael Neuling int i, j; 237469111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2375f2699491SMichael Ellerman struct perf_event *event; 2376bc09c219SMichael Neuling int found, active; 2377f2699491SMichael Ellerman 2378f2699491SMichael Ellerman if (cpuhw->n_limited) 2379f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2380f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 2381f2699491SMichael Ellerman 2382f2699491SMichael Ellerman perf_read_regs(regs); 2383f2699491SMichael Ellerman 2384bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 2385bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 238691f3469aSAthira Rajeev cpuhw->pmcs[i] = read_pmc(i + 1); 2387bc09c219SMichael Neuling 2388bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 2389bc09c219SMichael Neuling found = 0; 2390bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 239191f3469aSAthira Rajeev if (!pmc_overflow(cpuhw->pmcs[i])) 2392bc09c219SMichael Neuling continue; 2393bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 2394bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 2395bc09c219SMichael Neuling /* 2396bc09c219SMichael Neuling * We've found one that's overflowed. For active 2397bc09c219SMichael Neuling * counters we need to log this. For inactive 2398bc09c219SMichael Neuling * counters, we need to reset it anyway 2399bc09c219SMichael Neuling */ 2400bc09c219SMichael Neuling found = 1; 2401bc09c219SMichael Neuling active = 0; 2402bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 2403bc09c219SMichael Neuling event = cpuhw->event[j]; 2404bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 2405bc09c219SMichael Neuling active = 1; 240691f3469aSAthira Rajeev record_and_restart(event, cpuhw->pmcs[i], regs); 2407bc09c219SMichael Neuling break; 2408bc09c219SMichael Neuling } 2409bc09c219SMichael Neuling } 24102c9ac51bSAthira Rajeev 24112c9ac51bSAthira Rajeev /* 24122c9ac51bSAthira Rajeev * Clear PACA_IRQ_PMI in case it was set by 24132c9ac51bSAthira Rajeev * set_pmi_irq_pending() when PMU was enabled 24142c9ac51bSAthira Rajeev * after accounting for interrupts. 24152c9ac51bSAthira Rajeev */ 24162c9ac51bSAthira Rajeev clear_pmi_irq_pending(); 24172c9ac51bSAthira Rajeev 2418bc09c219SMichael Neuling if (!active) 2419bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 2420bc09c219SMichael Neuling write_pmc(i + 1, 0); 2421bc09c219SMichael Neuling } 2422bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 2423bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 2424f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 2425f2699491SMichael Ellerman event = cpuhw->event[i]; 2426f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2427f2699491SMichael Ellerman continue; 242891f3469aSAthira Rajeev if (pmc_overflow_power7(cpuhw->pmcs[event->hw.idx - 1])) { 2429bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 2430f2699491SMichael Ellerman found = 1; 2431bc09c219SMichael Neuling record_and_restart(event, 243291f3469aSAthira Rajeev cpuhw->pmcs[event->hw.idx - 1], 2433bc09c219SMichael Neuling regs); 2434f2699491SMichael Ellerman } 2435f2699491SMichael Ellerman } 2436f2699491SMichael Ellerman } 24372c9ac51bSAthira Rajeev 24382c9ac51bSAthira Rajeev /* 24392c9ac51bSAthira Rajeev * During system wide profling or while specific CPU is monitored for an 24402c9ac51bSAthira Rajeev * event, some corner cases could cause PMC to overflow in idle path. This 24412c9ac51bSAthira Rajeev * will trigger a PMI after waking up from idle. Since counter values are _not_ 24422c9ac51bSAthira Rajeev * saved/restored in idle path, can lead to below "Can't find PMC" message. 24432c9ac51bSAthira Rajeev */ 2444156b5371SNicholas Piggin if (unlikely(!found) && !arch_irq_disabled_regs(regs)) 2445156b5371SNicholas Piggin printk_ratelimited(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2446f2699491SMichael Ellerman 2447f2699491SMichael Ellerman /* 2448f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 2449f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2450f2699491SMichael Ellerman * and thus allow interrupts to occur again. 2451f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 2452f2699491SMichael Ellerman * we get back out of this interrupt. 2453f2699491SMichael Ellerman */ 245478d76819SAthira Rajeev write_mmcr0(cpuhw, cpuhw->mmcr.mmcr0); 2455f2699491SMichael Ellerman 245691f3469aSAthira Rajeev /* Clear the cpuhw->pmcs */ 245791f3469aSAthira Rajeev memset(&cpuhw->pmcs, 0, sizeof(cpuhw->pmcs)); 245891f3469aSAthira Rajeev 2459f2699491SMichael Ellerman } 2460f2699491SMichael Ellerman 24610c9108b0SRavi Bangoria static void perf_event_interrupt(struct pt_regs *regs) 24620c9108b0SRavi Bangoria { 24630c9108b0SRavi Bangoria u64 start_clock = sched_clock(); 24640c9108b0SRavi Bangoria 24650c9108b0SRavi Bangoria __perf_event_interrupt(regs); 24660c9108b0SRavi Bangoria perf_sample_event_took(sched_clock() - start_clock); 24670c9108b0SRavi Bangoria } 24680c9108b0SRavi Bangoria 24697c98bd72SDaniel Axtens static int power_pmu_prepare_cpu(unsigned int cpu) 2470f2699491SMichael Ellerman { 2471f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2472f2699491SMichael Ellerman 247357ecde42SThomas Gleixner if (ppmu) { 2474f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 247578d76819SAthira Rajeev cpuhw->mmcr.mmcr0 = MMCR0_FC; 2476f2699491SMichael Ellerman } 247757ecde42SThomas Gleixner return 0; 2478f2699491SMichael Ellerman } 2479f2699491SMichael Ellerman 2480c49f5d88SNick Child int __init register_power_pmu(struct power_pmu *pmu) 2481f2699491SMichael Ellerman { 2482f2699491SMichael Ellerman if (ppmu) 2483f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 2484f2699491SMichael Ellerman 2485f2699491SMichael Ellerman ppmu = pmu; 2486f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 2487f2699491SMichael Ellerman pmu->name); 2488f2699491SMichael Ellerman 24891c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 2490781fa481SAnju T Sudhakar power_pmu.capabilities |= (ppmu->capabilities & PERF_PMU_CAP_EXTENDED_REGS); 24911c53a270SSukadev Bhattiprolu 2492f2699491SMichael Ellerman #ifdef MSR_HV 2493f2699491SMichael Ellerman /* 2494f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 2495f2699491SMichael Ellerman */ 2496f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 2497f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 2498f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 2499f2699491SMichael Ellerman 2500f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 250173c1b41eSThomas Gleixner cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", 250257ecde42SThomas Gleixner power_pmu_prepare_cpu, NULL); 2503f2699491SMichael Ellerman return 0; 2504f2699491SMichael Ellerman } 2505708597daSMadhavan Srinivasan 2506708597daSMadhavan Srinivasan #ifdef CONFIG_PPC64 25070a4b4327SNicholas Piggin static bool pmu_override = false; 25080a4b4327SNicholas Piggin static unsigned long pmu_override_val; 25090a4b4327SNicholas Piggin static void do_pmu_override(void *data) 25100a4b4327SNicholas Piggin { 25110a4b4327SNicholas Piggin ppc_set_pmu_inuse(1); 25120a4b4327SNicholas Piggin if (pmu_override_val) 25130a4b4327SNicholas Piggin mtspr(SPRN_MMCR1, pmu_override_val); 25140a4b4327SNicholas Piggin mtspr(SPRN_MMCR0, mfspr(SPRN_MMCR0) & ~MMCR0_FC); 25150a4b4327SNicholas Piggin } 25160a4b4327SNicholas Piggin 2517708597daSMadhavan Srinivasan static int __init init_ppc64_pmu(void) 2518708597daSMadhavan Srinivasan { 25190a4b4327SNicholas Piggin if (cpu_has_feature(CPU_FTR_HVMODE) && pmu_override) { 25200a4b4327SNicholas Piggin pr_warn("disabling perf due to pmu_override= command line option.\n"); 25210a4b4327SNicholas Piggin on_each_cpu(do_pmu_override, NULL, 1); 25220a4b4327SNicholas Piggin return 0; 25230a4b4327SNicholas Piggin } 25240a4b4327SNicholas Piggin 2525708597daSMadhavan Srinivasan /* run through all the pmu drivers one at a time */ 2526708597daSMadhavan Srinivasan if (!init_power5_pmu()) 2527708597daSMadhavan Srinivasan return 0; 2528708597daSMadhavan Srinivasan else if (!init_power5p_pmu()) 2529708597daSMadhavan Srinivasan return 0; 2530708597daSMadhavan Srinivasan else if (!init_power6_pmu()) 2531708597daSMadhavan Srinivasan return 0; 2532708597daSMadhavan Srinivasan else if (!init_power7_pmu()) 2533708597daSMadhavan Srinivasan return 0; 2534708597daSMadhavan Srinivasan else if (!init_power8_pmu()) 2535708597daSMadhavan Srinivasan return 0; 2536708597daSMadhavan Srinivasan else if (!init_power9_pmu()) 2537708597daSMadhavan Srinivasan return 0; 2538a64e697cSAthira Rajeev else if (!init_power10_pmu()) 2539a64e697cSAthira Rajeev return 0; 2540708597daSMadhavan Srinivasan else if (!init_ppc970_pmu()) 2541708597daSMadhavan Srinivasan return 0; 2542708597daSMadhavan Srinivasan else 2543be80e758SMadhavan Srinivasan return init_generic_compat_pmu(); 2544708597daSMadhavan Srinivasan } 2545708597daSMadhavan Srinivasan early_initcall(init_ppc64_pmu); 25460a4b4327SNicholas Piggin 25470a4b4327SNicholas Piggin static int __init pmu_setup(char *str) 25480a4b4327SNicholas Piggin { 25490a4b4327SNicholas Piggin unsigned long val; 25500a4b4327SNicholas Piggin 25510a4b4327SNicholas Piggin if (!early_cpu_has_feature(CPU_FTR_HVMODE)) 25520a4b4327SNicholas Piggin return 0; 25530a4b4327SNicholas Piggin 25540a4b4327SNicholas Piggin pmu_override = true; 25550a4b4327SNicholas Piggin 25560a4b4327SNicholas Piggin if (kstrtoul(str, 0, &val)) 25570a4b4327SNicholas Piggin val = 0; 25580a4b4327SNicholas Piggin 25590a4b4327SNicholas Piggin pmu_override_val = val; 25600a4b4327SNicholas Piggin 25610a4b4327SNicholas Piggin return 1; 25620a4b4327SNicholas Piggin } 25630a4b4327SNicholas Piggin __setup("pmu_override=", pmu_setup); 25640a4b4327SNicholas Piggin 2565708597daSMadhavan Srinivasan #endif 2566