1f2699491SMichael Ellerman /* 2f2699491SMichael Ellerman * Performance event support - powerpc architecture code 3f2699491SMichael Ellerman * 4f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5f2699491SMichael Ellerman * 6f2699491SMichael Ellerman * This program is free software; you can redistribute it and/or 7f2699491SMichael Ellerman * modify it under the terms of the GNU General Public License 8f2699491SMichael Ellerman * as published by the Free Software Foundation; either version 9f2699491SMichael Ellerman * 2 of the License, or (at your option) any later version. 10f2699491SMichael Ellerman */ 11f2699491SMichael Ellerman #include <linux/kernel.h> 12f2699491SMichael Ellerman #include <linux/sched.h> 13f2699491SMichael Ellerman #include <linux/perf_event.h> 14f2699491SMichael Ellerman #include <linux/percpu.h> 15f2699491SMichael Ellerman #include <linux/hardirq.h> 16f2699491SMichael Ellerman #include <asm/reg.h> 17f2699491SMichael Ellerman #include <asm/pmc.h> 18f2699491SMichael Ellerman #include <asm/machdep.h> 19f2699491SMichael Ellerman #include <asm/firmware.h> 20f2699491SMichael Ellerman #include <asm/ptrace.h> 21f2699491SMichael Ellerman 223925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 233925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 243925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 253925f46bSAnshuman Khandual #define BHRB_EA 0xFFFFFFFFFFFFFFFC 263925f46bSAnshuman Khandual 27f2699491SMichael Ellerman struct cpu_hw_events { 28f2699491SMichael Ellerman int n_events; 29f2699491SMichael Ellerman int n_percpu; 30f2699491SMichael Ellerman int disabled; 31f2699491SMichael Ellerman int n_added; 32f2699491SMichael Ellerman int n_limited; 33f2699491SMichael Ellerman u8 pmcs_enabled; 34f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 35f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 36f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 37f2699491SMichael Ellerman unsigned long mmcr[3]; 38f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 39f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 40f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 41f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 42f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 43f2699491SMichael Ellerman 44f2699491SMichael Ellerman unsigned int group_flag; 45f2699491SMichael Ellerman int n_txn_start; 463925f46bSAnshuman Khandual 473925f46bSAnshuman Khandual /* BHRB bits */ 483925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 493925f46bSAnshuman Khandual int bhrb_users; 503925f46bSAnshuman Khandual void *bhrb_context; 513925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 523925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 53f2699491SMichael Ellerman }; 543925f46bSAnshuman Khandual 55f2699491SMichael Ellerman DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 56f2699491SMichael Ellerman 57f2699491SMichael Ellerman struct power_pmu *ppmu; 58f2699491SMichael Ellerman 59f2699491SMichael Ellerman /* 60f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 61f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 62f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 63f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 64f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 65f2699491SMichael Ellerman */ 66f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 67f2699491SMichael Ellerman 68f2699491SMichael Ellerman /* 69f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 70f2699491SMichael Ellerman * and a few other names are different. 71f2699491SMichael Ellerman */ 72f2699491SMichael Ellerman #ifdef CONFIG_PPC32 73f2699491SMichael Ellerman 74f2699491SMichael Ellerman #define MMCR0_FCHV 0 75f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 76f2699491SMichael Ellerman 77f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 78f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 79f2699491SMichael Ellerman 80f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 81f2699491SMichael Ellerman { 82f2699491SMichael Ellerman return 0; 83f2699491SMichael Ellerman } 84f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 85f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 86f2699491SMichael Ellerman { 87f2699491SMichael Ellerman return 0; 88f2699491SMichael Ellerman } 8975382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 9075382aa7SAnton Blanchard { 9175382aa7SAnton Blanchard regs->result = 0; 9275382aa7SAnton Blanchard } 93f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 94f2699491SMichael Ellerman { 95f2699491SMichael Ellerman return 0; 96f2699491SMichael Ellerman } 97f2699491SMichael Ellerman 98e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 99e6878835Ssukadev@linux.vnet.ibm.com { 100e6878835Ssukadev@linux.vnet.ibm.com return 1; 101e6878835Ssukadev@linux.vnet.ibm.com } 102e6878835Ssukadev@linux.vnet.ibm.com 103f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 104f2699491SMichael Ellerman 10533904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 10633904054SMichael Ellerman { 10733904054SMichael Ellerman return !!(regs->result & 1); 10833904054SMichael Ellerman } 10933904054SMichael Ellerman 110f2699491SMichael Ellerman /* 111f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 112f2699491SMichael Ellerman */ 113f2699491SMichael Ellerman #ifdef CONFIG_PPC64 114f2699491SMichael Ellerman 115f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 116f2699491SMichael Ellerman { 117f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 118f2699491SMichael Ellerman 1197a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 120f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 121f2699491SMichael Ellerman if (slot > 1) 122f2699491SMichael Ellerman return 4 * (slot - 1); 123f2699491SMichael Ellerman } 1247a786832SMichael Ellerman 125f2699491SMichael Ellerman return 0; 126f2699491SMichael Ellerman } 127f2699491SMichael Ellerman 128f2699491SMichael Ellerman /* 129f2699491SMichael Ellerman * The user wants a data address recorded. 130f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 131f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 132f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 133e6878835Ssukadev@linux.vnet.ibm.com * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC or 134e6878835Ssukadev@linux.vnet.ibm.com * the [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA. 135f2699491SMichael Ellerman */ 136f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 137f2699491SMichael Ellerman { 138f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 139e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 140e6878835Ssukadev@linux.vnet.ibm.com 141e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 142e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 143e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 144e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 145e6878835Ssukadev@linux.vnet.ibm.com else 146e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 147f2699491SMichael Ellerman 148f2699491SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || (mmcra & sdsync)) 149f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 150f2699491SMichael Ellerman } 151f2699491SMichael Ellerman 1525682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 15368b30bb9SAnton Blanchard { 15468b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 15568b30bb9SAnton Blanchard 1568f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 1578f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 1588f61aa32SMichael Ellerman 15968b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 16068b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 16168b30bb9SAnton Blanchard 1625682c460SMichael Ellerman return !!(regs->dsisr & sihv); 16368b30bb9SAnton Blanchard } 16468b30bb9SAnton Blanchard 1655682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 16668b30bb9SAnton Blanchard { 16768b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 16868b30bb9SAnton Blanchard 1698f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 1708f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 1718f61aa32SMichael Ellerman 17268b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 17368b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 17468b30bb9SAnton Blanchard 1755682c460SMichael Ellerman return !!(regs->dsisr & sipr); 17668b30bb9SAnton Blanchard } 17768b30bb9SAnton Blanchard 178860aad71SMichael Ellerman static bool regs_no_sipr(struct pt_regs *regs) 179860aad71SMichael Ellerman { 180860aad71SMichael Ellerman return !!(regs->result & 2); 181860aad71SMichael Ellerman } 182860aad71SMichael Ellerman 1831ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 1841ce447b9SBenjamin Herrenschmidt { 1851ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 1861ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 1871ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 1881ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 1891ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 1901ce447b9SBenjamin Herrenschmidt } 1911ce447b9SBenjamin Herrenschmidt 192f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 193f2699491SMichael Ellerman { 19433904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 195f2699491SMichael Ellerman 19675382aa7SAnton Blanchard if (!use_siar) 1971ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 1981ce447b9SBenjamin Herrenschmidt 1991ce447b9SBenjamin Herrenschmidt /* 2001ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2011ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2021ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2031ce447b9SBenjamin Herrenschmidt * results 2041ce447b9SBenjamin Herrenschmidt */ 205860aad71SMichael Ellerman if (regs_no_sipr(regs)) { 2061ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 2071ce447b9SBenjamin Herrenschmidt if (siar >= PAGE_OFFSET) 2081ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2091ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2101ce447b9SBenjamin Herrenschmidt } 211f2699491SMichael Ellerman 212f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 2135682c460SMichael Ellerman if (regs_sipr(regs)) 214f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 2155682c460SMichael Ellerman 2165682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 217f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 2185682c460SMichael Ellerman 219f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 220f2699491SMichael Ellerman } 221f2699491SMichael Ellerman 222f2699491SMichael Ellerman /* 223f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 224f2699491SMichael Ellerman * on each interrupt. 2258f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 22675382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 22775382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 228f2699491SMichael Ellerman */ 229f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 230f2699491SMichael Ellerman { 23175382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 23275382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 23375382aa7SAnton Blanchard int use_siar; 23475382aa7SAnton Blanchard 2355682c460SMichael Ellerman regs->dsisr = mmcra; 236860aad71SMichael Ellerman regs->result = 0; 237860aad71SMichael Ellerman 238860aad71SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) 239860aad71SMichael Ellerman regs->result |= 2; 2405682c460SMichael Ellerman 2415c093efaSAnton Blanchard /* 2428f61aa32SMichael Ellerman * On power8 if we're in random sampling mode, the SIER is updated. 2438f61aa32SMichael Ellerman * If we're in continuous sampling mode, we don't have SIPR. 2448f61aa32SMichael Ellerman */ 2458f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) { 2468f61aa32SMichael Ellerman if (marked) 2478f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 2488f61aa32SMichael Ellerman else 2498f61aa32SMichael Ellerman regs->result |= 2; 2508f61aa32SMichael Ellerman } 2518f61aa32SMichael Ellerman 2528f61aa32SMichael Ellerman 2538f61aa32SMichael Ellerman /* 2545c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 2555c093efaSAnton Blanchard * not valid. Use pt_regs. 2565c093efaSAnton Blanchard * 2575c093efaSAnton Blanchard * If it is a marked event use the SIAR. 2585c093efaSAnton Blanchard * 2595c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 2605c093efaSAnton Blanchard * pt_regs. 2615c093efaSAnton Blanchard * 2625c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 2635c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 2645c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 2655c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 2665c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 2675c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 2685c093efaSAnton Blanchard * interrupts off hence the userspace check. 2695c093efaSAnton Blanchard */ 27075382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 27175382aa7SAnton Blanchard use_siar = 0; 2725c093efaSAnton Blanchard else if (marked) 2735c093efaSAnton Blanchard use_siar = 1; 2745c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 2755c093efaSAnton Blanchard use_siar = 0; 276860aad71SMichael Ellerman else if (!regs_no_sipr(regs) && regs_sipr(regs)) 27775382aa7SAnton Blanchard use_siar = 0; 27875382aa7SAnton Blanchard else 27975382aa7SAnton Blanchard use_siar = 1; 28075382aa7SAnton Blanchard 281860aad71SMichael Ellerman regs->result |= use_siar; 282f2699491SMichael Ellerman } 283f2699491SMichael Ellerman 284f2699491SMichael Ellerman /* 285f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 286f2699491SMichael Ellerman * it as an NMI. 287f2699491SMichael Ellerman */ 288f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 289f2699491SMichael Ellerman { 290f2699491SMichael Ellerman return !regs->softe; 291f2699491SMichael Ellerman } 292f2699491SMichael Ellerman 293e6878835Ssukadev@linux.vnet.ibm.com /* 294e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 295e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 296e6878835Ssukadev@linux.vnet.ibm.com * 297e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 298e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 299e6878835Ssukadev@linux.vnet.ibm.com */ 300e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 301e6878835Ssukadev@linux.vnet.ibm.com { 302e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 303e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 304e6878835Ssukadev@linux.vnet.ibm.com 305e6878835Ssukadev@linux.vnet.ibm.com if ((ppmu->flags & PPMU_SIAR_VALID) && marked) 306e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 307e6878835Ssukadev@linux.vnet.ibm.com 308e6878835Ssukadev@linux.vnet.ibm.com return 1; 309e6878835Ssukadev@linux.vnet.ibm.com } 310e6878835Ssukadev@linux.vnet.ibm.com 311f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 312f2699491SMichael Ellerman 313f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 314f2699491SMichael Ellerman 315f2699491SMichael Ellerman void perf_event_print_debug(void) 316f2699491SMichael Ellerman { 317f2699491SMichael Ellerman } 318f2699491SMichael Ellerman 319f2699491SMichael Ellerman /* 320f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 321f2699491SMichael Ellerman */ 322f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 323f2699491SMichael Ellerman { 324f2699491SMichael Ellerman unsigned long val; 325f2699491SMichael Ellerman 326f2699491SMichael Ellerman switch (idx) { 327f2699491SMichael Ellerman case 1: 328f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 329f2699491SMichael Ellerman break; 330f2699491SMichael Ellerman case 2: 331f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 332f2699491SMichael Ellerman break; 333f2699491SMichael Ellerman case 3: 334f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 335f2699491SMichael Ellerman break; 336f2699491SMichael Ellerman case 4: 337f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 338f2699491SMichael Ellerman break; 339f2699491SMichael Ellerman case 5: 340f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 341f2699491SMichael Ellerman break; 342f2699491SMichael Ellerman case 6: 343f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 344f2699491SMichael Ellerman break; 345f2699491SMichael Ellerman #ifdef CONFIG_PPC64 346f2699491SMichael Ellerman case 7: 347f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 348f2699491SMichael Ellerman break; 349f2699491SMichael Ellerman case 8: 350f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 351f2699491SMichael Ellerman break; 352f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 353f2699491SMichael Ellerman default: 354f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 355f2699491SMichael Ellerman val = 0; 356f2699491SMichael Ellerman } 357f2699491SMichael Ellerman return val; 358f2699491SMichael Ellerman } 359f2699491SMichael Ellerman 360f2699491SMichael Ellerman /* 361f2699491SMichael Ellerman * Write one PMC. 362f2699491SMichael Ellerman */ 363f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 364f2699491SMichael Ellerman { 365f2699491SMichael Ellerman switch (idx) { 366f2699491SMichael Ellerman case 1: 367f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 368f2699491SMichael Ellerman break; 369f2699491SMichael Ellerman case 2: 370f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 371f2699491SMichael Ellerman break; 372f2699491SMichael Ellerman case 3: 373f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 374f2699491SMichael Ellerman break; 375f2699491SMichael Ellerman case 4: 376f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 377f2699491SMichael Ellerman break; 378f2699491SMichael Ellerman case 5: 379f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 380f2699491SMichael Ellerman break; 381f2699491SMichael Ellerman case 6: 382f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 383f2699491SMichael Ellerman break; 384f2699491SMichael Ellerman #ifdef CONFIG_PPC64 385f2699491SMichael Ellerman case 7: 386f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 387f2699491SMichael Ellerman break; 388f2699491SMichael Ellerman case 8: 389f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 390f2699491SMichael Ellerman break; 391f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 392f2699491SMichael Ellerman default: 393f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 394f2699491SMichael Ellerman } 395f2699491SMichael Ellerman } 396f2699491SMichael Ellerman 397f2699491SMichael Ellerman /* 398f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 399f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 400f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 401f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 402f2699491SMichael Ellerman */ 403f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 404f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 405f2699491SMichael Ellerman int n_ev) 406f2699491SMichael Ellerman { 407f2699491SMichael Ellerman unsigned long mask, value, nv; 408f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 409f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 410f2699491SMichael Ellerman int i, j; 411f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 412f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 413f2699491SMichael Ellerman 414f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 415f2699491SMichael Ellerman return -1; 416f2699491SMichael Ellerman 417f2699491SMichael Ellerman /* First see if the events will go on as-is */ 418f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 419f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 420f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 421f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 422f2699491SMichael Ellerman cpuhw->alternatives[i]); 423f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 424f2699491SMichael Ellerman } 425f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 426f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 427f2699491SMichael Ellerman return -1; 428f2699491SMichael Ellerman } 429f2699491SMichael Ellerman value = mask = 0; 430f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 431f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 432f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 433f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) != 0 || 434f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][0]) & 435f2699491SMichael Ellerman cpuhw->amasks[i][0]) != 0) 436f2699491SMichael Ellerman break; 437f2699491SMichael Ellerman value = nv; 438f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 439f2699491SMichael Ellerman } 440f2699491SMichael Ellerman if (i == n_ev) 441f2699491SMichael Ellerman return 0; /* all OK */ 442f2699491SMichael Ellerman 443f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 444f2699491SMichael Ellerman if (!ppmu->get_alternatives) 445f2699491SMichael Ellerman return -1; 446f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 447f2699491SMichael Ellerman choice[i] = 0; 448f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 449f2699491SMichael Ellerman cpuhw->alternatives[i]); 450f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 451f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 452f2699491SMichael Ellerman &cpuhw->amasks[i][j], 453f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 454f2699491SMichael Ellerman } 455f2699491SMichael Ellerman 456f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 457f2699491SMichael Ellerman i = 0; 458f2699491SMichael Ellerman j = -1; 459f2699491SMichael Ellerman value = mask = nv = 0; 460f2699491SMichael Ellerman while (i < n_ev) { 461f2699491SMichael Ellerman if (j >= 0) { 462f2699491SMichael Ellerman /* we're backtracking, restore context */ 463f2699491SMichael Ellerman value = svalues[i]; 464f2699491SMichael Ellerman mask = smasks[i]; 465f2699491SMichael Ellerman j = choice[i]; 466f2699491SMichael Ellerman } 467f2699491SMichael Ellerman /* 468f2699491SMichael Ellerman * See if any alternative k for event_id i, 469f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 470f2699491SMichael Ellerman */ 471f2699491SMichael Ellerman while (++j < n_alt[i]) { 472f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 473f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 474f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 475f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 476f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 477f2699491SMichael Ellerman break; 478f2699491SMichael Ellerman } 479f2699491SMichael Ellerman if (j >= n_alt[i]) { 480f2699491SMichael Ellerman /* 481f2699491SMichael Ellerman * No feasible alternative, backtrack 482f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 483f2699491SMichael Ellerman * alternatives from where we got up to. 484f2699491SMichael Ellerman */ 485f2699491SMichael Ellerman if (--i < 0) 486f2699491SMichael Ellerman return -1; 487f2699491SMichael Ellerman } else { 488f2699491SMichael Ellerman /* 489f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 490f2699491SMichael Ellerman * remember where we got up to with this event_id, 491f2699491SMichael Ellerman * go on to the next event_id, and start with 492f2699491SMichael Ellerman * the first alternative for it. 493f2699491SMichael Ellerman */ 494f2699491SMichael Ellerman choice[i] = j; 495f2699491SMichael Ellerman svalues[i] = value; 496f2699491SMichael Ellerman smasks[i] = mask; 497f2699491SMichael Ellerman value = nv; 498f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 499f2699491SMichael Ellerman ++i; 500f2699491SMichael Ellerman j = -1; 501f2699491SMichael Ellerman } 502f2699491SMichael Ellerman } 503f2699491SMichael Ellerman 504f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 505f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 506f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 507f2699491SMichael Ellerman return 0; 508f2699491SMichael Ellerman } 509f2699491SMichael Ellerman 510f2699491SMichael Ellerman /* 511f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 512f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 513f2699491SMichael Ellerman * added events. 514f2699491SMichael Ellerman */ 515f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 516f2699491SMichael Ellerman int n_prev, int n_new) 517f2699491SMichael Ellerman { 518f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 519f2699491SMichael Ellerman int i, n, first; 520f2699491SMichael Ellerman struct perf_event *event; 521f2699491SMichael Ellerman 522f2699491SMichael Ellerman n = n_prev + n_new; 523f2699491SMichael Ellerman if (n <= 1) 524f2699491SMichael Ellerman return 0; 525f2699491SMichael Ellerman 526f2699491SMichael Ellerman first = 1; 527f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 528f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 529f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 530f2699491SMichael Ellerman continue; 531f2699491SMichael Ellerman } 532f2699491SMichael Ellerman event = ctrs[i]; 533f2699491SMichael Ellerman if (first) { 534f2699491SMichael Ellerman eu = event->attr.exclude_user; 535f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 536f2699491SMichael Ellerman eh = event->attr.exclude_hv; 537f2699491SMichael Ellerman first = 0; 538f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 539f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 540f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 541f2699491SMichael Ellerman return -EAGAIN; 542f2699491SMichael Ellerman } 543f2699491SMichael Ellerman } 544f2699491SMichael Ellerman 545f2699491SMichael Ellerman if (eu || ek || eh) 546f2699491SMichael Ellerman for (i = 0; i < n; ++i) 547f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 548f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 549f2699491SMichael Ellerman 550f2699491SMichael Ellerman return 0; 551f2699491SMichael Ellerman } 552f2699491SMichael Ellerman 553f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 554f2699491SMichael Ellerman { 555f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 556f2699491SMichael Ellerman 557f2699491SMichael Ellerman /* 558f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 559f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 560f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 561f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 562f2699491SMichael Ellerman * number of events to rollback at once. If we dectect a rollback 563f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 564f2699491SMichael Ellerman * counters. 565f2699491SMichael Ellerman */ 566f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 567f2699491SMichael Ellerman delta = 0; 568f2699491SMichael Ellerman 569f2699491SMichael Ellerman return delta; 570f2699491SMichael Ellerman } 571f2699491SMichael Ellerman 572f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 573f2699491SMichael Ellerman { 574f2699491SMichael Ellerman s64 val, delta, prev; 575f2699491SMichael Ellerman 576f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 577f2699491SMichael Ellerman return; 578f2699491SMichael Ellerman 579f2699491SMichael Ellerman if (!event->hw.idx) 580f2699491SMichael Ellerman return; 581f2699491SMichael Ellerman /* 582f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 583f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 584f2699491SMichael Ellerman * Therefore we treat them like NMIs. 585f2699491SMichael Ellerman */ 586f2699491SMichael Ellerman do { 587f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 588f2699491SMichael Ellerman barrier(); 589f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 590f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 591f2699491SMichael Ellerman if (!delta) 592f2699491SMichael Ellerman return; 593f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 594f2699491SMichael Ellerman 595f2699491SMichael Ellerman local64_add(delta, &event->count); 596f2699491SMichael Ellerman local64_sub(delta, &event->hw.period_left); 597f2699491SMichael Ellerman } 598f2699491SMichael Ellerman 599f2699491SMichael Ellerman /* 600f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 601f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 602f2699491SMichael Ellerman * us if `event' is using such a PMC. 603f2699491SMichael Ellerman */ 604f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 605f2699491SMichael Ellerman { 606f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 607f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 608f2699491SMichael Ellerman } 609f2699491SMichael Ellerman 610f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 611f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 612f2699491SMichael Ellerman { 613f2699491SMichael Ellerman struct perf_event *event; 614f2699491SMichael Ellerman u64 val, prev, delta; 615f2699491SMichael Ellerman int i; 616f2699491SMichael Ellerman 617f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 618f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 619f2699491SMichael Ellerman if (!event->hw.idx) 620f2699491SMichael Ellerman continue; 621f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 622f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 623f2699491SMichael Ellerman event->hw.idx = 0; 624f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 625f2699491SMichael Ellerman if (delta) 626f2699491SMichael Ellerman local64_add(delta, &event->count); 627f2699491SMichael Ellerman } 628f2699491SMichael Ellerman } 629f2699491SMichael Ellerman 630f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 631f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 632f2699491SMichael Ellerman { 633f2699491SMichael Ellerman struct perf_event *event; 634f2699491SMichael Ellerman u64 val, prev; 635f2699491SMichael Ellerman int i; 636f2699491SMichael Ellerman 637f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 638f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 639f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 640f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 641f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 642f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 643f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 644f2699491SMichael Ellerman perf_event_update_userpage(event); 645f2699491SMichael Ellerman } 646f2699491SMichael Ellerman } 647f2699491SMichael Ellerman 648f2699491SMichael Ellerman /* 649f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 650f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 651f2699491SMichael Ellerman * other events. We try to keep the values from the limited 652f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 653f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 654f2699491SMichael Ellerman * the limited events as small and consistent as possible. 655f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 656f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 657f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 658f2699491SMichael Ellerman */ 659f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 660f2699491SMichael Ellerman { 661f2699491SMichael Ellerman unsigned long pmc5, pmc6; 662f2699491SMichael Ellerman 663f2699491SMichael Ellerman if (!cpuhw->n_limited) { 664f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 665f2699491SMichael Ellerman return; 666f2699491SMichael Ellerman } 667f2699491SMichael Ellerman 668f2699491SMichael Ellerman /* 669f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 670f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 671f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 672f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 673f2699491SMichael Ellerman * interrupt enable bits turned off. 674f2699491SMichael Ellerman */ 675f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 676f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 677f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 678f2699491SMichael Ellerman "i" (SPRN_MMCR0), 679f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 680f2699491SMichael Ellerman 681f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 682f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 683f2699491SMichael Ellerman else 684f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 685f2699491SMichael Ellerman 686f2699491SMichael Ellerman /* 687f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 688f2699491SMichael Ellerman * enable bits, if necessary. 689f2699491SMichael Ellerman */ 690f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 691f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 692f2699491SMichael Ellerman } 693f2699491SMichael Ellerman 694f2699491SMichael Ellerman /* 695f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 696f2699491SMichael Ellerman * events to be added or removed. 697f2699491SMichael Ellerman */ 698f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 699f2699491SMichael Ellerman { 700f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 701f2699491SMichael Ellerman unsigned long flags; 702f2699491SMichael Ellerman 703f2699491SMichael Ellerman if (!ppmu) 704f2699491SMichael Ellerman return; 705f2699491SMichael Ellerman local_irq_save(flags); 706f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 707f2699491SMichael Ellerman 708f2699491SMichael Ellerman if (!cpuhw->disabled) { 709f2699491SMichael Ellerman cpuhw->disabled = 1; 710f2699491SMichael Ellerman cpuhw->n_added = 0; 711f2699491SMichael Ellerman 712f2699491SMichael Ellerman /* 713f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 714f2699491SMichael Ellerman */ 715f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 716f2699491SMichael Ellerman ppc_enable_pmcs(); 717f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 718f2699491SMichael Ellerman } 719f2699491SMichael Ellerman 720f2699491SMichael Ellerman /* 721f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 722f2699491SMichael Ellerman */ 723f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 724f2699491SMichael Ellerman mtspr(SPRN_MMCRA, 725f2699491SMichael Ellerman cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 726f2699491SMichael Ellerman mb(); 727f2699491SMichael Ellerman } 728f2699491SMichael Ellerman 729f2699491SMichael Ellerman /* 730f2699491SMichael Ellerman * Set the 'freeze counters' bit. 731f2699491SMichael Ellerman * The barrier is to make sure the mtspr has been 732f2699491SMichael Ellerman * executed and the PMU has frozen the events 733f2699491SMichael Ellerman * before we return. 734f2699491SMichael Ellerman */ 735f2699491SMichael Ellerman write_mmcr0(cpuhw, mfspr(SPRN_MMCR0) | MMCR0_FC); 736f2699491SMichael Ellerman mb(); 737f2699491SMichael Ellerman } 738f2699491SMichael Ellerman local_irq_restore(flags); 739f2699491SMichael Ellerman } 740f2699491SMichael Ellerman 741f2699491SMichael Ellerman /* 742f2699491SMichael Ellerman * Re-enable all events if disable == 0. 743f2699491SMichael Ellerman * If we were previously disabled and events were added, then 744f2699491SMichael Ellerman * put the new config on the PMU. 745f2699491SMichael Ellerman */ 746f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 747f2699491SMichael Ellerman { 748f2699491SMichael Ellerman struct perf_event *event; 749f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 750f2699491SMichael Ellerman unsigned long flags; 751f2699491SMichael Ellerman long i; 752f2699491SMichael Ellerman unsigned long val; 753f2699491SMichael Ellerman s64 left; 754f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 755f2699491SMichael Ellerman int n_lim; 756f2699491SMichael Ellerman int idx; 757f2699491SMichael Ellerman 758f2699491SMichael Ellerman if (!ppmu) 759f2699491SMichael Ellerman return; 760f2699491SMichael Ellerman local_irq_save(flags); 761f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 762f2699491SMichael Ellerman if (!cpuhw->disabled) { 763f2699491SMichael Ellerman local_irq_restore(flags); 764f2699491SMichael Ellerman return; 765f2699491SMichael Ellerman } 766f2699491SMichael Ellerman cpuhw->disabled = 0; 767f2699491SMichael Ellerman 768f2699491SMichael Ellerman /* 769f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 770f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 771f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 772f2699491SMichael Ellerman * (possibly updated for removal of events). 773f2699491SMichael Ellerman */ 774f2699491SMichael Ellerman if (!cpuhw->n_added) { 775f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 776f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 777f2699491SMichael Ellerman if (cpuhw->n_events == 0) 778f2699491SMichael Ellerman ppc_set_pmu_inuse(0); 779f2699491SMichael Ellerman goto out_enable; 780f2699491SMichael Ellerman } 781f2699491SMichael Ellerman 782f2699491SMichael Ellerman /* 783f2699491SMichael Ellerman * Compute MMCR* values for the new set of events 784f2699491SMichael Ellerman */ 785f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 786f2699491SMichael Ellerman cpuhw->mmcr)) { 787f2699491SMichael Ellerman /* shouldn't ever get here */ 788f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 789f2699491SMichael Ellerman goto out; 790f2699491SMichael Ellerman } 791f2699491SMichael Ellerman 792f2699491SMichael Ellerman /* 793f2699491SMichael Ellerman * Add in MMCR0 freeze bits corresponding to the 794f2699491SMichael Ellerman * attr.exclude_* bits for the first event. 795f2699491SMichael Ellerman * We have already checked that all events have the 796f2699491SMichael Ellerman * same values for these bits as the first event. 797f2699491SMichael Ellerman */ 798f2699491SMichael Ellerman event = cpuhw->event[0]; 799f2699491SMichael Ellerman if (event->attr.exclude_user) 800f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCP; 801f2699491SMichael Ellerman if (event->attr.exclude_kernel) 802f2699491SMichael Ellerman cpuhw->mmcr[0] |= freeze_events_kernel; 803f2699491SMichael Ellerman if (event->attr.exclude_hv) 804f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCHV; 805f2699491SMichael Ellerman 806f2699491SMichael Ellerman /* 807f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 808f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 809f2699491SMichael Ellerman * Then unfreeze the events. 810f2699491SMichael Ellerman */ 811f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 812f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 813f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 814f2699491SMichael Ellerman mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 815f2699491SMichael Ellerman | MMCR0_FC); 816f2699491SMichael Ellerman 817f2699491SMichael Ellerman /* 818f2699491SMichael Ellerman * Read off any pre-existing events that need to move 819f2699491SMichael Ellerman * to another PMC. 820f2699491SMichael Ellerman */ 821f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 822f2699491SMichael Ellerman event = cpuhw->event[i]; 823f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 824f2699491SMichael Ellerman power_pmu_read(event); 825f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 826f2699491SMichael Ellerman event->hw.idx = 0; 827f2699491SMichael Ellerman } 828f2699491SMichael Ellerman } 829f2699491SMichael Ellerman 830f2699491SMichael Ellerman /* 831f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 832f2699491SMichael Ellerman */ 833f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 834f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 835f2699491SMichael Ellerman event = cpuhw->event[i]; 836f2699491SMichael Ellerman if (event->hw.idx) 837f2699491SMichael Ellerman continue; 838f2699491SMichael Ellerman idx = hwc_index[i] + 1; 839f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 840f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 841f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 842f2699491SMichael Ellerman ++n_lim; 843f2699491SMichael Ellerman continue; 844f2699491SMichael Ellerman } 845f2699491SMichael Ellerman val = 0; 846f2699491SMichael Ellerman if (event->hw.sample_period) { 847f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 848f2699491SMichael Ellerman if (left < 0x80000000L) 849f2699491SMichael Ellerman val = 0x80000000L - left; 850f2699491SMichael Ellerman } 851f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 852f2699491SMichael Ellerman event->hw.idx = idx; 853f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 854f2699491SMichael Ellerman val = 0; 855f2699491SMichael Ellerman write_pmc(idx, val); 856f2699491SMichael Ellerman perf_event_update_userpage(event); 857f2699491SMichael Ellerman } 858f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 859f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 860f2699491SMichael Ellerman 861f2699491SMichael Ellerman out_enable: 862f2699491SMichael Ellerman mb(); 863f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 864f2699491SMichael Ellerman 865f2699491SMichael Ellerman /* 866f2699491SMichael Ellerman * Enable instruction sampling if necessary 867f2699491SMichael Ellerman */ 868f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 869f2699491SMichael Ellerman mb(); 870f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 871f2699491SMichael Ellerman } 872f2699491SMichael Ellerman 873f2699491SMichael Ellerman out: 8743925f46bSAnshuman Khandual if (cpuhw->bhrb_users) 8753925f46bSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 8763925f46bSAnshuman Khandual 877f2699491SMichael Ellerman local_irq_restore(flags); 878f2699491SMichael Ellerman } 879f2699491SMichael Ellerman 880f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 881f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 882f2699491SMichael Ellerman unsigned int *flags) 883f2699491SMichael Ellerman { 884f2699491SMichael Ellerman int n = 0; 885f2699491SMichael Ellerman struct perf_event *event; 886f2699491SMichael Ellerman 887f2699491SMichael Ellerman if (!is_software_event(group)) { 888f2699491SMichael Ellerman if (n >= max_count) 889f2699491SMichael Ellerman return -1; 890f2699491SMichael Ellerman ctrs[n] = group; 891f2699491SMichael Ellerman flags[n] = group->hw.event_base; 892f2699491SMichael Ellerman events[n++] = group->hw.config; 893f2699491SMichael Ellerman } 894f2699491SMichael Ellerman list_for_each_entry(event, &group->sibling_list, group_entry) { 895f2699491SMichael Ellerman if (!is_software_event(event) && 896f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 897f2699491SMichael Ellerman if (n >= max_count) 898f2699491SMichael Ellerman return -1; 899f2699491SMichael Ellerman ctrs[n] = event; 900f2699491SMichael Ellerman flags[n] = event->hw.event_base; 901f2699491SMichael Ellerman events[n++] = event->hw.config; 902f2699491SMichael Ellerman } 903f2699491SMichael Ellerman } 904f2699491SMichael Ellerman return n; 905f2699491SMichael Ellerman } 906f2699491SMichael Ellerman 9073925f46bSAnshuman Khandual /* Reset all possible BHRB entries */ 9083925f46bSAnshuman Khandual static void power_pmu_bhrb_reset(void) 9093925f46bSAnshuman Khandual { 9103925f46bSAnshuman Khandual asm volatile(PPC_CLRBHRB); 9113925f46bSAnshuman Khandual } 9123925f46bSAnshuman Khandual 9133925f46bSAnshuman Khandual void power_pmu_bhrb_enable(struct perf_event *event) 9143925f46bSAnshuman Khandual { 9153925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 9163925f46bSAnshuman Khandual 9173925f46bSAnshuman Khandual if (!ppmu->bhrb_nr) 9183925f46bSAnshuman Khandual return; 9193925f46bSAnshuman Khandual 9203925f46bSAnshuman Khandual /* Clear BHRB if we changed task context to avoid data leaks */ 9213925f46bSAnshuman Khandual if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 9223925f46bSAnshuman Khandual power_pmu_bhrb_reset(); 9233925f46bSAnshuman Khandual cpuhw->bhrb_context = event->ctx; 9243925f46bSAnshuman Khandual } 9253925f46bSAnshuman Khandual cpuhw->bhrb_users++; 9263925f46bSAnshuman Khandual } 9273925f46bSAnshuman Khandual 9283925f46bSAnshuman Khandual void power_pmu_bhrb_disable(struct perf_event *event) 9293925f46bSAnshuman Khandual { 9303925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 9313925f46bSAnshuman Khandual 9323925f46bSAnshuman Khandual if (!ppmu->bhrb_nr) 9333925f46bSAnshuman Khandual return; 9343925f46bSAnshuman Khandual 9353925f46bSAnshuman Khandual cpuhw->bhrb_users--; 9363925f46bSAnshuman Khandual WARN_ON_ONCE(cpuhw->bhrb_users < 0); 9373925f46bSAnshuman Khandual 9383925f46bSAnshuman Khandual if (!cpuhw->disabled && !cpuhw->bhrb_users) { 9393925f46bSAnshuman Khandual /* BHRB cannot be turned off when other 9403925f46bSAnshuman Khandual * events are active on the PMU. 9413925f46bSAnshuman Khandual */ 9423925f46bSAnshuman Khandual 9433925f46bSAnshuman Khandual /* avoid stale pointer */ 9443925f46bSAnshuman Khandual cpuhw->bhrb_context = NULL; 9453925f46bSAnshuman Khandual } 9463925f46bSAnshuman Khandual } 9473925f46bSAnshuman Khandual 948f2699491SMichael Ellerman /* 949f2699491SMichael Ellerman * Add a event to the PMU. 950f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 951f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 952f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 953f2699491SMichael Ellerman */ 954f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 955f2699491SMichael Ellerman { 956f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 957f2699491SMichael Ellerman unsigned long flags; 958f2699491SMichael Ellerman int n0; 959f2699491SMichael Ellerman int ret = -EAGAIN; 960f2699491SMichael Ellerman 961f2699491SMichael Ellerman local_irq_save(flags); 962f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 963f2699491SMichael Ellerman 964f2699491SMichael Ellerman /* 965f2699491SMichael Ellerman * Add the event to the list (if there is room) 966f2699491SMichael Ellerman * and check whether the total set is still feasible. 967f2699491SMichael Ellerman */ 968f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 969f2699491SMichael Ellerman n0 = cpuhw->n_events; 970f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 971f2699491SMichael Ellerman goto out; 972f2699491SMichael Ellerman cpuhw->event[n0] = event; 973f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 974f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 975f2699491SMichael Ellerman 976f53d168cSsukadev@linux.vnet.ibm.com /* 977f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 978f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 979f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 980f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 981f53d168cSsukadev@linux.vnet.ibm.com */ 982f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 983f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 984f53d168cSsukadev@linux.vnet.ibm.com else 985f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 986f2699491SMichael Ellerman 987f2699491SMichael Ellerman /* 988f2699491SMichael Ellerman * If group events scheduling transaction was started, 989f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 990f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 991f2699491SMichael Ellerman */ 992f2699491SMichael Ellerman if (cpuhw->group_flag & PERF_EVENT_TXN) 993f2699491SMichael Ellerman goto nocheck; 994f2699491SMichael Ellerman 995f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 996f2699491SMichael Ellerman goto out; 997f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 998f2699491SMichael Ellerman goto out; 999f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1000f2699491SMichael Ellerman 1001f2699491SMichael Ellerman nocheck: 1002f2699491SMichael Ellerman ++cpuhw->n_events; 1003f2699491SMichael Ellerman ++cpuhw->n_added; 1004f2699491SMichael Ellerman 1005f2699491SMichael Ellerman ret = 0; 1006f2699491SMichael Ellerman out: 10073925f46bSAnshuman Khandual if (has_branch_stack(event)) 10083925f46bSAnshuman Khandual power_pmu_bhrb_enable(event); 10093925f46bSAnshuman Khandual 1010f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1011f2699491SMichael Ellerman local_irq_restore(flags); 1012f2699491SMichael Ellerman return ret; 1013f2699491SMichael Ellerman } 1014f2699491SMichael Ellerman 1015f2699491SMichael Ellerman /* 1016f2699491SMichael Ellerman * Remove a event from the PMU. 1017f2699491SMichael Ellerman */ 1018f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1019f2699491SMichael Ellerman { 1020f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1021f2699491SMichael Ellerman long i; 1022f2699491SMichael Ellerman unsigned long flags; 1023f2699491SMichael Ellerman 1024f2699491SMichael Ellerman local_irq_save(flags); 1025f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1026f2699491SMichael Ellerman 1027f2699491SMichael Ellerman power_pmu_read(event); 1028f2699491SMichael Ellerman 1029f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1030f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1031f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1032f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1033f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1034f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1035f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1036f2699491SMichael Ellerman } 1037f2699491SMichael Ellerman --cpuhw->n_events; 1038f2699491SMichael Ellerman ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1039f2699491SMichael Ellerman if (event->hw.idx) { 1040f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1041f2699491SMichael Ellerman event->hw.idx = 0; 1042f2699491SMichael Ellerman } 1043f2699491SMichael Ellerman perf_event_update_userpage(event); 1044f2699491SMichael Ellerman break; 1045f2699491SMichael Ellerman } 1046f2699491SMichael Ellerman } 1047f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1048f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1049f2699491SMichael Ellerman break; 1050f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1051f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1052f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1053f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1054f2699491SMichael Ellerman } 1055f2699491SMichael Ellerman --cpuhw->n_limited; 1056f2699491SMichael Ellerman } 1057f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1058f2699491SMichael Ellerman /* disable exceptions if no events are running */ 1059f2699491SMichael Ellerman cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1060f2699491SMichael Ellerman } 1061f2699491SMichael Ellerman 10623925f46bSAnshuman Khandual if (has_branch_stack(event)) 10633925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 10643925f46bSAnshuman Khandual 1065f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1066f2699491SMichael Ellerman local_irq_restore(flags); 1067f2699491SMichael Ellerman } 1068f2699491SMichael Ellerman 1069f2699491SMichael Ellerman /* 1070f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1071f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1072f2699491SMichael Ellerman */ 1073f2699491SMichael Ellerman 1074f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1075f2699491SMichael Ellerman { 1076f2699491SMichael Ellerman unsigned long flags; 1077f2699491SMichael Ellerman s64 left; 1078f2699491SMichael Ellerman unsigned long val; 1079f2699491SMichael Ellerman 1080f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1081f2699491SMichael Ellerman return; 1082f2699491SMichael Ellerman 1083f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1084f2699491SMichael Ellerman return; 1085f2699491SMichael Ellerman 1086f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1087f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1088f2699491SMichael Ellerman 1089f2699491SMichael Ellerman local_irq_save(flags); 1090f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1091f2699491SMichael Ellerman 1092f2699491SMichael Ellerman event->hw.state = 0; 1093f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1094f2699491SMichael Ellerman 1095f2699491SMichael Ellerman val = 0; 1096f2699491SMichael Ellerman if (left < 0x80000000L) 1097f2699491SMichael Ellerman val = 0x80000000L - left; 1098f2699491SMichael Ellerman 1099f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1100f2699491SMichael Ellerman 1101f2699491SMichael Ellerman perf_event_update_userpage(event); 1102f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1103f2699491SMichael Ellerman local_irq_restore(flags); 1104f2699491SMichael Ellerman } 1105f2699491SMichael Ellerman 1106f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1107f2699491SMichael Ellerman { 1108f2699491SMichael Ellerman unsigned long flags; 1109f2699491SMichael Ellerman 1110f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1111f2699491SMichael Ellerman return; 1112f2699491SMichael Ellerman 1113f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1114f2699491SMichael Ellerman return; 1115f2699491SMichael Ellerman 1116f2699491SMichael Ellerman local_irq_save(flags); 1117f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1118f2699491SMichael Ellerman 1119f2699491SMichael Ellerman power_pmu_read(event); 1120f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1121f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1122f2699491SMichael Ellerman 1123f2699491SMichael Ellerman perf_event_update_userpage(event); 1124f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1125f2699491SMichael Ellerman local_irq_restore(flags); 1126f2699491SMichael Ellerman } 1127f2699491SMichael Ellerman 1128f2699491SMichael Ellerman /* 1129f2699491SMichael Ellerman * Start group events scheduling transaction 1130f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1131f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1132f2699491SMichael Ellerman */ 1133f2699491SMichael Ellerman void power_pmu_start_txn(struct pmu *pmu) 1134f2699491SMichael Ellerman { 1135f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1136f2699491SMichael Ellerman 1137f2699491SMichael Ellerman perf_pmu_disable(pmu); 1138f2699491SMichael Ellerman cpuhw->group_flag |= PERF_EVENT_TXN; 1139f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1140f2699491SMichael Ellerman } 1141f2699491SMichael Ellerman 1142f2699491SMichael Ellerman /* 1143f2699491SMichael Ellerman * Stop group events scheduling transaction 1144f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1145f2699491SMichael Ellerman * schedulability test. 1146f2699491SMichael Ellerman */ 1147f2699491SMichael Ellerman void power_pmu_cancel_txn(struct pmu *pmu) 1148f2699491SMichael Ellerman { 1149f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1150f2699491SMichael Ellerman 1151f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1152f2699491SMichael Ellerman perf_pmu_enable(pmu); 1153f2699491SMichael Ellerman } 1154f2699491SMichael Ellerman 1155f2699491SMichael Ellerman /* 1156f2699491SMichael Ellerman * Commit group events scheduling transaction 1157f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1158f2699491SMichael Ellerman * Return 0 if success 1159f2699491SMichael Ellerman */ 1160f2699491SMichael Ellerman int power_pmu_commit_txn(struct pmu *pmu) 1161f2699491SMichael Ellerman { 1162f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1163f2699491SMichael Ellerman long i, n; 1164f2699491SMichael Ellerman 1165f2699491SMichael Ellerman if (!ppmu) 1166f2699491SMichael Ellerman return -EAGAIN; 1167f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1168f2699491SMichael Ellerman n = cpuhw->n_events; 1169f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1170f2699491SMichael Ellerman return -EAGAIN; 1171f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1172f2699491SMichael Ellerman if (i < 0) 1173f2699491SMichael Ellerman return -EAGAIN; 1174f2699491SMichael Ellerman 1175f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1176f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1177f2699491SMichael Ellerman 1178f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1179f2699491SMichael Ellerman perf_pmu_enable(pmu); 1180f2699491SMichael Ellerman return 0; 1181f2699491SMichael Ellerman } 1182f2699491SMichael Ellerman 11833925f46bSAnshuman Khandual /* Called from ctxsw to prevent one process's branch entries to 11843925f46bSAnshuman Khandual * mingle with the other process's entries during context switch. 11853925f46bSAnshuman Khandual */ 11863925f46bSAnshuman Khandual void power_pmu_flush_branch_stack(void) 11873925f46bSAnshuman Khandual { 11883925f46bSAnshuman Khandual if (ppmu->bhrb_nr) 11893925f46bSAnshuman Khandual power_pmu_bhrb_reset(); 11903925f46bSAnshuman Khandual } 11913925f46bSAnshuman Khandual 1192f2699491SMichael Ellerman /* 1193f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1194f2699491SMichael Ellerman * or 0 if not. 1195f2699491SMichael Ellerman * A event can only go on a limited PMC if it counts something 1196f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1197f2699491SMichael Ellerman * doesn't exclude any processor mode. 1198f2699491SMichael Ellerman */ 1199f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1200f2699491SMichael Ellerman unsigned int flags) 1201f2699491SMichael Ellerman { 1202f2699491SMichael Ellerman int n; 1203f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1204f2699491SMichael Ellerman 1205f2699491SMichael Ellerman if (event->attr.exclude_user 1206f2699491SMichael Ellerman || event->attr.exclude_kernel 1207f2699491SMichael Ellerman || event->attr.exclude_hv 1208f2699491SMichael Ellerman || event->attr.sample_period) 1209f2699491SMichael Ellerman return 0; 1210f2699491SMichael Ellerman 1211f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1212f2699491SMichael Ellerman return 1; 1213f2699491SMichael Ellerman 1214f2699491SMichael Ellerman /* 1215f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1216f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1217f2699491SMichael Ellerman */ 1218f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1219f2699491SMichael Ellerman return 0; 1220f2699491SMichael Ellerman 1221f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1222f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1223f2699491SMichael Ellerman 1224f2699491SMichael Ellerman return n > 0; 1225f2699491SMichael Ellerman } 1226f2699491SMichael Ellerman 1227f2699491SMichael Ellerman /* 1228f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1229f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1230f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1231f2699491SMichael Ellerman */ 1232f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1233f2699491SMichael Ellerman { 1234f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1235f2699491SMichael Ellerman int n; 1236f2699491SMichael Ellerman 1237f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1238f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1239f2699491SMichael Ellerman if (!n) 1240f2699491SMichael Ellerman return 0; 1241f2699491SMichael Ellerman return alt[0]; 1242f2699491SMichael Ellerman } 1243f2699491SMichael Ellerman 1244f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1245f2699491SMichael Ellerman static atomic_t num_events; 1246f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1247f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1248f2699491SMichael Ellerman 1249f2699491SMichael Ellerman /* 1250f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1251f2699491SMichael Ellerman */ 1252f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1253f2699491SMichael Ellerman { 1254f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1255f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1256f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1257f2699491SMichael Ellerman release_pmc_hardware(); 1258f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1259f2699491SMichael Ellerman } 1260f2699491SMichael Ellerman } 1261f2699491SMichael Ellerman 1262f2699491SMichael Ellerman /* 1263f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1264f2699491SMichael Ellerman */ 1265f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1266f2699491SMichael Ellerman { 1267f2699491SMichael Ellerman unsigned long type, op, result; 1268f2699491SMichael Ellerman int ev; 1269f2699491SMichael Ellerman 1270f2699491SMichael Ellerman if (!ppmu->cache_events) 1271f2699491SMichael Ellerman return -EINVAL; 1272f2699491SMichael Ellerman 1273f2699491SMichael Ellerman /* unpack config */ 1274f2699491SMichael Ellerman type = config & 0xff; 1275f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1276f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1277f2699491SMichael Ellerman 1278f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1279f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1280f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1281f2699491SMichael Ellerman return -EINVAL; 1282f2699491SMichael Ellerman 1283f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1284f2699491SMichael Ellerman if (ev == 0) 1285f2699491SMichael Ellerman return -EOPNOTSUPP; 1286f2699491SMichael Ellerman if (ev == -1) 1287f2699491SMichael Ellerman return -EINVAL; 1288f2699491SMichael Ellerman *eventp = ev; 1289f2699491SMichael Ellerman return 0; 1290f2699491SMichael Ellerman } 1291f2699491SMichael Ellerman 1292f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1293f2699491SMichael Ellerman { 1294f2699491SMichael Ellerman u64 ev; 1295f2699491SMichael Ellerman unsigned long flags; 1296f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1297f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1298f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1299f2699491SMichael Ellerman int n; 1300f2699491SMichael Ellerman int err; 1301f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1302f2699491SMichael Ellerman 1303f2699491SMichael Ellerman if (!ppmu) 1304f2699491SMichael Ellerman return -ENOENT; 1305f2699491SMichael Ellerman 13063925f46bSAnshuman Khandual if (has_branch_stack(event)) { 13073925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 13083925f46bSAnshuman Khandual if (!(ppmu->flags & PPMU_BHRB)) 13095375871dSLinus Torvalds return -EOPNOTSUPP; 13103925f46bSAnshuman Khandual } 13115375871dSLinus Torvalds 1312f2699491SMichael Ellerman switch (event->attr.type) { 1313f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1314f2699491SMichael Ellerman ev = event->attr.config; 1315f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1316f2699491SMichael Ellerman return -EOPNOTSUPP; 1317f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1318f2699491SMichael Ellerman break; 1319f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1320f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1321f2699491SMichael Ellerman if (err) 1322f2699491SMichael Ellerman return err; 1323f2699491SMichael Ellerman break; 1324f2699491SMichael Ellerman case PERF_TYPE_RAW: 1325f2699491SMichael Ellerman ev = event->attr.config; 1326f2699491SMichael Ellerman break; 1327f2699491SMichael Ellerman default: 1328f2699491SMichael Ellerman return -ENOENT; 1329f2699491SMichael Ellerman } 1330f2699491SMichael Ellerman 1331f2699491SMichael Ellerman event->hw.config_base = ev; 1332f2699491SMichael Ellerman event->hw.idx = 0; 1333f2699491SMichael Ellerman 1334f2699491SMichael Ellerman /* 1335f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1336f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1337f2699491SMichael Ellerman * the user set it to. 1338f2699491SMichael Ellerman */ 1339f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1340f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1341f2699491SMichael Ellerman 1342f2699491SMichael Ellerman /* 1343f2699491SMichael Ellerman * If this is a per-task event, then we can use 1344f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1345f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1346f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1347f2699491SMichael Ellerman */ 1348f2699491SMichael Ellerman flags = 0; 1349f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1350f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1351f2699491SMichael Ellerman 1352f2699491SMichael Ellerman /* 1353f2699491SMichael Ellerman * If this machine has limited events, check whether this 1354f2699491SMichael Ellerman * event_id could go on a limited event. 1355f2699491SMichael Ellerman */ 1356f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1357f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1358f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1359f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1360f2699491SMichael Ellerman /* 1361f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1362f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1363f2699491SMichael Ellerman * alternative goes on a normal PMC. 1364f2699491SMichael Ellerman */ 1365f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1366f2699491SMichael Ellerman if (!ev) 1367f2699491SMichael Ellerman return -EINVAL; 1368f2699491SMichael Ellerman } 1369f2699491SMichael Ellerman } 1370f2699491SMichael Ellerman 1371f2699491SMichael Ellerman /* 1372f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1373f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1374f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1375f2699491SMichael Ellerman */ 1376f2699491SMichael Ellerman n = 0; 1377f2699491SMichael Ellerman if (event->group_leader != event) { 1378f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1379f2699491SMichael Ellerman ctrs, events, cflags); 1380f2699491SMichael Ellerman if (n < 0) 1381f2699491SMichael Ellerman return -EINVAL; 1382f2699491SMichael Ellerman } 1383f2699491SMichael Ellerman events[n] = ev; 1384f2699491SMichael Ellerman ctrs[n] = event; 1385f2699491SMichael Ellerman cflags[n] = flags; 1386f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1387f2699491SMichael Ellerman return -EINVAL; 1388f2699491SMichael Ellerman 1389f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1390f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 13913925f46bSAnshuman Khandual 13923925f46bSAnshuman Khandual if (has_branch_stack(event)) { 13933925f46bSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 13943925f46bSAnshuman Khandual event->attr.branch_sample_type); 13953925f46bSAnshuman Khandual 13963925f46bSAnshuman Khandual if(cpuhw->bhrb_filter == -1) 13973925f46bSAnshuman Khandual return -EOPNOTSUPP; 13983925f46bSAnshuman Khandual } 13993925f46bSAnshuman Khandual 1400f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 1401f2699491SMichael Ellerman if (err) 1402f2699491SMichael Ellerman return -EINVAL; 1403f2699491SMichael Ellerman 1404f2699491SMichael Ellerman event->hw.config = events[n]; 1405f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 1406f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1407f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 1408f2699491SMichael Ellerman 1409f2699491SMichael Ellerman /* 1410f2699491SMichael Ellerman * See if we need to reserve the PMU. 1411f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 1412f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 1413f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 1414f2699491SMichael Ellerman */ 1415f2699491SMichael Ellerman err = 0; 1416f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 1417f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1418f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 1419f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 1420f2699491SMichael Ellerman err = -EBUSY; 1421f2699491SMichael Ellerman else 1422f2699491SMichael Ellerman atomic_inc(&num_events); 1423f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1424f2699491SMichael Ellerman } 1425f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 1426f2699491SMichael Ellerman 1427f2699491SMichael Ellerman return err; 1428f2699491SMichael Ellerman } 1429f2699491SMichael Ellerman 14305375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 14315375871dSLinus Torvalds { 14325375871dSLinus Torvalds return event->hw.idx; 14335375871dSLinus Torvalds } 14345375871dSLinus Torvalds 14351c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 14361c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 14371c53a270SSukadev Bhattiprolu { 14381c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 14391c53a270SSukadev Bhattiprolu 14401c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 14411c53a270SSukadev Bhattiprolu 14421c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 14431c53a270SSukadev Bhattiprolu } 14441c53a270SSukadev Bhattiprolu 1445f2699491SMichael Ellerman struct pmu power_pmu = { 1446f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 1447f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 1448f2699491SMichael Ellerman .event_init = power_pmu_event_init, 1449f2699491SMichael Ellerman .add = power_pmu_add, 1450f2699491SMichael Ellerman .del = power_pmu_del, 1451f2699491SMichael Ellerman .start = power_pmu_start, 1452f2699491SMichael Ellerman .stop = power_pmu_stop, 1453f2699491SMichael Ellerman .read = power_pmu_read, 1454f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 1455f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 1456f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 14575375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 14583925f46bSAnshuman Khandual .flush_branch_stack = power_pmu_flush_branch_stack, 1459f2699491SMichael Ellerman }; 1460f2699491SMichael Ellerman 14613925f46bSAnshuman Khandual /* Processing BHRB entries */ 14623925f46bSAnshuman Khandual void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 14633925f46bSAnshuman Khandual { 14643925f46bSAnshuman Khandual u64 val; 14653925f46bSAnshuman Khandual u64 addr; 14663925f46bSAnshuman Khandual int r_index, u_index, target, pred; 14673925f46bSAnshuman Khandual 14683925f46bSAnshuman Khandual r_index = 0; 14693925f46bSAnshuman Khandual u_index = 0; 14703925f46bSAnshuman Khandual while (r_index < ppmu->bhrb_nr) { 14713925f46bSAnshuman Khandual /* Assembly read function */ 14723925f46bSAnshuman Khandual val = read_bhrb(r_index); 14733925f46bSAnshuman Khandual 14743925f46bSAnshuman Khandual /* Terminal marker: End of valid BHRB entries */ 14753925f46bSAnshuman Khandual if (val == 0) { 14763925f46bSAnshuman Khandual break; 14773925f46bSAnshuman Khandual } else { 14783925f46bSAnshuman Khandual /* BHRB field break up */ 14793925f46bSAnshuman Khandual addr = val & BHRB_EA; 14803925f46bSAnshuman Khandual pred = val & BHRB_PREDICTION; 14813925f46bSAnshuman Khandual target = val & BHRB_TARGET; 14823925f46bSAnshuman Khandual 14833925f46bSAnshuman Khandual /* Probable Missed entry: Not applicable for POWER8 */ 14843925f46bSAnshuman Khandual if ((addr == 0) && (target == 0) && (pred == 1)) { 14853925f46bSAnshuman Khandual r_index++; 14863925f46bSAnshuman Khandual continue; 14873925f46bSAnshuman Khandual } 14883925f46bSAnshuman Khandual 14893925f46bSAnshuman Khandual /* Real Missed entry: Power8 based missed entry */ 14903925f46bSAnshuman Khandual if ((addr == 0) && (target == 1) && (pred == 1)) { 14913925f46bSAnshuman Khandual r_index++; 14923925f46bSAnshuman Khandual continue; 14933925f46bSAnshuman Khandual } 14943925f46bSAnshuman Khandual 14953925f46bSAnshuman Khandual /* Reserved condition: Not a valid entry */ 14963925f46bSAnshuman Khandual if ((addr == 0) && (target == 1) && (pred == 0)) { 14973925f46bSAnshuman Khandual r_index++; 14983925f46bSAnshuman Khandual continue; 14993925f46bSAnshuman Khandual } 15003925f46bSAnshuman Khandual 15013925f46bSAnshuman Khandual /* Is a target address */ 15023925f46bSAnshuman Khandual if (val & BHRB_TARGET) { 15033925f46bSAnshuman Khandual /* First address cannot be a target address */ 15043925f46bSAnshuman Khandual if (r_index == 0) { 15053925f46bSAnshuman Khandual r_index++; 15063925f46bSAnshuman Khandual continue; 15073925f46bSAnshuman Khandual } 15083925f46bSAnshuman Khandual 15093925f46bSAnshuman Khandual /* Update target address for the previous entry */ 15103925f46bSAnshuman Khandual cpuhw->bhrb_entries[u_index - 1].to = addr; 15113925f46bSAnshuman Khandual cpuhw->bhrb_entries[u_index - 1].mispred = pred; 15123925f46bSAnshuman Khandual cpuhw->bhrb_entries[u_index - 1].predicted = ~pred; 15133925f46bSAnshuman Khandual 15143925f46bSAnshuman Khandual /* Dont increment u_index */ 15153925f46bSAnshuman Khandual r_index++; 15163925f46bSAnshuman Khandual } else { 15173925f46bSAnshuman Khandual /* Update address, flags for current entry */ 15183925f46bSAnshuman Khandual cpuhw->bhrb_entries[u_index].from = addr; 15193925f46bSAnshuman Khandual cpuhw->bhrb_entries[u_index].mispred = pred; 15203925f46bSAnshuman Khandual cpuhw->bhrb_entries[u_index].predicted = ~pred; 15213925f46bSAnshuman Khandual 15223925f46bSAnshuman Khandual /* Successfully popullated one entry */ 15233925f46bSAnshuman Khandual u_index++; 15243925f46bSAnshuman Khandual r_index++; 15253925f46bSAnshuman Khandual } 15263925f46bSAnshuman Khandual } 15273925f46bSAnshuman Khandual } 15283925f46bSAnshuman Khandual cpuhw->bhrb_stack.nr = u_index; 15293925f46bSAnshuman Khandual return; 15303925f46bSAnshuman Khandual } 1531e6878835Ssukadev@linux.vnet.ibm.com 1532f2699491SMichael Ellerman /* 1533f2699491SMichael Ellerman * A counter has overflowed; update its count and record 1534f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 1535f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 1536f2699491SMichael Ellerman */ 1537f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 1538f2699491SMichael Ellerman struct pt_regs *regs) 1539f2699491SMichael Ellerman { 1540f2699491SMichael Ellerman u64 period = event->hw.sample_period; 1541f2699491SMichael Ellerman s64 prev, delta, left; 1542f2699491SMichael Ellerman int record = 0; 1543f2699491SMichael Ellerman 1544f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 1545f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1546f2699491SMichael Ellerman return; 1547f2699491SMichael Ellerman } 1548f2699491SMichael Ellerman 1549f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 1550f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1551f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1552f2699491SMichael Ellerman local64_add(delta, &event->count); 1553f2699491SMichael Ellerman 1554f2699491SMichael Ellerman /* 1555f2699491SMichael Ellerman * See if the total period for this event has expired, 1556f2699491SMichael Ellerman * and update for the next period. 1557f2699491SMichael Ellerman */ 1558f2699491SMichael Ellerman val = 0; 1559f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 1560e13e895fSMichael Neuling if (delta == 0) 1561e13e895fSMichael Neuling left++; 1562f2699491SMichael Ellerman if (period) { 1563f2699491SMichael Ellerman if (left <= 0) { 1564f2699491SMichael Ellerman left += period; 1565f2699491SMichael Ellerman if (left <= 0) 1566f2699491SMichael Ellerman left = period; 1567e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 1568f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1569f2699491SMichael Ellerman } 1570f2699491SMichael Ellerman if (left < 0x80000000LL) 1571f2699491SMichael Ellerman val = 0x80000000LL - left; 1572f2699491SMichael Ellerman } 1573f2699491SMichael Ellerman 1574f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1575f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1576f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 1577f2699491SMichael Ellerman perf_event_update_userpage(event); 1578f2699491SMichael Ellerman 1579f2699491SMichael Ellerman /* 1580f2699491SMichael Ellerman * Finally record data if requested. 1581f2699491SMichael Ellerman */ 1582f2699491SMichael Ellerman if (record) { 1583f2699491SMichael Ellerman struct perf_sample_data data; 1584f2699491SMichael Ellerman 1585fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 1586f2699491SMichael Ellerman 1587f2699491SMichael Ellerman if (event->attr.sample_type & PERF_SAMPLE_ADDR) 1588f2699491SMichael Ellerman perf_get_data_addr(regs, &data.addr); 1589f2699491SMichael Ellerman 15903925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 15913925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 15923925f46bSAnshuman Khandual cpuhw = &__get_cpu_var(cpu_hw_events); 15933925f46bSAnshuman Khandual power_pmu_bhrb_read(cpuhw); 15943925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 15953925f46bSAnshuman Khandual } 15963925f46bSAnshuman Khandual 1597f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 1598f2699491SMichael Ellerman power_pmu_stop(event, 0); 1599f2699491SMichael Ellerman } 1600f2699491SMichael Ellerman } 1601f2699491SMichael Ellerman 1602f2699491SMichael Ellerman /* 1603f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 1604f2699491SMichael Ellerman * for an event_id. 1605f2699491SMichael Ellerman */ 1606f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 1607f2699491SMichael Ellerman { 1608f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 1609f2699491SMichael Ellerman 1610f2699491SMichael Ellerman if (flags) 1611f2699491SMichael Ellerman return flags; 1612f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 1613f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 1614f2699491SMichael Ellerman } 1615f2699491SMichael Ellerman 1616f2699491SMichael Ellerman /* 1617f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 1618f2699491SMichael Ellerman * for an event_id. 1619f2699491SMichael Ellerman */ 1620f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 1621f2699491SMichael Ellerman { 162233904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 1623f2699491SMichael Ellerman 1624e6878835Ssukadev@linux.vnet.ibm.com if (use_siar && siar_valid(regs)) 16251ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 1626e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 1627e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 162875382aa7SAnton Blanchard else 162975382aa7SAnton Blanchard return regs->nip; 1630f2699491SMichael Ellerman } 1631f2699491SMichael Ellerman 1632bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 1633f2699491SMichael Ellerman { 1634f2699491SMichael Ellerman /* 1635f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 1636f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 1637f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 1638f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 1639f2699491SMichael Ellerman * cycles from overflow. 1640f2699491SMichael Ellerman * 1641f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 1642f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 1643f2699491SMichael Ellerman * don't want to mistakenly reset them. 1644f2699491SMichael Ellerman */ 1645bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 1646bc09c219SMichael Neuling return true; 1647bc09c219SMichael Neuling 1648bc09c219SMichael Neuling return false; 1649bc09c219SMichael Neuling } 1650bc09c219SMichael Neuling 1651bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 1652bc09c219SMichael Neuling { 1653bc09c219SMichael Neuling if ((int)val < 0) 1654f2699491SMichael Ellerman return true; 1655f2699491SMichael Ellerman 1656f2699491SMichael Ellerman return false; 1657f2699491SMichael Ellerman } 1658f2699491SMichael Ellerman 1659f2699491SMichael Ellerman /* 1660f2699491SMichael Ellerman * Performance monitor interrupt stuff 1661f2699491SMichael Ellerman */ 1662f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs) 1663f2699491SMichael Ellerman { 1664bc09c219SMichael Neuling int i, j; 1665f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1666f2699491SMichael Ellerman struct perf_event *event; 1667bc09c219SMichael Neuling unsigned long val[8]; 1668bc09c219SMichael Neuling int found, active; 1669f2699491SMichael Ellerman int nmi; 1670f2699491SMichael Ellerman 1671f2699491SMichael Ellerman if (cpuhw->n_limited) 1672f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 1673f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 1674f2699491SMichael Ellerman 1675f2699491SMichael Ellerman perf_read_regs(regs); 1676f2699491SMichael Ellerman 1677f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 1678f2699491SMichael Ellerman if (nmi) 1679f2699491SMichael Ellerman nmi_enter(); 1680f2699491SMichael Ellerman else 1681f2699491SMichael Ellerman irq_enter(); 1682f2699491SMichael Ellerman 1683bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 1684bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 1685bc09c219SMichael Neuling val[i] = read_pmc(i + 1); 1686bc09c219SMichael Neuling 1687bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 1688bc09c219SMichael Neuling found = 0; 1689bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 1690bc09c219SMichael Neuling if (!pmc_overflow(val[i])) 1691bc09c219SMichael Neuling continue; 1692bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 1693bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 1694bc09c219SMichael Neuling /* 1695bc09c219SMichael Neuling * We've found one that's overflowed. For active 1696bc09c219SMichael Neuling * counters we need to log this. For inactive 1697bc09c219SMichael Neuling * counters, we need to reset it anyway 1698bc09c219SMichael Neuling */ 1699bc09c219SMichael Neuling found = 1; 1700bc09c219SMichael Neuling active = 0; 1701bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 1702bc09c219SMichael Neuling event = cpuhw->event[j]; 1703bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 1704bc09c219SMichael Neuling active = 1; 1705bc09c219SMichael Neuling record_and_restart(event, val[i], regs); 1706bc09c219SMichael Neuling break; 1707bc09c219SMichael Neuling } 1708bc09c219SMichael Neuling } 1709bc09c219SMichael Neuling if (!active) 1710bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 1711bc09c219SMichael Neuling write_pmc(i + 1, 0); 1712bc09c219SMichael Neuling } 1713bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 1714bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 1715f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1716f2699491SMichael Ellerman event = cpuhw->event[i]; 1717f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 1718f2699491SMichael Ellerman continue; 1719bc09c219SMichael Neuling if (pmc_overflow_power7(val[event->hw.idx - 1])) { 1720bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 1721f2699491SMichael Ellerman found = 1; 1722bc09c219SMichael Neuling record_and_restart(event, 1723bc09c219SMichael Neuling val[event->hw.idx - 1], 1724bc09c219SMichael Neuling regs); 1725f2699491SMichael Ellerman } 1726f2699491SMichael Ellerman } 1727f2699491SMichael Ellerman } 1728bc09c219SMichael Neuling if ((!found) && printk_ratelimit()) 1729bc09c219SMichael Neuling printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 1730f2699491SMichael Ellerman 1731f2699491SMichael Ellerman /* 1732f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 1733f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 1734f2699491SMichael Ellerman * and thus allow interrupts to occur again. 1735f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 1736f2699491SMichael Ellerman * we get back out of this interrupt. 1737f2699491SMichael Ellerman */ 1738f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 1739f2699491SMichael Ellerman 1740f2699491SMichael Ellerman if (nmi) 1741f2699491SMichael Ellerman nmi_exit(); 1742f2699491SMichael Ellerman else 1743f2699491SMichael Ellerman irq_exit(); 1744f2699491SMichael Ellerman } 1745f2699491SMichael Ellerman 1746f2699491SMichael Ellerman static void power_pmu_setup(int cpu) 1747f2699491SMichael Ellerman { 1748f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 1749f2699491SMichael Ellerman 1750f2699491SMichael Ellerman if (!ppmu) 1751f2699491SMichael Ellerman return; 1752f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 1753f2699491SMichael Ellerman cpuhw->mmcr[0] = MMCR0_FC; 1754f2699491SMichael Ellerman } 1755f2699491SMichael Ellerman 1756f2699491SMichael Ellerman static int __cpuinit 1757f2699491SMichael Ellerman power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) 1758f2699491SMichael Ellerman { 1759f2699491SMichael Ellerman unsigned int cpu = (long)hcpu; 1760f2699491SMichael Ellerman 1761f2699491SMichael Ellerman switch (action & ~CPU_TASKS_FROZEN) { 1762f2699491SMichael Ellerman case CPU_UP_PREPARE: 1763f2699491SMichael Ellerman power_pmu_setup(cpu); 1764f2699491SMichael Ellerman break; 1765f2699491SMichael Ellerman 1766f2699491SMichael Ellerman default: 1767f2699491SMichael Ellerman break; 1768f2699491SMichael Ellerman } 1769f2699491SMichael Ellerman 1770f2699491SMichael Ellerman return NOTIFY_OK; 1771f2699491SMichael Ellerman } 1772f2699491SMichael Ellerman 1773f2699491SMichael Ellerman int __cpuinit register_power_pmu(struct power_pmu *pmu) 1774f2699491SMichael Ellerman { 1775f2699491SMichael Ellerman if (ppmu) 1776f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 1777f2699491SMichael Ellerman 1778f2699491SMichael Ellerman ppmu = pmu; 1779f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 1780f2699491SMichael Ellerman pmu->name); 1781f2699491SMichael Ellerman 17821c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 17831c53a270SSukadev Bhattiprolu 1784f2699491SMichael Ellerman #ifdef MSR_HV 1785f2699491SMichael Ellerman /* 1786f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 1787f2699491SMichael Ellerman */ 1788f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 1789f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 1790f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 1791f2699491SMichael Ellerman 1792f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 1793f2699491SMichael Ellerman perf_cpu_notifier(power_pmu_notifier); 1794f2699491SMichael Ellerman 1795f2699491SMichael Ellerman return 0; 1796f2699491SMichael Ellerman } 1797