1f2699491SMichael Ellerman /* 2f2699491SMichael Ellerman * Performance event support - powerpc architecture code 3f2699491SMichael Ellerman * 4f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5f2699491SMichael Ellerman * 6f2699491SMichael Ellerman * This program is free software; you can redistribute it and/or 7f2699491SMichael Ellerman * modify it under the terms of the GNU General Public License 8f2699491SMichael Ellerman * as published by the Free Software Foundation; either version 9f2699491SMichael Ellerman * 2 of the License, or (at your option) any later version. 10f2699491SMichael Ellerman */ 11f2699491SMichael Ellerman #include <linux/kernel.h> 12f2699491SMichael Ellerman #include <linux/sched.h> 13f2699491SMichael Ellerman #include <linux/perf_event.h> 14f2699491SMichael Ellerman #include <linux/percpu.h> 15f2699491SMichael Ellerman #include <linux/hardirq.h> 1669123184SMichael Neuling #include <linux/uaccess.h> 17f2699491SMichael Ellerman #include <asm/reg.h> 18f2699491SMichael Ellerman #include <asm/pmc.h> 19f2699491SMichael Ellerman #include <asm/machdep.h> 20f2699491SMichael Ellerman #include <asm/firmware.h> 21f2699491SMichael Ellerman #include <asm/ptrace.h> 2269123184SMichael Neuling #include <asm/code-patching.h> 23f2699491SMichael Ellerman 243925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 253925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 263925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 273925f46bSAnshuman Khandual #define BHRB_EA 0xFFFFFFFFFFFFFFFC 283925f46bSAnshuman Khandual 29f2699491SMichael Ellerman struct cpu_hw_events { 30f2699491SMichael Ellerman int n_events; 31f2699491SMichael Ellerman int n_percpu; 32f2699491SMichael Ellerman int disabled; 33f2699491SMichael Ellerman int n_added; 34f2699491SMichael Ellerman int n_limited; 35f2699491SMichael Ellerman u8 pmcs_enabled; 36f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 37f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 38f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 39f2699491SMichael Ellerman unsigned long mmcr[3]; 40f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 41f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 42f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 43f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 44f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 45f2699491SMichael Ellerman 46f2699491SMichael Ellerman unsigned int group_flag; 47f2699491SMichael Ellerman int n_txn_start; 483925f46bSAnshuman Khandual 493925f46bSAnshuman Khandual /* BHRB bits */ 503925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 513925f46bSAnshuman Khandual int bhrb_users; 523925f46bSAnshuman Khandual void *bhrb_context; 533925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 543925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 55f2699491SMichael Ellerman }; 563925f46bSAnshuman Khandual 57f2699491SMichael Ellerman DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 58f2699491SMichael Ellerman 59f2699491SMichael Ellerman struct power_pmu *ppmu; 60f2699491SMichael Ellerman 61f2699491SMichael Ellerman /* 62f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 63f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 64f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 65f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 66f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 67f2699491SMichael Ellerman */ 68f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 69f2699491SMichael Ellerman 70f2699491SMichael Ellerman /* 71f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 72f2699491SMichael Ellerman * and a few other names are different. 73f2699491SMichael Ellerman */ 74f2699491SMichael Ellerman #ifdef CONFIG_PPC32 75f2699491SMichael Ellerman 76f2699491SMichael Ellerman #define MMCR0_FCHV 0 77f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 787a7a41f9SMichael Ellerman #define MMCR0_FC56 0 79378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 80f2699491SMichael Ellerman 81f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 82f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 83f2699491SMichael Ellerman 84f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 85f2699491SMichael Ellerman { 86f2699491SMichael Ellerman return 0; 87f2699491SMichael Ellerman } 88f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 89f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 90f2699491SMichael Ellerman { 91f2699491SMichael Ellerman return 0; 92f2699491SMichael Ellerman } 9375382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 9475382aa7SAnton Blanchard { 9575382aa7SAnton Blanchard regs->result = 0; 9675382aa7SAnton Blanchard } 97f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 98f2699491SMichael Ellerman { 99f2699491SMichael Ellerman return 0; 100f2699491SMichael Ellerman } 101f2699491SMichael Ellerman 102e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 103e6878835Ssukadev@linux.vnet.ibm.com { 104e6878835Ssukadev@linux.vnet.ibm.com return 1; 105e6878835Ssukadev@linux.vnet.ibm.com } 106e6878835Ssukadev@linux.vnet.ibm.com 107d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 108d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 109d52f2dc4SMichael Neuling void power_pmu_flush_branch_stack(void) {} 110d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 111f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 112f2699491SMichael Ellerman 11333904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 11433904054SMichael Ellerman { 115cbda6aa1SMichael Ellerman return !!regs->result; 11633904054SMichael Ellerman } 11733904054SMichael Ellerman 118f2699491SMichael Ellerman /* 119f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 120f2699491SMichael Ellerman */ 121f2699491SMichael Ellerman #ifdef CONFIG_PPC64 122f2699491SMichael Ellerman 123f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 124f2699491SMichael Ellerman { 125f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 126f2699491SMichael Ellerman 1277a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 128f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 129f2699491SMichael Ellerman if (slot > 1) 130f2699491SMichael Ellerman return 4 * (slot - 1); 131f2699491SMichael Ellerman } 1327a786832SMichael Ellerman 133f2699491SMichael Ellerman return 0; 134f2699491SMichael Ellerman } 135f2699491SMichael Ellerman 136f2699491SMichael Ellerman /* 137f2699491SMichael Ellerman * The user wants a data address recorded. 138f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 139f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 140f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 14158a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 14258a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 143f2699491SMichael Ellerman */ 144f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 145f2699491SMichael Ellerman { 146f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 14758a032c3SMichael Ellerman bool sdar_valid; 14858a032c3SMichael Ellerman 14958a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 15058a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 15158a032c3SMichael Ellerman else { 152e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 153e6878835Ssukadev@linux.vnet.ibm.com 154e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 155e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 156e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 157e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 158e6878835Ssukadev@linux.vnet.ibm.com else 159e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 160f2699491SMichael Ellerman 16158a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 16258a032c3SMichael Ellerman } 16358a032c3SMichael Ellerman 16458a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 165f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 166f2699491SMichael Ellerman } 167f2699491SMichael Ellerman 1685682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 16968b30bb9SAnton Blanchard { 17068b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 17168b30bb9SAnton Blanchard 1728f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 1738f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 1748f61aa32SMichael Ellerman 17568b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 17668b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 17768b30bb9SAnton Blanchard 1785682c460SMichael Ellerman return !!(regs->dsisr & sihv); 17968b30bb9SAnton Blanchard } 18068b30bb9SAnton Blanchard 1815682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 18268b30bb9SAnton Blanchard { 18368b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 18468b30bb9SAnton Blanchard 1858f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 1868f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 1878f61aa32SMichael Ellerman 18868b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 18968b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 19068b30bb9SAnton Blanchard 1915682c460SMichael Ellerman return !!(regs->dsisr & sipr); 19268b30bb9SAnton Blanchard } 19368b30bb9SAnton Blanchard 1941ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 1951ce447b9SBenjamin Herrenschmidt { 1961ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 1971ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 1981ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 1991ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2001ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2011ce447b9SBenjamin Herrenschmidt } 2021ce447b9SBenjamin Herrenschmidt 203f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 204f2699491SMichael Ellerman { 20533904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 206f2699491SMichael Ellerman 20775382aa7SAnton Blanchard if (!use_siar) 2081ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2091ce447b9SBenjamin Herrenschmidt 2101ce447b9SBenjamin Herrenschmidt /* 2111ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2121ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2131ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2141ce447b9SBenjamin Herrenschmidt * results 2151ce447b9SBenjamin Herrenschmidt */ 216cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 2171ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 2181ce447b9SBenjamin Herrenschmidt if (siar >= PAGE_OFFSET) 2191ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2201ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2211ce447b9SBenjamin Herrenschmidt } 222f2699491SMichael Ellerman 223f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 2245682c460SMichael Ellerman if (regs_sipr(regs)) 225f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 2265682c460SMichael Ellerman 2275682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 228f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 2295682c460SMichael Ellerman 230f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 231f2699491SMichael Ellerman } 232f2699491SMichael Ellerman 233f2699491SMichael Ellerman /* 234f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 235f2699491SMichael Ellerman * on each interrupt. 2368f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 23775382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 23875382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 239f2699491SMichael Ellerman */ 240f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 241f2699491SMichael Ellerman { 24275382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 24375382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 24475382aa7SAnton Blanchard int use_siar; 24575382aa7SAnton Blanchard 2465682c460SMichael Ellerman regs->dsisr = mmcra; 247860aad71SMichael Ellerman 248cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2498f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 2508f61aa32SMichael Ellerman 2518f61aa32SMichael Ellerman /* 2525c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 2535c093efaSAnton Blanchard * not valid. Use pt_regs. 2545c093efaSAnton Blanchard * 2555c093efaSAnton Blanchard * If it is a marked event use the SIAR. 2565c093efaSAnton Blanchard * 2575c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 2585c093efaSAnton Blanchard * pt_regs. 2595c093efaSAnton Blanchard * 2605c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 2615c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 2625c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 2635c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 2645c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 2655c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 2665c093efaSAnton Blanchard * interrupts off hence the userspace check. 2675c093efaSAnton Blanchard */ 26875382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 26975382aa7SAnton Blanchard use_siar = 0; 2705c093efaSAnton Blanchard else if (marked) 2715c093efaSAnton Blanchard use_siar = 1; 2725c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 2735c093efaSAnton Blanchard use_siar = 0; 274cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 27575382aa7SAnton Blanchard use_siar = 0; 27675382aa7SAnton Blanchard else 27775382aa7SAnton Blanchard use_siar = 1; 27875382aa7SAnton Blanchard 279cbda6aa1SMichael Ellerman regs->result = use_siar; 280f2699491SMichael Ellerman } 281f2699491SMichael Ellerman 282f2699491SMichael Ellerman /* 283f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 284f2699491SMichael Ellerman * it as an NMI. 285f2699491SMichael Ellerman */ 286f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 287f2699491SMichael Ellerman { 288f2699491SMichael Ellerman return !regs->softe; 289f2699491SMichael Ellerman } 290f2699491SMichael Ellerman 291e6878835Ssukadev@linux.vnet.ibm.com /* 292e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 293e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 294e6878835Ssukadev@linux.vnet.ibm.com * 295e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 296e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 297e6878835Ssukadev@linux.vnet.ibm.com */ 298e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 299e6878835Ssukadev@linux.vnet.ibm.com { 300e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 301e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 302e6878835Ssukadev@linux.vnet.ibm.com 30358a032c3SMichael Ellerman if (marked) { 30458a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 30558a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 30658a032c3SMichael Ellerman 30758a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 308e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 30958a032c3SMichael Ellerman } 310e6878835Ssukadev@linux.vnet.ibm.com 311e6878835Ssukadev@linux.vnet.ibm.com return 1; 312e6878835Ssukadev@linux.vnet.ibm.com } 313e6878835Ssukadev@linux.vnet.ibm.com 314d52f2dc4SMichael Neuling 315d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 316d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 317d52f2dc4SMichael Neuling { 318d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 319d52f2dc4SMichael Neuling } 320d52f2dc4SMichael Neuling 321d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 322d52f2dc4SMichael Neuling { 323d52f2dc4SMichael Neuling struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 324d52f2dc4SMichael Neuling 325d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 326d52f2dc4SMichael Neuling return; 327d52f2dc4SMichael Neuling 328d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 329d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 330d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 331d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 332d52f2dc4SMichael Neuling } 333d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 334d52f2dc4SMichael Neuling } 335d52f2dc4SMichael Neuling 336d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 337d52f2dc4SMichael Neuling { 338d52f2dc4SMichael Neuling struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 339d52f2dc4SMichael Neuling 340d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 341d52f2dc4SMichael Neuling return; 342d52f2dc4SMichael Neuling 343d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 344d52f2dc4SMichael Neuling WARN_ON_ONCE(cpuhw->bhrb_users < 0); 345d52f2dc4SMichael Neuling 346d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 347d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 348d52f2dc4SMichael Neuling * events are active on the PMU. 349d52f2dc4SMichael Neuling */ 350d52f2dc4SMichael Neuling 351d52f2dc4SMichael Neuling /* avoid stale pointer */ 352d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 353d52f2dc4SMichael Neuling } 354d52f2dc4SMichael Neuling } 355d52f2dc4SMichael Neuling 356d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 357d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 358d52f2dc4SMichael Neuling */ 359d52f2dc4SMichael Neuling void power_pmu_flush_branch_stack(void) 360d52f2dc4SMichael Neuling { 361d52f2dc4SMichael Neuling if (ppmu->bhrb_nr) 362d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 363d52f2dc4SMichael Neuling } 36469123184SMichael Neuling /* Calculate the to address for a branch */ 36569123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 36669123184SMichael Neuling { 36769123184SMichael Neuling unsigned int instr; 36869123184SMichael Neuling int ret; 36969123184SMichael Neuling __u64 target; 37069123184SMichael Neuling 37169123184SMichael Neuling if (is_kernel_addr(addr)) 37269123184SMichael Neuling return branch_target((unsigned int *)addr); 37369123184SMichael Neuling 37469123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 37569123184SMichael Neuling pagefault_disable(); 37669123184SMichael Neuling ret = __get_user_inatomic(instr, (unsigned int __user *)addr); 37769123184SMichael Neuling if (ret) { 37869123184SMichael Neuling pagefault_enable(); 37969123184SMichael Neuling return 0; 38069123184SMichael Neuling } 38169123184SMichael Neuling pagefault_enable(); 38269123184SMichael Neuling 38369123184SMichael Neuling target = branch_target(&instr); 38469123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 38569123184SMichael Neuling return target; 38669123184SMichael Neuling 38769123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 38869123184SMichael Neuling return target - (unsigned long)&instr + addr; 38969123184SMichael Neuling } 390d52f2dc4SMichael Neuling 391d52f2dc4SMichael Neuling /* Processing BHRB entries */ 392506e70d1SMichael Neuling void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 393d52f2dc4SMichael Neuling { 394d52f2dc4SMichael Neuling u64 val; 395d52f2dc4SMichael Neuling u64 addr; 396506e70d1SMichael Neuling int r_index, u_index, pred; 397d52f2dc4SMichael Neuling 398d52f2dc4SMichael Neuling r_index = 0; 399d52f2dc4SMichael Neuling u_index = 0; 400d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 401d52f2dc4SMichael Neuling /* Assembly read function */ 402506e70d1SMichael Neuling val = read_bhrb(r_index++); 403506e70d1SMichael Neuling if (!val) 404d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 405d52f2dc4SMichael Neuling break; 406506e70d1SMichael Neuling else { 407d52f2dc4SMichael Neuling addr = val & BHRB_EA; 408d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 409d52f2dc4SMichael Neuling 410506e70d1SMichael Neuling if (!addr) 411506e70d1SMichael Neuling /* invalid entry */ 412d52f2dc4SMichael Neuling continue; 413d52f2dc4SMichael Neuling 414506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 415506e70d1SMichael Neuling * the most recent branch). 416506e70d1SMichael Neuling * There are two types of valid entries: 417506e70d1SMichael Neuling * 1) a target entry which is the to address of a 418506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 419506e70d1SMichael Neuling * entry read from the bhrb will be branch 420506e70d1SMichael Neuling * corresponding to this target (ie. the actual 421506e70d1SMichael Neuling * blr/bctr/btar instruction). 422506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 423506e70d1SMichael Neuling * target entry proceeds this, then this is the 424506e70d1SMichael Neuling * matching branch for that target. If this is not 425506e70d1SMichael Neuling * following a target entry, then this is a branch 426506e70d1SMichael Neuling * where the target is given as an immediate field 427506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 428506e70d1SMichael Neuling * In this case we need to read the instruction from 429506e70d1SMichael Neuling * memory to determine the target/to address. 430506e70d1SMichael Neuling */ 431d52f2dc4SMichael Neuling 432d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 433506e70d1SMichael Neuling /* Target branches use two entries 434506e70d1SMichael Neuling * (ie. computed gotos/XL form) 435506e70d1SMichael Neuling */ 436506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 437d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 438d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 439d52f2dc4SMichael Neuling 440506e70d1SMichael Neuling /* Get from address in next entry */ 441506e70d1SMichael Neuling val = read_bhrb(r_index++); 442506e70d1SMichael Neuling addr = val & BHRB_EA; 443506e70d1SMichael Neuling if (val & BHRB_TARGET) { 444506e70d1SMichael Neuling /* Shouldn't have two targets in a 445506e70d1SMichael Neuling row.. Reset index and try again */ 446506e70d1SMichael Neuling r_index--; 447506e70d1SMichael Neuling addr = 0; 448d52f2dc4SMichael Neuling } 449506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 450506e70d1SMichael Neuling } else { 451506e70d1SMichael Neuling /* Branches to immediate field 452506e70d1SMichael Neuling (ie I or B form) */ 453506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 45469123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 45569123184SMichael Neuling power_pmu_bhrb_to(addr); 456506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 457506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 458506e70d1SMichael Neuling } 459506e70d1SMichael Neuling u_index++; 460506e70d1SMichael Neuling 461d52f2dc4SMichael Neuling } 462d52f2dc4SMichael Neuling } 463d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 464d52f2dc4SMichael Neuling return; 465d52f2dc4SMichael Neuling } 466d52f2dc4SMichael Neuling 467f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 468f2699491SMichael Ellerman 469f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 470f2699491SMichael Ellerman 471f2699491SMichael Ellerman void perf_event_print_debug(void) 472f2699491SMichael Ellerman { 473f2699491SMichael Ellerman } 474f2699491SMichael Ellerman 475f2699491SMichael Ellerman /* 476f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 477f2699491SMichael Ellerman */ 478f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 479f2699491SMichael Ellerman { 480f2699491SMichael Ellerman unsigned long val; 481f2699491SMichael Ellerman 482f2699491SMichael Ellerman switch (idx) { 483f2699491SMichael Ellerman case 1: 484f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 485f2699491SMichael Ellerman break; 486f2699491SMichael Ellerman case 2: 487f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 488f2699491SMichael Ellerman break; 489f2699491SMichael Ellerman case 3: 490f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 491f2699491SMichael Ellerman break; 492f2699491SMichael Ellerman case 4: 493f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 494f2699491SMichael Ellerman break; 495f2699491SMichael Ellerman case 5: 496f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 497f2699491SMichael Ellerman break; 498f2699491SMichael Ellerman case 6: 499f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 500f2699491SMichael Ellerman break; 501f2699491SMichael Ellerman #ifdef CONFIG_PPC64 502f2699491SMichael Ellerman case 7: 503f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 504f2699491SMichael Ellerman break; 505f2699491SMichael Ellerman case 8: 506f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 507f2699491SMichael Ellerman break; 508f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 509f2699491SMichael Ellerman default: 510f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 511f2699491SMichael Ellerman val = 0; 512f2699491SMichael Ellerman } 513f2699491SMichael Ellerman return val; 514f2699491SMichael Ellerman } 515f2699491SMichael Ellerman 516f2699491SMichael Ellerman /* 517f2699491SMichael Ellerman * Write one PMC. 518f2699491SMichael Ellerman */ 519f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 520f2699491SMichael Ellerman { 521f2699491SMichael Ellerman switch (idx) { 522f2699491SMichael Ellerman case 1: 523f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 524f2699491SMichael Ellerman break; 525f2699491SMichael Ellerman case 2: 526f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 527f2699491SMichael Ellerman break; 528f2699491SMichael Ellerman case 3: 529f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 530f2699491SMichael Ellerman break; 531f2699491SMichael Ellerman case 4: 532f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 533f2699491SMichael Ellerman break; 534f2699491SMichael Ellerman case 5: 535f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 536f2699491SMichael Ellerman break; 537f2699491SMichael Ellerman case 6: 538f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 539f2699491SMichael Ellerman break; 540f2699491SMichael Ellerman #ifdef CONFIG_PPC64 541f2699491SMichael Ellerman case 7: 542f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 543f2699491SMichael Ellerman break; 544f2699491SMichael Ellerman case 8: 545f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 546f2699491SMichael Ellerman break; 547f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 548f2699491SMichael Ellerman default: 549f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 550f2699491SMichael Ellerman } 551f2699491SMichael Ellerman } 552f2699491SMichael Ellerman 553f2699491SMichael Ellerman /* 554f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 555f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 556f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 557f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 558f2699491SMichael Ellerman */ 559f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 560f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 561f2699491SMichael Ellerman int n_ev) 562f2699491SMichael Ellerman { 563f2699491SMichael Ellerman unsigned long mask, value, nv; 564f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 565f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 566f2699491SMichael Ellerman int i, j; 567f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 568f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 569f2699491SMichael Ellerman 570f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 571f2699491SMichael Ellerman return -1; 572f2699491SMichael Ellerman 573f2699491SMichael Ellerman /* First see if the events will go on as-is */ 574f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 575f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 576f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 577f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 578f2699491SMichael Ellerman cpuhw->alternatives[i]); 579f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 580f2699491SMichael Ellerman } 581f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 582f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 583f2699491SMichael Ellerman return -1; 584f2699491SMichael Ellerman } 585f2699491SMichael Ellerman value = mask = 0; 586f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 587f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 588f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 589f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) != 0 || 590f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][0]) & 591f2699491SMichael Ellerman cpuhw->amasks[i][0]) != 0) 592f2699491SMichael Ellerman break; 593f2699491SMichael Ellerman value = nv; 594f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 595f2699491SMichael Ellerman } 596f2699491SMichael Ellerman if (i == n_ev) 597f2699491SMichael Ellerman return 0; /* all OK */ 598f2699491SMichael Ellerman 599f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 600f2699491SMichael Ellerman if (!ppmu->get_alternatives) 601f2699491SMichael Ellerman return -1; 602f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 603f2699491SMichael Ellerman choice[i] = 0; 604f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 605f2699491SMichael Ellerman cpuhw->alternatives[i]); 606f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 607f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 608f2699491SMichael Ellerman &cpuhw->amasks[i][j], 609f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 610f2699491SMichael Ellerman } 611f2699491SMichael Ellerman 612f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 613f2699491SMichael Ellerman i = 0; 614f2699491SMichael Ellerman j = -1; 615f2699491SMichael Ellerman value = mask = nv = 0; 616f2699491SMichael Ellerman while (i < n_ev) { 617f2699491SMichael Ellerman if (j >= 0) { 618f2699491SMichael Ellerman /* we're backtracking, restore context */ 619f2699491SMichael Ellerman value = svalues[i]; 620f2699491SMichael Ellerman mask = smasks[i]; 621f2699491SMichael Ellerman j = choice[i]; 622f2699491SMichael Ellerman } 623f2699491SMichael Ellerman /* 624f2699491SMichael Ellerman * See if any alternative k for event_id i, 625f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 626f2699491SMichael Ellerman */ 627f2699491SMichael Ellerman while (++j < n_alt[i]) { 628f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 629f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 630f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 631f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 632f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 633f2699491SMichael Ellerman break; 634f2699491SMichael Ellerman } 635f2699491SMichael Ellerman if (j >= n_alt[i]) { 636f2699491SMichael Ellerman /* 637f2699491SMichael Ellerman * No feasible alternative, backtrack 638f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 639f2699491SMichael Ellerman * alternatives from where we got up to. 640f2699491SMichael Ellerman */ 641f2699491SMichael Ellerman if (--i < 0) 642f2699491SMichael Ellerman return -1; 643f2699491SMichael Ellerman } else { 644f2699491SMichael Ellerman /* 645f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 646f2699491SMichael Ellerman * remember where we got up to with this event_id, 647f2699491SMichael Ellerman * go on to the next event_id, and start with 648f2699491SMichael Ellerman * the first alternative for it. 649f2699491SMichael Ellerman */ 650f2699491SMichael Ellerman choice[i] = j; 651f2699491SMichael Ellerman svalues[i] = value; 652f2699491SMichael Ellerman smasks[i] = mask; 653f2699491SMichael Ellerman value = nv; 654f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 655f2699491SMichael Ellerman ++i; 656f2699491SMichael Ellerman j = -1; 657f2699491SMichael Ellerman } 658f2699491SMichael Ellerman } 659f2699491SMichael Ellerman 660f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 661f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 662f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 663f2699491SMichael Ellerman return 0; 664f2699491SMichael Ellerman } 665f2699491SMichael Ellerman 666f2699491SMichael Ellerman /* 667f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 668f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 669f2699491SMichael Ellerman * added events. 670f2699491SMichael Ellerman */ 671f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 672f2699491SMichael Ellerman int n_prev, int n_new) 673f2699491SMichael Ellerman { 674f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 675f2699491SMichael Ellerman int i, n, first; 676f2699491SMichael Ellerman struct perf_event *event; 677f2699491SMichael Ellerman 678f2699491SMichael Ellerman n = n_prev + n_new; 679f2699491SMichael Ellerman if (n <= 1) 680f2699491SMichael Ellerman return 0; 681f2699491SMichael Ellerman 682f2699491SMichael Ellerman first = 1; 683f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 684f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 685f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 686f2699491SMichael Ellerman continue; 687f2699491SMichael Ellerman } 688f2699491SMichael Ellerman event = ctrs[i]; 689f2699491SMichael Ellerman if (first) { 690f2699491SMichael Ellerman eu = event->attr.exclude_user; 691f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 692f2699491SMichael Ellerman eh = event->attr.exclude_hv; 693f2699491SMichael Ellerman first = 0; 694f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 695f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 696f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 697f2699491SMichael Ellerman return -EAGAIN; 698f2699491SMichael Ellerman } 699f2699491SMichael Ellerman } 700f2699491SMichael Ellerman 701f2699491SMichael Ellerman if (eu || ek || eh) 702f2699491SMichael Ellerman for (i = 0; i < n; ++i) 703f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 704f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 705f2699491SMichael Ellerman 706f2699491SMichael Ellerman return 0; 707f2699491SMichael Ellerman } 708f2699491SMichael Ellerman 709f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 710f2699491SMichael Ellerman { 711f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 712f2699491SMichael Ellerman 713f2699491SMichael Ellerman /* 714f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 715f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 716f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 717f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 718f2699491SMichael Ellerman * number of events to rollback at once. If we dectect a rollback 719f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 720f2699491SMichael Ellerman * counters. 721f2699491SMichael Ellerman */ 722f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 723f2699491SMichael Ellerman delta = 0; 724f2699491SMichael Ellerman 725f2699491SMichael Ellerman return delta; 726f2699491SMichael Ellerman } 727f2699491SMichael Ellerman 728f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 729f2699491SMichael Ellerman { 730f2699491SMichael Ellerman s64 val, delta, prev; 731f2699491SMichael Ellerman 732f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 733f2699491SMichael Ellerman return; 734f2699491SMichael Ellerman 735f2699491SMichael Ellerman if (!event->hw.idx) 736f2699491SMichael Ellerman return; 737f2699491SMichael Ellerman /* 738f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 739f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 740f2699491SMichael Ellerman * Therefore we treat them like NMIs. 741f2699491SMichael Ellerman */ 742f2699491SMichael Ellerman do { 743f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 744f2699491SMichael Ellerman barrier(); 745f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 746f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 747f2699491SMichael Ellerman if (!delta) 748f2699491SMichael Ellerman return; 749f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 750f2699491SMichael Ellerman 751f2699491SMichael Ellerman local64_add(delta, &event->count); 752f2699491SMichael Ellerman local64_sub(delta, &event->hw.period_left); 753f2699491SMichael Ellerman } 754f2699491SMichael Ellerman 755f2699491SMichael Ellerman /* 756f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 757f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 758f2699491SMichael Ellerman * us if `event' is using such a PMC. 759f2699491SMichael Ellerman */ 760f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 761f2699491SMichael Ellerman { 762f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 763f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 764f2699491SMichael Ellerman } 765f2699491SMichael Ellerman 766f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 767f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 768f2699491SMichael Ellerman { 769f2699491SMichael Ellerman struct perf_event *event; 770f2699491SMichael Ellerman u64 val, prev, delta; 771f2699491SMichael Ellerman int i; 772f2699491SMichael Ellerman 773f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 774f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 775f2699491SMichael Ellerman if (!event->hw.idx) 776f2699491SMichael Ellerman continue; 777f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 778f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 779f2699491SMichael Ellerman event->hw.idx = 0; 780f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 781f2699491SMichael Ellerman if (delta) 782f2699491SMichael Ellerman local64_add(delta, &event->count); 783f2699491SMichael Ellerman } 784f2699491SMichael Ellerman } 785f2699491SMichael Ellerman 786f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 787f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 788f2699491SMichael Ellerman { 789f2699491SMichael Ellerman struct perf_event *event; 790f2699491SMichael Ellerman u64 val, prev; 791f2699491SMichael Ellerman int i; 792f2699491SMichael Ellerman 793f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 794f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 795f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 796f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 797f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 798f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 799f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 800f2699491SMichael Ellerman perf_event_update_userpage(event); 801f2699491SMichael Ellerman } 802f2699491SMichael Ellerman } 803f2699491SMichael Ellerman 804f2699491SMichael Ellerman /* 805f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 806f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 807f2699491SMichael Ellerman * other events. We try to keep the values from the limited 808f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 809f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 810f2699491SMichael Ellerman * the limited events as small and consistent as possible. 811f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 812f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 813f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 814f2699491SMichael Ellerman */ 815f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 816f2699491SMichael Ellerman { 817f2699491SMichael Ellerman unsigned long pmc5, pmc6; 818f2699491SMichael Ellerman 819f2699491SMichael Ellerman if (!cpuhw->n_limited) { 820f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 821f2699491SMichael Ellerman return; 822f2699491SMichael Ellerman } 823f2699491SMichael Ellerman 824f2699491SMichael Ellerman /* 825f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 826f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 827f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 828f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 829f2699491SMichael Ellerman * interrupt enable bits turned off. 830f2699491SMichael Ellerman */ 831f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 832f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 833f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 834f2699491SMichael Ellerman "i" (SPRN_MMCR0), 835f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 836f2699491SMichael Ellerman 837f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 838f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 839f2699491SMichael Ellerman else 840f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 841f2699491SMichael Ellerman 842f2699491SMichael Ellerman /* 843f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 844f2699491SMichael Ellerman * enable bits, if necessary. 845f2699491SMichael Ellerman */ 846f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 847f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 848f2699491SMichael Ellerman } 849f2699491SMichael Ellerman 850f2699491SMichael Ellerman /* 851f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 852f2699491SMichael Ellerman * events to be added or removed. 853f2699491SMichael Ellerman */ 854f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 855f2699491SMichael Ellerman { 856f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 857378a6ee9SMichael Ellerman unsigned long flags, val; 858f2699491SMichael Ellerman 859f2699491SMichael Ellerman if (!ppmu) 860f2699491SMichael Ellerman return; 861f2699491SMichael Ellerman local_irq_save(flags); 862f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 863f2699491SMichael Ellerman 864f2699491SMichael Ellerman if (!cpuhw->disabled) { 865f2699491SMichael Ellerman /* 866f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 867f2699491SMichael Ellerman */ 868f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 869f2699491SMichael Ellerman ppc_enable_pmcs(); 870f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 871f2699491SMichael Ellerman } 872f2699491SMichael Ellerman 873f2699491SMichael Ellerman /* 8747a7a41f9SMichael Ellerman * Set the 'freeze counters' bit, clear PMAO/FC56. 875378a6ee9SMichael Ellerman */ 876378a6ee9SMichael Ellerman val = mfspr(SPRN_MMCR0); 877378a6ee9SMichael Ellerman val |= MMCR0_FC; 8787a7a41f9SMichael Ellerman val &= ~(MMCR0_PMAO | MMCR0_FC56); 879378a6ee9SMichael Ellerman 880378a6ee9SMichael Ellerman /* 881378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 882378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 883378a6ee9SMichael Ellerman * before we return. 884378a6ee9SMichael Ellerman */ 885378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 886378a6ee9SMichael Ellerman mb(); 887378a6ee9SMichael Ellerman 888378a6ee9SMichael Ellerman /* 889f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 890f2699491SMichael Ellerman */ 891f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 892f2699491SMichael Ellerman mtspr(SPRN_MMCRA, 893f2699491SMichael Ellerman cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 894f2699491SMichael Ellerman mb(); 895f2699491SMichael Ellerman } 896f2699491SMichael Ellerman 897378a6ee9SMichael Ellerman cpuhw->disabled = 1; 898378a6ee9SMichael Ellerman cpuhw->n_added = 0; 899f2699491SMichael Ellerman } 900f2699491SMichael Ellerman local_irq_restore(flags); 901f2699491SMichael Ellerman } 902f2699491SMichael Ellerman 903f2699491SMichael Ellerman /* 904f2699491SMichael Ellerman * Re-enable all events if disable == 0. 905f2699491SMichael Ellerman * If we were previously disabled and events were added, then 906f2699491SMichael Ellerman * put the new config on the PMU. 907f2699491SMichael Ellerman */ 908f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 909f2699491SMichael Ellerman { 910f2699491SMichael Ellerman struct perf_event *event; 911f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 912f2699491SMichael Ellerman unsigned long flags; 913f2699491SMichael Ellerman long i; 914f2699491SMichael Ellerman unsigned long val; 915f2699491SMichael Ellerman s64 left; 916f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 917f2699491SMichael Ellerman int n_lim; 918f2699491SMichael Ellerman int idx; 919f2699491SMichael Ellerman 920f2699491SMichael Ellerman if (!ppmu) 921f2699491SMichael Ellerman return; 9220a48843dSMichael Ellerman 923f2699491SMichael Ellerman local_irq_save(flags); 9240a48843dSMichael Ellerman 925f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 9260a48843dSMichael Ellerman if (!cpuhw->disabled) 9270a48843dSMichael Ellerman goto out; 9280a48843dSMichael Ellerman 929f2699491SMichael Ellerman cpuhw->disabled = 0; 930f2699491SMichael Ellerman 931f2699491SMichael Ellerman /* 932f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 933f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 934f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 935f2699491SMichael Ellerman * (possibly updated for removal of events). 936f2699491SMichael Ellerman */ 937f2699491SMichael Ellerman if (!cpuhw->n_added) { 938f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 939f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 940f2699491SMichael Ellerman if (cpuhw->n_events == 0) 941f2699491SMichael Ellerman ppc_set_pmu_inuse(0); 942f2699491SMichael Ellerman goto out_enable; 943f2699491SMichael Ellerman } 944f2699491SMichael Ellerman 945f2699491SMichael Ellerman /* 946f2699491SMichael Ellerman * Compute MMCR* values for the new set of events 947f2699491SMichael Ellerman */ 948f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 949f2699491SMichael Ellerman cpuhw->mmcr)) { 950f2699491SMichael Ellerman /* shouldn't ever get here */ 951f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 952f2699491SMichael Ellerman goto out; 953f2699491SMichael Ellerman } 954f2699491SMichael Ellerman 955f2699491SMichael Ellerman /* 956f2699491SMichael Ellerman * Add in MMCR0 freeze bits corresponding to the 957f2699491SMichael Ellerman * attr.exclude_* bits for the first event. 958f2699491SMichael Ellerman * We have already checked that all events have the 959f2699491SMichael Ellerman * same values for these bits as the first event. 960f2699491SMichael Ellerman */ 961f2699491SMichael Ellerman event = cpuhw->event[0]; 962f2699491SMichael Ellerman if (event->attr.exclude_user) 963f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCP; 964f2699491SMichael Ellerman if (event->attr.exclude_kernel) 965f2699491SMichael Ellerman cpuhw->mmcr[0] |= freeze_events_kernel; 966f2699491SMichael Ellerman if (event->attr.exclude_hv) 967f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCHV; 968f2699491SMichael Ellerman 969f2699491SMichael Ellerman /* 970f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 971f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 972f2699491SMichael Ellerman * Then unfreeze the events. 973f2699491SMichael Ellerman */ 974f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 975f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 976f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 977f2699491SMichael Ellerman mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 978f2699491SMichael Ellerman | MMCR0_FC); 979f2699491SMichael Ellerman 980f2699491SMichael Ellerman /* 981f2699491SMichael Ellerman * Read off any pre-existing events that need to move 982f2699491SMichael Ellerman * to another PMC. 983f2699491SMichael Ellerman */ 984f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 985f2699491SMichael Ellerman event = cpuhw->event[i]; 986f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 987f2699491SMichael Ellerman power_pmu_read(event); 988f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 989f2699491SMichael Ellerman event->hw.idx = 0; 990f2699491SMichael Ellerman } 991f2699491SMichael Ellerman } 992f2699491SMichael Ellerman 993f2699491SMichael Ellerman /* 994f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 995f2699491SMichael Ellerman */ 996f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 997f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 998f2699491SMichael Ellerman event = cpuhw->event[i]; 999f2699491SMichael Ellerman if (event->hw.idx) 1000f2699491SMichael Ellerman continue; 1001f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1002f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1003f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1004f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1005f2699491SMichael Ellerman ++n_lim; 1006f2699491SMichael Ellerman continue; 1007f2699491SMichael Ellerman } 1008f2699491SMichael Ellerman val = 0; 1009f2699491SMichael Ellerman if (event->hw.sample_period) { 1010f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1011f2699491SMichael Ellerman if (left < 0x80000000L) 1012f2699491SMichael Ellerman val = 0x80000000L - left; 1013f2699491SMichael Ellerman } 1014f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1015f2699491SMichael Ellerman event->hw.idx = idx; 1016f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1017f2699491SMichael Ellerman val = 0; 1018f2699491SMichael Ellerman write_pmc(idx, val); 1019f2699491SMichael Ellerman perf_event_update_userpage(event); 1020f2699491SMichael Ellerman } 1021f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 1022f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 1023f2699491SMichael Ellerman 1024f2699491SMichael Ellerman out_enable: 1025f2699491SMichael Ellerman mb(); 1026f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 1027f2699491SMichael Ellerman 1028f2699491SMichael Ellerman /* 1029f2699491SMichael Ellerman * Enable instruction sampling if necessary 1030f2699491SMichael Ellerman */ 1031f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1032f2699491SMichael Ellerman mb(); 1033f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 1034f2699491SMichael Ellerman } 1035f2699491SMichael Ellerman 1036f2699491SMichael Ellerman out: 10373925f46bSAnshuman Khandual if (cpuhw->bhrb_users) 10383925f46bSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 10393925f46bSAnshuman Khandual 1040f2699491SMichael Ellerman local_irq_restore(flags); 1041f2699491SMichael Ellerman } 1042f2699491SMichael Ellerman 1043f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1044f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1045f2699491SMichael Ellerman unsigned int *flags) 1046f2699491SMichael Ellerman { 1047f2699491SMichael Ellerman int n = 0; 1048f2699491SMichael Ellerman struct perf_event *event; 1049f2699491SMichael Ellerman 1050f2699491SMichael Ellerman if (!is_software_event(group)) { 1051f2699491SMichael Ellerman if (n >= max_count) 1052f2699491SMichael Ellerman return -1; 1053f2699491SMichael Ellerman ctrs[n] = group; 1054f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1055f2699491SMichael Ellerman events[n++] = group->hw.config; 1056f2699491SMichael Ellerman } 1057f2699491SMichael Ellerman list_for_each_entry(event, &group->sibling_list, group_entry) { 1058f2699491SMichael Ellerman if (!is_software_event(event) && 1059f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1060f2699491SMichael Ellerman if (n >= max_count) 1061f2699491SMichael Ellerman return -1; 1062f2699491SMichael Ellerman ctrs[n] = event; 1063f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1064f2699491SMichael Ellerman events[n++] = event->hw.config; 1065f2699491SMichael Ellerman } 1066f2699491SMichael Ellerman } 1067f2699491SMichael Ellerman return n; 1068f2699491SMichael Ellerman } 1069f2699491SMichael Ellerman 1070f2699491SMichael Ellerman /* 1071f2699491SMichael Ellerman * Add a event to the PMU. 1072f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1073f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1074f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1075f2699491SMichael Ellerman */ 1076f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1077f2699491SMichael Ellerman { 1078f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1079f2699491SMichael Ellerman unsigned long flags; 1080f2699491SMichael Ellerman int n0; 1081f2699491SMichael Ellerman int ret = -EAGAIN; 1082f2699491SMichael Ellerman 1083f2699491SMichael Ellerman local_irq_save(flags); 1084f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1085f2699491SMichael Ellerman 1086f2699491SMichael Ellerman /* 1087f2699491SMichael Ellerman * Add the event to the list (if there is room) 1088f2699491SMichael Ellerman * and check whether the total set is still feasible. 1089f2699491SMichael Ellerman */ 1090f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1091f2699491SMichael Ellerman n0 = cpuhw->n_events; 1092f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1093f2699491SMichael Ellerman goto out; 1094f2699491SMichael Ellerman cpuhw->event[n0] = event; 1095f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1096f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1097f2699491SMichael Ellerman 1098f53d168cSsukadev@linux.vnet.ibm.com /* 1099f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1100f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1101f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1102f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1103f53d168cSsukadev@linux.vnet.ibm.com */ 1104f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1105f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1106f53d168cSsukadev@linux.vnet.ibm.com else 1107f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1108f2699491SMichael Ellerman 1109f2699491SMichael Ellerman /* 1110f2699491SMichael Ellerman * If group events scheduling transaction was started, 1111f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1112f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1113f2699491SMichael Ellerman */ 1114f2699491SMichael Ellerman if (cpuhw->group_flag & PERF_EVENT_TXN) 1115f2699491SMichael Ellerman goto nocheck; 1116f2699491SMichael Ellerman 1117f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1118f2699491SMichael Ellerman goto out; 1119f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1120f2699491SMichael Ellerman goto out; 1121f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1122f2699491SMichael Ellerman 1123f2699491SMichael Ellerman nocheck: 1124f2699491SMichael Ellerman ++cpuhw->n_events; 1125f2699491SMichael Ellerman ++cpuhw->n_added; 1126f2699491SMichael Ellerman 1127f2699491SMichael Ellerman ret = 0; 1128f2699491SMichael Ellerman out: 11293925f46bSAnshuman Khandual if (has_branch_stack(event)) 11303925f46bSAnshuman Khandual power_pmu_bhrb_enable(event); 11313925f46bSAnshuman Khandual 1132f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1133f2699491SMichael Ellerman local_irq_restore(flags); 1134f2699491SMichael Ellerman return ret; 1135f2699491SMichael Ellerman } 1136f2699491SMichael Ellerman 1137f2699491SMichael Ellerman /* 1138f2699491SMichael Ellerman * Remove a event from the PMU. 1139f2699491SMichael Ellerman */ 1140f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1141f2699491SMichael Ellerman { 1142f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1143f2699491SMichael Ellerman long i; 1144f2699491SMichael Ellerman unsigned long flags; 1145f2699491SMichael Ellerman 1146f2699491SMichael Ellerman local_irq_save(flags); 1147f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1148f2699491SMichael Ellerman 1149f2699491SMichael Ellerman power_pmu_read(event); 1150f2699491SMichael Ellerman 1151f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1152f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1153f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1154f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1155f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1156f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1157f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1158f2699491SMichael Ellerman } 1159f2699491SMichael Ellerman --cpuhw->n_events; 1160f2699491SMichael Ellerman ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1161f2699491SMichael Ellerman if (event->hw.idx) { 1162f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1163f2699491SMichael Ellerman event->hw.idx = 0; 1164f2699491SMichael Ellerman } 1165f2699491SMichael Ellerman perf_event_update_userpage(event); 1166f2699491SMichael Ellerman break; 1167f2699491SMichael Ellerman } 1168f2699491SMichael Ellerman } 1169f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1170f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1171f2699491SMichael Ellerman break; 1172f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1173f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1174f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1175f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1176f2699491SMichael Ellerman } 1177f2699491SMichael Ellerman --cpuhw->n_limited; 1178f2699491SMichael Ellerman } 1179f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1180f2699491SMichael Ellerman /* disable exceptions if no events are running */ 1181f2699491SMichael Ellerman cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1182f2699491SMichael Ellerman } 1183f2699491SMichael Ellerman 11843925f46bSAnshuman Khandual if (has_branch_stack(event)) 11853925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 11863925f46bSAnshuman Khandual 1187f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1188f2699491SMichael Ellerman local_irq_restore(flags); 1189f2699491SMichael Ellerman } 1190f2699491SMichael Ellerman 1191f2699491SMichael Ellerman /* 1192f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1193f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1194f2699491SMichael Ellerman */ 1195f2699491SMichael Ellerman 1196f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1197f2699491SMichael Ellerman { 1198f2699491SMichael Ellerman unsigned long flags; 1199f2699491SMichael Ellerman s64 left; 1200f2699491SMichael Ellerman unsigned long val; 1201f2699491SMichael Ellerman 1202f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1203f2699491SMichael Ellerman return; 1204f2699491SMichael Ellerman 1205f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1206f2699491SMichael Ellerman return; 1207f2699491SMichael Ellerman 1208f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1209f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1210f2699491SMichael Ellerman 1211f2699491SMichael Ellerman local_irq_save(flags); 1212f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1213f2699491SMichael Ellerman 1214f2699491SMichael Ellerman event->hw.state = 0; 1215f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1216f2699491SMichael Ellerman 1217f2699491SMichael Ellerman val = 0; 1218f2699491SMichael Ellerman if (left < 0x80000000L) 1219f2699491SMichael Ellerman val = 0x80000000L - left; 1220f2699491SMichael Ellerman 1221f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1222f2699491SMichael Ellerman 1223f2699491SMichael Ellerman perf_event_update_userpage(event); 1224f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1225f2699491SMichael Ellerman local_irq_restore(flags); 1226f2699491SMichael Ellerman } 1227f2699491SMichael Ellerman 1228f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1229f2699491SMichael Ellerman { 1230f2699491SMichael Ellerman unsigned long flags; 1231f2699491SMichael Ellerman 1232f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1233f2699491SMichael Ellerman return; 1234f2699491SMichael Ellerman 1235f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1236f2699491SMichael Ellerman return; 1237f2699491SMichael Ellerman 1238f2699491SMichael Ellerman local_irq_save(flags); 1239f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1240f2699491SMichael Ellerman 1241f2699491SMichael Ellerman power_pmu_read(event); 1242f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1243f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1244f2699491SMichael Ellerman 1245f2699491SMichael Ellerman perf_event_update_userpage(event); 1246f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1247f2699491SMichael Ellerman local_irq_restore(flags); 1248f2699491SMichael Ellerman } 1249f2699491SMichael Ellerman 1250f2699491SMichael Ellerman /* 1251f2699491SMichael Ellerman * Start group events scheduling transaction 1252f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1253f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1254f2699491SMichael Ellerman */ 1255f2699491SMichael Ellerman void power_pmu_start_txn(struct pmu *pmu) 1256f2699491SMichael Ellerman { 1257f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1258f2699491SMichael Ellerman 1259f2699491SMichael Ellerman perf_pmu_disable(pmu); 1260f2699491SMichael Ellerman cpuhw->group_flag |= PERF_EVENT_TXN; 1261f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1262f2699491SMichael Ellerman } 1263f2699491SMichael Ellerman 1264f2699491SMichael Ellerman /* 1265f2699491SMichael Ellerman * Stop group events scheduling transaction 1266f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1267f2699491SMichael Ellerman * schedulability test. 1268f2699491SMichael Ellerman */ 1269f2699491SMichael Ellerman void power_pmu_cancel_txn(struct pmu *pmu) 1270f2699491SMichael Ellerman { 1271f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1272f2699491SMichael Ellerman 1273f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1274f2699491SMichael Ellerman perf_pmu_enable(pmu); 1275f2699491SMichael Ellerman } 1276f2699491SMichael Ellerman 1277f2699491SMichael Ellerman /* 1278f2699491SMichael Ellerman * Commit group events scheduling transaction 1279f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1280f2699491SMichael Ellerman * Return 0 if success 1281f2699491SMichael Ellerman */ 1282f2699491SMichael Ellerman int power_pmu_commit_txn(struct pmu *pmu) 1283f2699491SMichael Ellerman { 1284f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1285f2699491SMichael Ellerman long i, n; 1286f2699491SMichael Ellerman 1287f2699491SMichael Ellerman if (!ppmu) 1288f2699491SMichael Ellerman return -EAGAIN; 1289f2699491SMichael Ellerman cpuhw = &__get_cpu_var(cpu_hw_events); 1290f2699491SMichael Ellerman n = cpuhw->n_events; 1291f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1292f2699491SMichael Ellerman return -EAGAIN; 1293f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1294f2699491SMichael Ellerman if (i < 0) 1295f2699491SMichael Ellerman return -EAGAIN; 1296f2699491SMichael Ellerman 1297f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1298f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1299f2699491SMichael Ellerman 1300f2699491SMichael Ellerman cpuhw->group_flag &= ~PERF_EVENT_TXN; 1301f2699491SMichael Ellerman perf_pmu_enable(pmu); 1302f2699491SMichael Ellerman return 0; 1303f2699491SMichael Ellerman } 1304f2699491SMichael Ellerman 1305f2699491SMichael Ellerman /* 1306f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1307f2699491SMichael Ellerman * or 0 if not. 1308f2699491SMichael Ellerman * A event can only go on a limited PMC if it counts something 1309f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1310f2699491SMichael Ellerman * doesn't exclude any processor mode. 1311f2699491SMichael Ellerman */ 1312f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1313f2699491SMichael Ellerman unsigned int flags) 1314f2699491SMichael Ellerman { 1315f2699491SMichael Ellerman int n; 1316f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1317f2699491SMichael Ellerman 1318f2699491SMichael Ellerman if (event->attr.exclude_user 1319f2699491SMichael Ellerman || event->attr.exclude_kernel 1320f2699491SMichael Ellerman || event->attr.exclude_hv 1321f2699491SMichael Ellerman || event->attr.sample_period) 1322f2699491SMichael Ellerman return 0; 1323f2699491SMichael Ellerman 1324f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1325f2699491SMichael Ellerman return 1; 1326f2699491SMichael Ellerman 1327f2699491SMichael Ellerman /* 1328f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1329f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1330f2699491SMichael Ellerman */ 1331f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1332f2699491SMichael Ellerman return 0; 1333f2699491SMichael Ellerman 1334f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1335f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1336f2699491SMichael Ellerman 1337f2699491SMichael Ellerman return n > 0; 1338f2699491SMichael Ellerman } 1339f2699491SMichael Ellerman 1340f2699491SMichael Ellerman /* 1341f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1342f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1343f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1344f2699491SMichael Ellerman */ 1345f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1346f2699491SMichael Ellerman { 1347f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1348f2699491SMichael Ellerman int n; 1349f2699491SMichael Ellerman 1350f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1351f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1352f2699491SMichael Ellerman if (!n) 1353f2699491SMichael Ellerman return 0; 1354f2699491SMichael Ellerman return alt[0]; 1355f2699491SMichael Ellerman } 1356f2699491SMichael Ellerman 1357f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1358f2699491SMichael Ellerman static atomic_t num_events; 1359f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1360f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1361f2699491SMichael Ellerman 1362f2699491SMichael Ellerman /* 1363f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1364f2699491SMichael Ellerman */ 1365f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1366f2699491SMichael Ellerman { 1367f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1368f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1369f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1370f2699491SMichael Ellerman release_pmc_hardware(); 1371f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1372f2699491SMichael Ellerman } 1373f2699491SMichael Ellerman } 1374f2699491SMichael Ellerman 1375f2699491SMichael Ellerman /* 1376f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1377f2699491SMichael Ellerman */ 1378f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1379f2699491SMichael Ellerman { 1380f2699491SMichael Ellerman unsigned long type, op, result; 1381f2699491SMichael Ellerman int ev; 1382f2699491SMichael Ellerman 1383f2699491SMichael Ellerman if (!ppmu->cache_events) 1384f2699491SMichael Ellerman return -EINVAL; 1385f2699491SMichael Ellerman 1386f2699491SMichael Ellerman /* unpack config */ 1387f2699491SMichael Ellerman type = config & 0xff; 1388f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1389f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1390f2699491SMichael Ellerman 1391f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1392f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1393f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1394f2699491SMichael Ellerman return -EINVAL; 1395f2699491SMichael Ellerman 1396f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1397f2699491SMichael Ellerman if (ev == 0) 1398f2699491SMichael Ellerman return -EOPNOTSUPP; 1399f2699491SMichael Ellerman if (ev == -1) 1400f2699491SMichael Ellerman return -EINVAL; 1401f2699491SMichael Ellerman *eventp = ev; 1402f2699491SMichael Ellerman return 0; 1403f2699491SMichael Ellerman } 1404f2699491SMichael Ellerman 1405f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1406f2699491SMichael Ellerman { 1407f2699491SMichael Ellerman u64 ev; 1408f2699491SMichael Ellerman unsigned long flags; 1409f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1410f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1411f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1412f2699491SMichael Ellerman int n; 1413f2699491SMichael Ellerman int err; 1414f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1415f2699491SMichael Ellerman 1416f2699491SMichael Ellerman if (!ppmu) 1417f2699491SMichael Ellerman return -ENOENT; 1418f2699491SMichael Ellerman 14193925f46bSAnshuman Khandual if (has_branch_stack(event)) { 14203925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 14213925f46bSAnshuman Khandual if (!(ppmu->flags & PPMU_BHRB)) 14225375871dSLinus Torvalds return -EOPNOTSUPP; 14233925f46bSAnshuman Khandual } 14245375871dSLinus Torvalds 1425f2699491SMichael Ellerman switch (event->attr.type) { 1426f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1427f2699491SMichael Ellerman ev = event->attr.config; 1428f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1429f2699491SMichael Ellerman return -EOPNOTSUPP; 1430f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1431f2699491SMichael Ellerman break; 1432f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1433f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1434f2699491SMichael Ellerman if (err) 1435f2699491SMichael Ellerman return err; 1436f2699491SMichael Ellerman break; 1437f2699491SMichael Ellerman case PERF_TYPE_RAW: 1438f2699491SMichael Ellerman ev = event->attr.config; 1439f2699491SMichael Ellerman break; 1440f2699491SMichael Ellerman default: 1441f2699491SMichael Ellerman return -ENOENT; 1442f2699491SMichael Ellerman } 1443f2699491SMichael Ellerman 1444f2699491SMichael Ellerman event->hw.config_base = ev; 1445f2699491SMichael Ellerman event->hw.idx = 0; 1446f2699491SMichael Ellerman 1447f2699491SMichael Ellerman /* 1448f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1449f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1450f2699491SMichael Ellerman * the user set it to. 1451f2699491SMichael Ellerman */ 1452f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1453f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1454f2699491SMichael Ellerman 1455f2699491SMichael Ellerman /* 1456f2699491SMichael Ellerman * If this is a per-task event, then we can use 1457f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1458f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1459f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1460f2699491SMichael Ellerman */ 1461f2699491SMichael Ellerman flags = 0; 1462f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1463f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1464f2699491SMichael Ellerman 1465f2699491SMichael Ellerman /* 1466f2699491SMichael Ellerman * If this machine has limited events, check whether this 1467f2699491SMichael Ellerman * event_id could go on a limited event. 1468f2699491SMichael Ellerman */ 1469f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1470f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1471f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1472f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1473f2699491SMichael Ellerman /* 1474f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1475f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1476f2699491SMichael Ellerman * alternative goes on a normal PMC. 1477f2699491SMichael Ellerman */ 1478f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1479f2699491SMichael Ellerman if (!ev) 1480f2699491SMichael Ellerman return -EINVAL; 1481f2699491SMichael Ellerman } 1482f2699491SMichael Ellerman } 1483f2699491SMichael Ellerman 1484f2699491SMichael Ellerman /* 1485f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1486f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1487f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1488f2699491SMichael Ellerman */ 1489f2699491SMichael Ellerman n = 0; 1490f2699491SMichael Ellerman if (event->group_leader != event) { 1491f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1492f2699491SMichael Ellerman ctrs, events, cflags); 1493f2699491SMichael Ellerman if (n < 0) 1494f2699491SMichael Ellerman return -EINVAL; 1495f2699491SMichael Ellerman } 1496f2699491SMichael Ellerman events[n] = ev; 1497f2699491SMichael Ellerman ctrs[n] = event; 1498f2699491SMichael Ellerman cflags[n] = flags; 1499f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1500f2699491SMichael Ellerman return -EINVAL; 1501f2699491SMichael Ellerman 1502f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1503f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 15043925f46bSAnshuman Khandual 15053925f46bSAnshuman Khandual if (has_branch_stack(event)) { 15063925f46bSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 15073925f46bSAnshuman Khandual event->attr.branch_sample_type); 15083925f46bSAnshuman Khandual 15093925f46bSAnshuman Khandual if(cpuhw->bhrb_filter == -1) 15103925f46bSAnshuman Khandual return -EOPNOTSUPP; 15113925f46bSAnshuman Khandual } 15123925f46bSAnshuman Khandual 1513f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 1514f2699491SMichael Ellerman if (err) 1515f2699491SMichael Ellerman return -EINVAL; 1516f2699491SMichael Ellerman 1517f2699491SMichael Ellerman event->hw.config = events[n]; 1518f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 1519f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1520f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 1521f2699491SMichael Ellerman 1522f2699491SMichael Ellerman /* 1523f2699491SMichael Ellerman * See if we need to reserve the PMU. 1524f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 1525f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 1526f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 1527f2699491SMichael Ellerman */ 1528f2699491SMichael Ellerman err = 0; 1529f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 1530f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1531f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 1532f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 1533f2699491SMichael Ellerman err = -EBUSY; 1534f2699491SMichael Ellerman else 1535f2699491SMichael Ellerman atomic_inc(&num_events); 1536f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1537f2699491SMichael Ellerman } 1538f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 1539f2699491SMichael Ellerman 1540f2699491SMichael Ellerman return err; 1541f2699491SMichael Ellerman } 1542f2699491SMichael Ellerman 15435375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 15445375871dSLinus Torvalds { 15455375871dSLinus Torvalds return event->hw.idx; 15465375871dSLinus Torvalds } 15475375871dSLinus Torvalds 15481c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 15491c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 15501c53a270SSukadev Bhattiprolu { 15511c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 15521c53a270SSukadev Bhattiprolu 15531c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 15541c53a270SSukadev Bhattiprolu 15551c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 15561c53a270SSukadev Bhattiprolu } 15571c53a270SSukadev Bhattiprolu 1558f2699491SMichael Ellerman struct pmu power_pmu = { 1559f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 1560f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 1561f2699491SMichael Ellerman .event_init = power_pmu_event_init, 1562f2699491SMichael Ellerman .add = power_pmu_add, 1563f2699491SMichael Ellerman .del = power_pmu_del, 1564f2699491SMichael Ellerman .start = power_pmu_start, 1565f2699491SMichael Ellerman .stop = power_pmu_stop, 1566f2699491SMichael Ellerman .read = power_pmu_read, 1567f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 1568f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 1569f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 15705375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 15713925f46bSAnshuman Khandual .flush_branch_stack = power_pmu_flush_branch_stack, 1572f2699491SMichael Ellerman }; 1573f2699491SMichael Ellerman 1574f2699491SMichael Ellerman /* 1575f2699491SMichael Ellerman * A counter has overflowed; update its count and record 1576f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 1577f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 1578f2699491SMichael Ellerman */ 1579f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 1580f2699491SMichael Ellerman struct pt_regs *regs) 1581f2699491SMichael Ellerman { 1582f2699491SMichael Ellerman u64 period = event->hw.sample_period; 1583f2699491SMichael Ellerman s64 prev, delta, left; 1584f2699491SMichael Ellerman int record = 0; 1585f2699491SMichael Ellerman 1586f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 1587f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1588f2699491SMichael Ellerman return; 1589f2699491SMichael Ellerman } 1590f2699491SMichael Ellerman 1591f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 1592f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1593f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1594f2699491SMichael Ellerman local64_add(delta, &event->count); 1595f2699491SMichael Ellerman 1596f2699491SMichael Ellerman /* 1597f2699491SMichael Ellerman * See if the total period for this event has expired, 1598f2699491SMichael Ellerman * and update for the next period. 1599f2699491SMichael Ellerman */ 1600f2699491SMichael Ellerman val = 0; 1601f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 1602e13e895fSMichael Neuling if (delta == 0) 1603e13e895fSMichael Neuling left++; 1604f2699491SMichael Ellerman if (period) { 1605f2699491SMichael Ellerman if (left <= 0) { 1606f2699491SMichael Ellerman left += period; 1607f2699491SMichael Ellerman if (left <= 0) 1608f2699491SMichael Ellerman left = period; 1609e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 1610f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1611f2699491SMichael Ellerman } 1612f2699491SMichael Ellerman if (left < 0x80000000LL) 1613f2699491SMichael Ellerman val = 0x80000000LL - left; 1614f2699491SMichael Ellerman } 1615f2699491SMichael Ellerman 1616f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1617f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1618f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 1619f2699491SMichael Ellerman perf_event_update_userpage(event); 1620f2699491SMichael Ellerman 1621f2699491SMichael Ellerman /* 1622f2699491SMichael Ellerman * Finally record data if requested. 1623f2699491SMichael Ellerman */ 1624f2699491SMichael Ellerman if (record) { 1625f2699491SMichael Ellerman struct perf_sample_data data; 1626f2699491SMichael Ellerman 1627fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 1628f2699491SMichael Ellerman 1629f2699491SMichael Ellerman if (event->attr.sample_type & PERF_SAMPLE_ADDR) 1630f2699491SMichael Ellerman perf_get_data_addr(regs, &data.addr); 1631f2699491SMichael Ellerman 16323925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 16333925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 16343925f46bSAnshuman Khandual cpuhw = &__get_cpu_var(cpu_hw_events); 16353925f46bSAnshuman Khandual power_pmu_bhrb_read(cpuhw); 16363925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 16373925f46bSAnshuman Khandual } 16383925f46bSAnshuman Khandual 1639f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 1640f2699491SMichael Ellerman power_pmu_stop(event, 0); 1641f2699491SMichael Ellerman } 1642f2699491SMichael Ellerman } 1643f2699491SMichael Ellerman 1644f2699491SMichael Ellerman /* 1645f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 1646f2699491SMichael Ellerman * for an event_id. 1647f2699491SMichael Ellerman */ 1648f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 1649f2699491SMichael Ellerman { 1650f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 1651f2699491SMichael Ellerman 1652f2699491SMichael Ellerman if (flags) 1653f2699491SMichael Ellerman return flags; 1654f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 1655f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 1656f2699491SMichael Ellerman } 1657f2699491SMichael Ellerman 1658f2699491SMichael Ellerman /* 1659f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 1660f2699491SMichael Ellerman * for an event_id. 1661f2699491SMichael Ellerman */ 1662f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 1663f2699491SMichael Ellerman { 166433904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 1665f2699491SMichael Ellerman 1666e6878835Ssukadev@linux.vnet.ibm.com if (use_siar && siar_valid(regs)) 16671ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 1668e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 1669e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 167075382aa7SAnton Blanchard else 167175382aa7SAnton Blanchard return regs->nip; 1672f2699491SMichael Ellerman } 1673f2699491SMichael Ellerman 1674bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 1675f2699491SMichael Ellerman { 1676f2699491SMichael Ellerman /* 1677f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 1678f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 1679f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 1680f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 1681f2699491SMichael Ellerman * cycles from overflow. 1682f2699491SMichael Ellerman * 1683f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 1684f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 1685f2699491SMichael Ellerman * don't want to mistakenly reset them. 1686f2699491SMichael Ellerman */ 1687bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 1688bc09c219SMichael Neuling return true; 1689bc09c219SMichael Neuling 1690bc09c219SMichael Neuling return false; 1691bc09c219SMichael Neuling } 1692bc09c219SMichael Neuling 1693bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 1694bc09c219SMichael Neuling { 1695bc09c219SMichael Neuling if ((int)val < 0) 1696f2699491SMichael Ellerman return true; 1697f2699491SMichael Ellerman 1698f2699491SMichael Ellerman return false; 1699f2699491SMichael Ellerman } 1700f2699491SMichael Ellerman 1701f2699491SMichael Ellerman /* 1702f2699491SMichael Ellerman * Performance monitor interrupt stuff 1703f2699491SMichael Ellerman */ 1704f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs) 1705f2699491SMichael Ellerman { 1706bc09c219SMichael Neuling int i, j; 1707f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); 1708f2699491SMichael Ellerman struct perf_event *event; 1709bc09c219SMichael Neuling unsigned long val[8]; 1710bc09c219SMichael Neuling int found, active; 1711f2699491SMichael Ellerman int nmi; 1712f2699491SMichael Ellerman 1713f2699491SMichael Ellerman if (cpuhw->n_limited) 1714f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 1715f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 1716f2699491SMichael Ellerman 1717f2699491SMichael Ellerman perf_read_regs(regs); 1718f2699491SMichael Ellerman 1719f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 1720f2699491SMichael Ellerman if (nmi) 1721f2699491SMichael Ellerman nmi_enter(); 1722f2699491SMichael Ellerman else 1723f2699491SMichael Ellerman irq_enter(); 1724f2699491SMichael Ellerman 1725bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 1726bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 1727bc09c219SMichael Neuling val[i] = read_pmc(i + 1); 1728bc09c219SMichael Neuling 1729bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 1730bc09c219SMichael Neuling found = 0; 1731bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 1732bc09c219SMichael Neuling if (!pmc_overflow(val[i])) 1733bc09c219SMichael Neuling continue; 1734bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 1735bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 1736bc09c219SMichael Neuling /* 1737bc09c219SMichael Neuling * We've found one that's overflowed. For active 1738bc09c219SMichael Neuling * counters we need to log this. For inactive 1739bc09c219SMichael Neuling * counters, we need to reset it anyway 1740bc09c219SMichael Neuling */ 1741bc09c219SMichael Neuling found = 1; 1742bc09c219SMichael Neuling active = 0; 1743bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 1744bc09c219SMichael Neuling event = cpuhw->event[j]; 1745bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 1746bc09c219SMichael Neuling active = 1; 1747bc09c219SMichael Neuling record_and_restart(event, val[i], regs); 1748bc09c219SMichael Neuling break; 1749bc09c219SMichael Neuling } 1750bc09c219SMichael Neuling } 1751bc09c219SMichael Neuling if (!active) 1752bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 1753bc09c219SMichael Neuling write_pmc(i + 1, 0); 1754bc09c219SMichael Neuling } 1755bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 1756bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 1757f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1758f2699491SMichael Ellerman event = cpuhw->event[i]; 1759f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 1760f2699491SMichael Ellerman continue; 1761bc09c219SMichael Neuling if (pmc_overflow_power7(val[event->hw.idx - 1])) { 1762bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 1763f2699491SMichael Ellerman found = 1; 1764bc09c219SMichael Neuling record_and_restart(event, 1765bc09c219SMichael Neuling val[event->hw.idx - 1], 1766bc09c219SMichael Neuling regs); 1767f2699491SMichael Ellerman } 1768f2699491SMichael Ellerman } 1769f2699491SMichael Ellerman } 17706772faa1SMichael Ellerman if (!found && !nmi && printk_ratelimit()) 1771bc09c219SMichael Neuling printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 1772f2699491SMichael Ellerman 1773f2699491SMichael Ellerman /* 1774f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 1775f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 1776f2699491SMichael Ellerman * and thus allow interrupts to occur again. 1777f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 1778f2699491SMichael Ellerman * we get back out of this interrupt. 1779f2699491SMichael Ellerman */ 1780f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 1781f2699491SMichael Ellerman 1782f2699491SMichael Ellerman if (nmi) 1783f2699491SMichael Ellerman nmi_exit(); 1784f2699491SMichael Ellerman else 1785f2699491SMichael Ellerman irq_exit(); 1786f2699491SMichael Ellerman } 1787f2699491SMichael Ellerman 1788f2699491SMichael Ellerman static void power_pmu_setup(int cpu) 1789f2699491SMichael Ellerman { 1790f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 1791f2699491SMichael Ellerman 1792f2699491SMichael Ellerman if (!ppmu) 1793f2699491SMichael Ellerman return; 1794f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 1795f2699491SMichael Ellerman cpuhw->mmcr[0] = MMCR0_FC; 1796f2699491SMichael Ellerman } 1797f2699491SMichael Ellerman 1798061d19f2SPaul Gortmaker static int 1799f2699491SMichael Ellerman power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu) 1800f2699491SMichael Ellerman { 1801f2699491SMichael Ellerman unsigned int cpu = (long)hcpu; 1802f2699491SMichael Ellerman 1803f2699491SMichael Ellerman switch (action & ~CPU_TASKS_FROZEN) { 1804f2699491SMichael Ellerman case CPU_UP_PREPARE: 1805f2699491SMichael Ellerman power_pmu_setup(cpu); 1806f2699491SMichael Ellerman break; 1807f2699491SMichael Ellerman 1808f2699491SMichael Ellerman default: 1809f2699491SMichael Ellerman break; 1810f2699491SMichael Ellerman } 1811f2699491SMichael Ellerman 1812f2699491SMichael Ellerman return NOTIFY_OK; 1813f2699491SMichael Ellerman } 1814f2699491SMichael Ellerman 1815061d19f2SPaul Gortmaker int register_power_pmu(struct power_pmu *pmu) 1816f2699491SMichael Ellerman { 1817f2699491SMichael Ellerman if (ppmu) 1818f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 1819f2699491SMichael Ellerman 1820f2699491SMichael Ellerman ppmu = pmu; 1821f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 1822f2699491SMichael Ellerman pmu->name); 1823f2699491SMichael Ellerman 18241c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 18251c53a270SSukadev Bhattiprolu 1826f2699491SMichael Ellerman #ifdef MSR_HV 1827f2699491SMichael Ellerman /* 1828f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 1829f2699491SMichael Ellerman */ 1830f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 1831f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 1832f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 1833f2699491SMichael Ellerman 1834f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 1835f2699491SMichael Ellerman perf_cpu_notifier(power_pmu_notifier); 1836f2699491SMichael Ellerman 1837f2699491SMichael Ellerman return 0; 1838f2699491SMichael Ellerman } 1839