1f2699491SMichael Ellerman /* 2f2699491SMichael Ellerman * Performance event support - powerpc architecture code 3f2699491SMichael Ellerman * 4f2699491SMichael Ellerman * Copyright 2008-2009 Paul Mackerras, IBM Corporation. 5f2699491SMichael Ellerman * 6f2699491SMichael Ellerman * This program is free software; you can redistribute it and/or 7f2699491SMichael Ellerman * modify it under the terms of the GNU General Public License 8f2699491SMichael Ellerman * as published by the Free Software Foundation; either version 9f2699491SMichael Ellerman * 2 of the License, or (at your option) any later version. 10f2699491SMichael Ellerman */ 11f2699491SMichael Ellerman #include <linux/kernel.h> 12f2699491SMichael Ellerman #include <linux/sched.h> 13f2699491SMichael Ellerman #include <linux/perf_event.h> 14f2699491SMichael Ellerman #include <linux/percpu.h> 15f2699491SMichael Ellerman #include <linux/hardirq.h> 1669123184SMichael Neuling #include <linux/uaccess.h> 17f2699491SMichael Ellerman #include <asm/reg.h> 18f2699491SMichael Ellerman #include <asm/pmc.h> 19f2699491SMichael Ellerman #include <asm/machdep.h> 20f2699491SMichael Ellerman #include <asm/firmware.h> 21f2699491SMichael Ellerman #include <asm/ptrace.h> 2269123184SMichael Neuling #include <asm/code-patching.h> 23f2699491SMichael Ellerman 243925f46bSAnshuman Khandual #define BHRB_MAX_ENTRIES 32 253925f46bSAnshuman Khandual #define BHRB_TARGET 0x0000000000000002 263925f46bSAnshuman Khandual #define BHRB_PREDICTION 0x0000000000000001 27b0d436c7SAnton Blanchard #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL 283925f46bSAnshuman Khandual 29f2699491SMichael Ellerman struct cpu_hw_events { 30f2699491SMichael Ellerman int n_events; 31f2699491SMichael Ellerman int n_percpu; 32f2699491SMichael Ellerman int disabled; 33f2699491SMichael Ellerman int n_added; 34f2699491SMichael Ellerman int n_limited; 35f2699491SMichael Ellerman u8 pmcs_enabled; 36f2699491SMichael Ellerman struct perf_event *event[MAX_HWEVENTS]; 37f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 38f2699491SMichael Ellerman unsigned int flags[MAX_HWEVENTS]; 399de5cb0fSMichael Ellerman /* 409de5cb0fSMichael Ellerman * The order of the MMCR array is: 419de5cb0fSMichael Ellerman * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2 429de5cb0fSMichael Ellerman * - 32-bit, MMCR0, MMCR1, MMCR2 439de5cb0fSMichael Ellerman */ 449de5cb0fSMichael Ellerman unsigned long mmcr[4]; 45f2699491SMichael Ellerman struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS]; 46f2699491SMichael Ellerman u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; 47f2699491SMichael Ellerman u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 48f2699491SMichael Ellerman unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 49f2699491SMichael Ellerman unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES]; 50f2699491SMichael Ellerman 51fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 52f2699491SMichael Ellerman int n_txn_start; 533925f46bSAnshuman Khandual 543925f46bSAnshuman Khandual /* BHRB bits */ 553925f46bSAnshuman Khandual u64 bhrb_filter; /* BHRB HW branch filter */ 56f0322f7fSAnshuman Khandual unsigned int bhrb_users; 573925f46bSAnshuman Khandual void *bhrb_context; 583925f46bSAnshuman Khandual struct perf_branch_stack bhrb_stack; 593925f46bSAnshuman Khandual struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES]; 60356d8ce3SMadhavan Srinivasan u64 ic_init; 61f2699491SMichael Ellerman }; 623925f46bSAnshuman Khandual 63e51df2c1SAnton Blanchard static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events); 64f2699491SMichael Ellerman 65e51df2c1SAnton Blanchard static struct power_pmu *ppmu; 66f2699491SMichael Ellerman 67f2699491SMichael Ellerman /* 68f2699491SMichael Ellerman * Normally, to ignore kernel events we set the FCS (freeze counters 69f2699491SMichael Ellerman * in supervisor mode) bit in MMCR0, but if the kernel runs with the 70f2699491SMichael Ellerman * hypervisor bit set in the MSR, or if we are running on a processor 71f2699491SMichael Ellerman * where the hypervisor bit is forced to 1 (as on Apple G5 processors), 72f2699491SMichael Ellerman * then we need to use the FCHV bit to ignore kernel events. 73f2699491SMichael Ellerman */ 74f2699491SMichael Ellerman static unsigned int freeze_events_kernel = MMCR0_FCS; 75f2699491SMichael Ellerman 76f2699491SMichael Ellerman /* 77f2699491SMichael Ellerman * 32-bit doesn't have MMCRA but does have an MMCR2, 78f2699491SMichael Ellerman * and a few other names are different. 79f2699491SMichael Ellerman */ 80f2699491SMichael Ellerman #ifdef CONFIG_PPC32 81f2699491SMichael Ellerman 82f2699491SMichael Ellerman #define MMCR0_FCHV 0 83f2699491SMichael Ellerman #define MMCR0_PMCjCE MMCR0_PMCnCE 847a7a41f9SMichael Ellerman #define MMCR0_FC56 0 85378a6ee9SMichael Ellerman #define MMCR0_PMAO 0 86330a1eb7SMichael Ellerman #define MMCR0_EBE 0 8776cb8a78SMichael Ellerman #define MMCR0_BHRBA 0 88330a1eb7SMichael Ellerman #define MMCR0_PMCC 0 89330a1eb7SMichael Ellerman #define MMCR0_PMCC_U6 0 90f2699491SMichael Ellerman 91f2699491SMichael Ellerman #define SPRN_MMCRA SPRN_MMCR2 92f2699491SMichael Ellerman #define MMCRA_SAMPLE_ENABLE 0 93f2699491SMichael Ellerman 94f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 95f2699491SMichael Ellerman { 96f2699491SMichael Ellerman return 0; 97f2699491SMichael Ellerman } 98f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { } 99f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 100f2699491SMichael Ellerman { 101f2699491SMichael Ellerman return 0; 102f2699491SMichael Ellerman } 10375382aa7SAnton Blanchard static inline void perf_read_regs(struct pt_regs *regs) 10475382aa7SAnton Blanchard { 10575382aa7SAnton Blanchard regs->result = 0; 10675382aa7SAnton Blanchard } 107f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 108f2699491SMichael Ellerman { 109f2699491SMichael Ellerman return 0; 110f2699491SMichael Ellerman } 111f2699491SMichael Ellerman 112e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 113e6878835Ssukadev@linux.vnet.ibm.com { 114e6878835Ssukadev@linux.vnet.ibm.com return 1; 115e6878835Ssukadev@linux.vnet.ibm.com } 116e6878835Ssukadev@linux.vnet.ibm.com 117330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) { return false; } 118330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) { return 0; } 119330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) { } 120330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) { } 1219de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 122330a1eb7SMichael Ellerman { 1239de5cb0fSMichael Ellerman return cpuhw->mmcr[0]; 124330a1eb7SMichael Ellerman } 125330a1eb7SMichael Ellerman 126d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_enable(struct perf_event *event) {} 127d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_disable(struct perf_event *event) {} 128acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {} 129d52f2dc4SMichael Neuling static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {} 130c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) { } 131356d8ce3SMadhavan Srinivasan static bool use_ic(u64 event) 132356d8ce3SMadhavan Srinivasan { 133356d8ce3SMadhavan Srinivasan return false; 134356d8ce3SMadhavan Srinivasan } 135f2699491SMichael Ellerman #endif /* CONFIG_PPC32 */ 136f2699491SMichael Ellerman 13733904054SMichael Ellerman static bool regs_use_siar(struct pt_regs *regs) 13833904054SMichael Ellerman { 13972e349f1SAnton Blanchard /* 14072e349f1SAnton Blanchard * When we take a performance monitor exception the regs are setup 14172e349f1SAnton Blanchard * using perf_read_regs() which overloads some fields, in particular 14272e349f1SAnton Blanchard * regs->result to tell us whether to use SIAR. 14372e349f1SAnton Blanchard * 14472e349f1SAnton Blanchard * However if the regs are from another exception, eg. a syscall, then 14572e349f1SAnton Blanchard * they have not been setup using perf_read_regs() and so regs->result 14672e349f1SAnton Blanchard * is something random. 14772e349f1SAnton Blanchard */ 14872e349f1SAnton Blanchard return ((TRAP(regs) == 0xf00) && regs->result); 14933904054SMichael Ellerman } 15033904054SMichael Ellerman 151f2699491SMichael Ellerman /* 152f2699491SMichael Ellerman * Things that are specific to 64-bit implementations. 153f2699491SMichael Ellerman */ 154f2699491SMichael Ellerman #ifdef CONFIG_PPC64 155f2699491SMichael Ellerman 156f2699491SMichael Ellerman static inline unsigned long perf_ip_adjust(struct pt_regs *regs) 157f2699491SMichael Ellerman { 158f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 159f2699491SMichael Ellerman 1607a786832SMichael Ellerman if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) { 161f2699491SMichael Ellerman unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT; 162f2699491SMichael Ellerman if (slot > 1) 163f2699491SMichael Ellerman return 4 * (slot - 1); 164f2699491SMichael Ellerman } 1657a786832SMichael Ellerman 166f2699491SMichael Ellerman return 0; 167f2699491SMichael Ellerman } 168f2699491SMichael Ellerman 169f2699491SMichael Ellerman /* 170f2699491SMichael Ellerman * The user wants a data address recorded. 171f2699491SMichael Ellerman * If we're not doing instruction sampling, give them the SDAR 172f2699491SMichael Ellerman * (sampled data address). If we are doing instruction sampling, then 173f2699491SMichael Ellerman * only give them the SDAR if it corresponds to the instruction 17458a032c3SMichael Ellerman * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the 17558a032c3SMichael Ellerman * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER. 176f2699491SMichael Ellerman */ 177f2699491SMichael Ellerman static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) 178f2699491SMichael Ellerman { 179f2699491SMichael Ellerman unsigned long mmcra = regs->dsisr; 18058a032c3SMichael Ellerman bool sdar_valid; 18158a032c3SMichael Ellerman 18258a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 18358a032c3SMichael Ellerman sdar_valid = regs->dar & SIER_SDAR_VALID; 18458a032c3SMichael Ellerman else { 185e6878835Ssukadev@linux.vnet.ibm.com unsigned long sdsync; 186e6878835Ssukadev@linux.vnet.ibm.com 187e6878835Ssukadev@linux.vnet.ibm.com if (ppmu->flags & PPMU_SIAR_VALID) 188e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER7P_MMCRA_SDAR_VALID; 189e6878835Ssukadev@linux.vnet.ibm.com else if (ppmu->flags & PPMU_ALT_SIPR) 190e6878835Ssukadev@linux.vnet.ibm.com sdsync = POWER6_MMCRA_SDSYNC; 191f04d1080SMadhavan Srinivasan else if (ppmu->flags & PPMU_NO_SIAR) 192f04d1080SMadhavan Srinivasan sdsync = MMCRA_SAMPLE_ENABLE; 193e6878835Ssukadev@linux.vnet.ibm.com else 194e6878835Ssukadev@linux.vnet.ibm.com sdsync = MMCRA_SDSYNC; 195f2699491SMichael Ellerman 19658a032c3SMichael Ellerman sdar_valid = mmcra & sdsync; 19758a032c3SMichael Ellerman } 19858a032c3SMichael Ellerman 19958a032c3SMichael Ellerman if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid) 200f2699491SMichael Ellerman *addrp = mfspr(SPRN_SDAR); 201f2699491SMichael Ellerman } 202f2699491SMichael Ellerman 2035682c460SMichael Ellerman static bool regs_sihv(struct pt_regs *regs) 20468b30bb9SAnton Blanchard { 20568b30bb9SAnton Blanchard unsigned long sihv = MMCRA_SIHV; 20668b30bb9SAnton Blanchard 2078f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2088f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIHV); 2098f61aa32SMichael Ellerman 21068b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 21168b30bb9SAnton Blanchard sihv = POWER6_MMCRA_SIHV; 21268b30bb9SAnton Blanchard 2135682c460SMichael Ellerman return !!(regs->dsisr & sihv); 21468b30bb9SAnton Blanchard } 21568b30bb9SAnton Blanchard 2165682c460SMichael Ellerman static bool regs_sipr(struct pt_regs *regs) 21768b30bb9SAnton Blanchard { 21868b30bb9SAnton Blanchard unsigned long sipr = MMCRA_SIPR; 21968b30bb9SAnton Blanchard 2208f61aa32SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2218f61aa32SMichael Ellerman return !!(regs->dar & SIER_SIPR); 2228f61aa32SMichael Ellerman 22368b30bb9SAnton Blanchard if (ppmu->flags & PPMU_ALT_SIPR) 22468b30bb9SAnton Blanchard sipr = POWER6_MMCRA_SIPR; 22568b30bb9SAnton Blanchard 2265682c460SMichael Ellerman return !!(regs->dsisr & sipr); 22768b30bb9SAnton Blanchard } 22868b30bb9SAnton Blanchard 2291ce447b9SBenjamin Herrenschmidt static inline u32 perf_flags_from_msr(struct pt_regs *regs) 2301ce447b9SBenjamin Herrenschmidt { 2311ce447b9SBenjamin Herrenschmidt if (regs->msr & MSR_PR) 2321ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2331ce447b9SBenjamin Herrenschmidt if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV) 2341ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_HYPERVISOR; 2351ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2361ce447b9SBenjamin Herrenschmidt } 2371ce447b9SBenjamin Herrenschmidt 238f2699491SMichael Ellerman static inline u32 perf_get_misc_flags(struct pt_regs *regs) 239f2699491SMichael Ellerman { 24033904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 241f2699491SMichael Ellerman 24275382aa7SAnton Blanchard if (!use_siar) 2431ce447b9SBenjamin Herrenschmidt return perf_flags_from_msr(regs); 2441ce447b9SBenjamin Herrenschmidt 2451ce447b9SBenjamin Herrenschmidt /* 2461ce447b9SBenjamin Herrenschmidt * If we don't have flags in MMCRA, rather than using 2471ce447b9SBenjamin Herrenschmidt * the MSR, we intuit the flags from the address in 2481ce447b9SBenjamin Herrenschmidt * SIAR which should give slightly more reliable 2491ce447b9SBenjamin Herrenschmidt * results 2501ce447b9SBenjamin Herrenschmidt */ 251cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_NO_SIPR) { 2521ce447b9SBenjamin Herrenschmidt unsigned long siar = mfspr(SPRN_SIAR); 253a2391b35SMadhavan Srinivasan if (is_kernel_addr(siar)) 2541ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_KERNEL; 2551ce447b9SBenjamin Herrenschmidt return PERF_RECORD_MISC_USER; 2561ce447b9SBenjamin Herrenschmidt } 257f2699491SMichael Ellerman 258f2699491SMichael Ellerman /* PR has priority over HV, so order below is important */ 2595682c460SMichael Ellerman if (regs_sipr(regs)) 260f2699491SMichael Ellerman return PERF_RECORD_MISC_USER; 2615682c460SMichael Ellerman 2625682c460SMichael Ellerman if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV)) 263f2699491SMichael Ellerman return PERF_RECORD_MISC_HYPERVISOR; 2645682c460SMichael Ellerman 265f2699491SMichael Ellerman return PERF_RECORD_MISC_KERNEL; 266f2699491SMichael Ellerman } 267f2699491SMichael Ellerman 268f2699491SMichael Ellerman /* 269f2699491SMichael Ellerman * Overload regs->dsisr to store MMCRA so we only need to read it once 270f2699491SMichael Ellerman * on each interrupt. 2718f61aa32SMichael Ellerman * Overload regs->dar to store SIER if we have it. 27275382aa7SAnton Blanchard * Overload regs->result to specify whether we should use the MSR (result 27375382aa7SAnton Blanchard * is zero) or the SIAR (result is non zero). 274f2699491SMichael Ellerman */ 275f2699491SMichael Ellerman static inline void perf_read_regs(struct pt_regs *regs) 276f2699491SMichael Ellerman { 27775382aa7SAnton Blanchard unsigned long mmcra = mfspr(SPRN_MMCRA); 27875382aa7SAnton Blanchard int marked = mmcra & MMCRA_SAMPLE_ENABLE; 27975382aa7SAnton Blanchard int use_siar; 28075382aa7SAnton Blanchard 2815682c460SMichael Ellerman regs->dsisr = mmcra; 282860aad71SMichael Ellerman 283cbda6aa1SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 2848f61aa32SMichael Ellerman regs->dar = mfspr(SPRN_SIER); 2858f61aa32SMichael Ellerman 2868f61aa32SMichael Ellerman /* 2875c093efaSAnton Blanchard * If this isn't a PMU exception (eg a software event) the SIAR is 2885c093efaSAnton Blanchard * not valid. Use pt_regs. 2895c093efaSAnton Blanchard * 2905c093efaSAnton Blanchard * If it is a marked event use the SIAR. 2915c093efaSAnton Blanchard * 2925c093efaSAnton Blanchard * If the PMU doesn't update the SIAR for non marked events use 2935c093efaSAnton Blanchard * pt_regs. 2945c093efaSAnton Blanchard * 2955c093efaSAnton Blanchard * If the PMU has HV/PR flags then check to see if they 2965c093efaSAnton Blanchard * place the exception in userspace. If so, use pt_regs. In 2975c093efaSAnton Blanchard * continuous sampling mode the SIAR and the PMU exception are 2985c093efaSAnton Blanchard * not synchronised, so they may be many instructions apart. 2995c093efaSAnton Blanchard * This can result in confusing backtraces. We still want 3005c093efaSAnton Blanchard * hypervisor samples as well as samples in the kernel with 3015c093efaSAnton Blanchard * interrupts off hence the userspace check. 3025c093efaSAnton Blanchard */ 30375382aa7SAnton Blanchard if (TRAP(regs) != 0xf00) 30475382aa7SAnton Blanchard use_siar = 0; 30527593d72SMadhavan Srinivasan else if ((ppmu->flags & PPMU_NO_SIAR)) 30627593d72SMadhavan Srinivasan use_siar = 0; 3075c093efaSAnton Blanchard else if (marked) 3085c093efaSAnton Blanchard use_siar = 1; 3095c093efaSAnton Blanchard else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING)) 3105c093efaSAnton Blanchard use_siar = 0; 311cbda6aa1SMichael Ellerman else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs)) 31275382aa7SAnton Blanchard use_siar = 0; 31375382aa7SAnton Blanchard else 31475382aa7SAnton Blanchard use_siar = 1; 31575382aa7SAnton Blanchard 316cbda6aa1SMichael Ellerman regs->result = use_siar; 317f2699491SMichael Ellerman } 318f2699491SMichael Ellerman 319f2699491SMichael Ellerman /* 320f2699491SMichael Ellerman * If interrupts were soft-disabled when a PMU interrupt occurs, treat 321f2699491SMichael Ellerman * it as an NMI. 322f2699491SMichael Ellerman */ 323f2699491SMichael Ellerman static inline int perf_intr_is_nmi(struct pt_regs *regs) 324f2699491SMichael Ellerman { 32501417c6cSMadhavan Srinivasan return (regs->softe & IRQS_DISABLED); 326f2699491SMichael Ellerman } 327f2699491SMichael Ellerman 328e6878835Ssukadev@linux.vnet.ibm.com /* 329e6878835Ssukadev@linux.vnet.ibm.com * On processors like P7+ that have the SIAR-Valid bit, marked instructions 330e6878835Ssukadev@linux.vnet.ibm.com * must be sampled only if the SIAR-valid bit is set. 331e6878835Ssukadev@linux.vnet.ibm.com * 332e6878835Ssukadev@linux.vnet.ibm.com * For unmarked instructions and for processors that don't have the SIAR-Valid 333e6878835Ssukadev@linux.vnet.ibm.com * bit, assume that SIAR is valid. 334e6878835Ssukadev@linux.vnet.ibm.com */ 335e6878835Ssukadev@linux.vnet.ibm.com static inline int siar_valid(struct pt_regs *regs) 336e6878835Ssukadev@linux.vnet.ibm.com { 337e6878835Ssukadev@linux.vnet.ibm.com unsigned long mmcra = regs->dsisr; 338e6878835Ssukadev@linux.vnet.ibm.com int marked = mmcra & MMCRA_SAMPLE_ENABLE; 339e6878835Ssukadev@linux.vnet.ibm.com 34058a032c3SMichael Ellerman if (marked) { 34158a032c3SMichael Ellerman if (ppmu->flags & PPMU_HAS_SIER) 34258a032c3SMichael Ellerman return regs->dar & SIER_SIAR_VALID; 34358a032c3SMichael Ellerman 34458a032c3SMichael Ellerman if (ppmu->flags & PPMU_SIAR_VALID) 345e6878835Ssukadev@linux.vnet.ibm.com return mmcra & POWER7P_MMCRA_SIAR_VALID; 34658a032c3SMichael Ellerman } 347e6878835Ssukadev@linux.vnet.ibm.com 348e6878835Ssukadev@linux.vnet.ibm.com return 1; 349e6878835Ssukadev@linux.vnet.ibm.com } 350e6878835Ssukadev@linux.vnet.ibm.com 351d52f2dc4SMichael Neuling 352d52f2dc4SMichael Neuling /* Reset all possible BHRB entries */ 353d52f2dc4SMichael Neuling static void power_pmu_bhrb_reset(void) 354d52f2dc4SMichael Neuling { 355d52f2dc4SMichael Neuling asm volatile(PPC_CLRBHRB); 356d52f2dc4SMichael Neuling } 357d52f2dc4SMichael Neuling 358d52f2dc4SMichael Neuling static void power_pmu_bhrb_enable(struct perf_event *event) 359d52f2dc4SMichael Neuling { 36069111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 361d52f2dc4SMichael Neuling 362d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 363d52f2dc4SMichael Neuling return; 364d52f2dc4SMichael Neuling 365d52f2dc4SMichael Neuling /* Clear BHRB if we changed task context to avoid data leaks */ 366d52f2dc4SMichael Neuling if (event->ctx->task && cpuhw->bhrb_context != event->ctx) { 367d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 368d52f2dc4SMichael Neuling cpuhw->bhrb_context = event->ctx; 369d52f2dc4SMichael Neuling } 370d52f2dc4SMichael Neuling cpuhw->bhrb_users++; 371acba3c7eSPeter Zijlstra perf_sched_cb_inc(event->ctx->pmu); 372d52f2dc4SMichael Neuling } 373d52f2dc4SMichael Neuling 374d52f2dc4SMichael Neuling static void power_pmu_bhrb_disable(struct perf_event *event) 375d52f2dc4SMichael Neuling { 37669111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 377d52f2dc4SMichael Neuling 378d52f2dc4SMichael Neuling if (!ppmu->bhrb_nr) 379d52f2dc4SMichael Neuling return; 380d52f2dc4SMichael Neuling 381f0322f7fSAnshuman Khandual WARN_ON_ONCE(!cpuhw->bhrb_users); 382d52f2dc4SMichael Neuling cpuhw->bhrb_users--; 383acba3c7eSPeter Zijlstra perf_sched_cb_dec(event->ctx->pmu); 384d52f2dc4SMichael Neuling 385d52f2dc4SMichael Neuling if (!cpuhw->disabled && !cpuhw->bhrb_users) { 386d52f2dc4SMichael Neuling /* BHRB cannot be turned off when other 387d52f2dc4SMichael Neuling * events are active on the PMU. 388d52f2dc4SMichael Neuling */ 389d52f2dc4SMichael Neuling 390d52f2dc4SMichael Neuling /* avoid stale pointer */ 391d52f2dc4SMichael Neuling cpuhw->bhrb_context = NULL; 392d52f2dc4SMichael Neuling } 393d52f2dc4SMichael Neuling } 394d52f2dc4SMichael Neuling 395d52f2dc4SMichael Neuling /* Called from ctxsw to prevent one process's branch entries to 396d52f2dc4SMichael Neuling * mingle with the other process's entries during context switch. 397d52f2dc4SMichael Neuling */ 398acba3c7eSPeter Zijlstra static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) 399d52f2dc4SMichael Neuling { 400acba3c7eSPeter Zijlstra if (!ppmu->bhrb_nr) 401acba3c7eSPeter Zijlstra return; 402acba3c7eSPeter Zijlstra 403acba3c7eSPeter Zijlstra if (sched_in) 404d52f2dc4SMichael Neuling power_pmu_bhrb_reset(); 405d52f2dc4SMichael Neuling } 40669123184SMichael Neuling /* Calculate the to address for a branch */ 40769123184SMichael Neuling static __u64 power_pmu_bhrb_to(u64 addr) 40869123184SMichael Neuling { 40969123184SMichael Neuling unsigned int instr; 41069123184SMichael Neuling int ret; 41169123184SMichael Neuling __u64 target; 41269123184SMichael Neuling 41369123184SMichael Neuling if (is_kernel_addr(addr)) 41469123184SMichael Neuling return branch_target((unsigned int *)addr); 41569123184SMichael Neuling 41669123184SMichael Neuling /* Userspace: need copy instruction here then translate it */ 41769123184SMichael Neuling pagefault_disable(); 41869123184SMichael Neuling ret = __get_user_inatomic(instr, (unsigned int __user *)addr); 41969123184SMichael Neuling if (ret) { 42069123184SMichael Neuling pagefault_enable(); 42169123184SMichael Neuling return 0; 42269123184SMichael Neuling } 42369123184SMichael Neuling pagefault_enable(); 42469123184SMichael Neuling 42569123184SMichael Neuling target = branch_target(&instr); 42669123184SMichael Neuling if ((!target) || (instr & BRANCH_ABSOLUTE)) 42769123184SMichael Neuling return target; 42869123184SMichael Neuling 42969123184SMichael Neuling /* Translate relative branch target from kernel to user address */ 43069123184SMichael Neuling return target - (unsigned long)&instr + addr; 43169123184SMichael Neuling } 432d52f2dc4SMichael Neuling 433d52f2dc4SMichael Neuling /* Processing BHRB entries */ 434e51df2c1SAnton Blanchard static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) 435d52f2dc4SMichael Neuling { 436d52f2dc4SMichael Neuling u64 val; 437d52f2dc4SMichael Neuling u64 addr; 438506e70d1SMichael Neuling int r_index, u_index, pred; 439d52f2dc4SMichael Neuling 440d52f2dc4SMichael Neuling r_index = 0; 441d52f2dc4SMichael Neuling u_index = 0; 442d52f2dc4SMichael Neuling while (r_index < ppmu->bhrb_nr) { 443d52f2dc4SMichael Neuling /* Assembly read function */ 444506e70d1SMichael Neuling val = read_bhrb(r_index++); 445506e70d1SMichael Neuling if (!val) 446d52f2dc4SMichael Neuling /* Terminal marker: End of valid BHRB entries */ 447d52f2dc4SMichael Neuling break; 448506e70d1SMichael Neuling else { 449d52f2dc4SMichael Neuling addr = val & BHRB_EA; 450d52f2dc4SMichael Neuling pred = val & BHRB_PREDICTION; 451d52f2dc4SMichael Neuling 452506e70d1SMichael Neuling if (!addr) 453506e70d1SMichael Neuling /* invalid entry */ 454d52f2dc4SMichael Neuling continue; 455d52f2dc4SMichael Neuling 456506e70d1SMichael Neuling /* Branches are read most recent first (ie. mfbhrb 0 is 457506e70d1SMichael Neuling * the most recent branch). 458506e70d1SMichael Neuling * There are two types of valid entries: 459506e70d1SMichael Neuling * 1) a target entry which is the to address of a 460506e70d1SMichael Neuling * computed goto like a blr,bctr,btar. The next 461506e70d1SMichael Neuling * entry read from the bhrb will be branch 462506e70d1SMichael Neuling * corresponding to this target (ie. the actual 463506e70d1SMichael Neuling * blr/bctr/btar instruction). 464506e70d1SMichael Neuling * 2) a from address which is an actual branch. If a 465506e70d1SMichael Neuling * target entry proceeds this, then this is the 466506e70d1SMichael Neuling * matching branch for that target. If this is not 467506e70d1SMichael Neuling * following a target entry, then this is a branch 468506e70d1SMichael Neuling * where the target is given as an immediate field 469506e70d1SMichael Neuling * in the instruction (ie. an i or b form branch). 470506e70d1SMichael Neuling * In this case we need to read the instruction from 471506e70d1SMichael Neuling * memory to determine the target/to address. 472506e70d1SMichael Neuling */ 473d52f2dc4SMichael Neuling 474d52f2dc4SMichael Neuling if (val & BHRB_TARGET) { 475506e70d1SMichael Neuling /* Target branches use two entries 476506e70d1SMichael Neuling * (ie. computed gotos/XL form) 477506e70d1SMichael Neuling */ 478506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].to = addr; 479d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 480d52f2dc4SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 481d52f2dc4SMichael Neuling 482506e70d1SMichael Neuling /* Get from address in next entry */ 483506e70d1SMichael Neuling val = read_bhrb(r_index++); 484506e70d1SMichael Neuling addr = val & BHRB_EA; 485506e70d1SMichael Neuling if (val & BHRB_TARGET) { 486506e70d1SMichael Neuling /* Shouldn't have two targets in a 487506e70d1SMichael Neuling row.. Reset index and try again */ 488506e70d1SMichael Neuling r_index--; 489506e70d1SMichael Neuling addr = 0; 490d52f2dc4SMichael Neuling } 491506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 492506e70d1SMichael Neuling } else { 493506e70d1SMichael Neuling /* Branches to immediate field 494506e70d1SMichael Neuling (ie I or B form) */ 495506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].from = addr; 49669123184SMichael Neuling cpuhw->bhrb_entries[u_index].to = 49769123184SMichael Neuling power_pmu_bhrb_to(addr); 498506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].mispred = pred; 499506e70d1SMichael Neuling cpuhw->bhrb_entries[u_index].predicted = ~pred; 500506e70d1SMichael Neuling } 501506e70d1SMichael Neuling u_index++; 502506e70d1SMichael Neuling 503d52f2dc4SMichael Neuling } 504d52f2dc4SMichael Neuling } 505d52f2dc4SMichael Neuling cpuhw->bhrb_stack.nr = u_index; 506d52f2dc4SMichael Neuling return; 507d52f2dc4SMichael Neuling } 508d52f2dc4SMichael Neuling 509330a1eb7SMichael Ellerman static bool is_ebb_event(struct perf_event *event) 510330a1eb7SMichael Ellerman { 511330a1eb7SMichael Ellerman /* 512330a1eb7SMichael Ellerman * This could be a per-PMU callback, but we'd rather avoid the cost. We 513330a1eb7SMichael Ellerman * check that the PMU supports EBB, meaning those that don't can still 514330a1eb7SMichael Ellerman * use bit 63 of the event code for something else if they wish. 515330a1eb7SMichael Ellerman */ 5164d9690ddSJoel Stanley return (ppmu->flags & PPMU_ARCH_207S) && 5178d7c55d0SMichael Ellerman ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1); 518330a1eb7SMichael Ellerman } 519330a1eb7SMichael Ellerman 520330a1eb7SMichael Ellerman static int ebb_event_check(struct perf_event *event) 521330a1eb7SMichael Ellerman { 522330a1eb7SMichael Ellerman struct perf_event *leader = event->group_leader; 523330a1eb7SMichael Ellerman 524330a1eb7SMichael Ellerman /* Event and group leader must agree on EBB */ 525330a1eb7SMichael Ellerman if (is_ebb_event(leader) != is_ebb_event(event)) 526330a1eb7SMichael Ellerman return -EINVAL; 527330a1eb7SMichael Ellerman 528330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 529330a1eb7SMichael Ellerman if (!(event->attach_state & PERF_ATTACH_TASK)) 530330a1eb7SMichael Ellerman return -EINVAL; 531330a1eb7SMichael Ellerman 532330a1eb7SMichael Ellerman if (!leader->attr.pinned || !leader->attr.exclusive) 533330a1eb7SMichael Ellerman return -EINVAL; 534330a1eb7SMichael Ellerman 53558b5fb00SMichael Ellerman if (event->attr.freq || 53658b5fb00SMichael Ellerman event->attr.inherit || 53758b5fb00SMichael Ellerman event->attr.sample_type || 53858b5fb00SMichael Ellerman event->attr.sample_period || 53958b5fb00SMichael Ellerman event->attr.enable_on_exec) 540330a1eb7SMichael Ellerman return -EINVAL; 541330a1eb7SMichael Ellerman } 542330a1eb7SMichael Ellerman 543330a1eb7SMichael Ellerman return 0; 544330a1eb7SMichael Ellerman } 545330a1eb7SMichael Ellerman 546330a1eb7SMichael Ellerman static void ebb_event_add(struct perf_event *event) 547330a1eb7SMichael Ellerman { 548330a1eb7SMichael Ellerman if (!is_ebb_event(event) || current->thread.used_ebb) 549330a1eb7SMichael Ellerman return; 550330a1eb7SMichael Ellerman 551330a1eb7SMichael Ellerman /* 552330a1eb7SMichael Ellerman * IFF this is the first time we've added an EBB event, set 553330a1eb7SMichael Ellerman * PMXE in the user MMCR0 so we can detect when it's cleared by 554330a1eb7SMichael Ellerman * userspace. We need this so that we can context switch while 555330a1eb7SMichael Ellerman * userspace is in the EBB handler (where PMXE is 0). 556330a1eb7SMichael Ellerman */ 557330a1eb7SMichael Ellerman current->thread.used_ebb = 1; 558330a1eb7SMichael Ellerman current->thread.mmcr0 |= MMCR0_PMXE; 559330a1eb7SMichael Ellerman } 560330a1eb7SMichael Ellerman 561330a1eb7SMichael Ellerman static void ebb_switch_out(unsigned long mmcr0) 562330a1eb7SMichael Ellerman { 563330a1eb7SMichael Ellerman if (!(mmcr0 & MMCR0_EBE)) 564330a1eb7SMichael Ellerman return; 565330a1eb7SMichael Ellerman 566330a1eb7SMichael Ellerman current->thread.siar = mfspr(SPRN_SIAR); 567330a1eb7SMichael Ellerman current->thread.sier = mfspr(SPRN_SIER); 568330a1eb7SMichael Ellerman current->thread.sdar = mfspr(SPRN_SDAR); 569330a1eb7SMichael Ellerman current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK; 570330a1eb7SMichael Ellerman current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK; 571330a1eb7SMichael Ellerman } 572330a1eb7SMichael Ellerman 5739de5cb0fSMichael Ellerman static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw) 574330a1eb7SMichael Ellerman { 5759de5cb0fSMichael Ellerman unsigned long mmcr0 = cpuhw->mmcr[0]; 5769de5cb0fSMichael Ellerman 577330a1eb7SMichael Ellerman if (!ebb) 578330a1eb7SMichael Ellerman goto out; 579330a1eb7SMichael Ellerman 58076cb8a78SMichael Ellerman /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */ 58176cb8a78SMichael Ellerman mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6; 582330a1eb7SMichael Ellerman 583c2e37a26SMichael Ellerman /* 584c2e37a26SMichael Ellerman * Add any bits from the user MMCR0, FC or PMAO. This is compatible 585c2e37a26SMichael Ellerman * with pmao_restore_workaround() because we may add PMAO but we never 586c2e37a26SMichael Ellerman * clear it here. 587c2e37a26SMichael Ellerman */ 588330a1eb7SMichael Ellerman mmcr0 |= current->thread.mmcr0; 589330a1eb7SMichael Ellerman 590c2e37a26SMichael Ellerman /* 591c2e37a26SMichael Ellerman * Be careful not to set PMXE if userspace had it cleared. This is also 592c2e37a26SMichael Ellerman * compatible with pmao_restore_workaround() because it has already 593c2e37a26SMichael Ellerman * cleared PMXE and we leave PMAO alone. 594c2e37a26SMichael Ellerman */ 595330a1eb7SMichael Ellerman if (!(current->thread.mmcr0 & MMCR0_PMXE)) 596330a1eb7SMichael Ellerman mmcr0 &= ~MMCR0_PMXE; 597330a1eb7SMichael Ellerman 598330a1eb7SMichael Ellerman mtspr(SPRN_SIAR, current->thread.siar); 599330a1eb7SMichael Ellerman mtspr(SPRN_SIER, current->thread.sier); 600330a1eb7SMichael Ellerman mtspr(SPRN_SDAR, current->thread.sdar); 6019de5cb0fSMichael Ellerman 6029de5cb0fSMichael Ellerman /* 6039de5cb0fSMichael Ellerman * Merge the kernel & user values of MMCR2. The semantics we implement 6049de5cb0fSMichael Ellerman * are that the user MMCR2 can set bits, ie. cause counters to freeze, 6059de5cb0fSMichael Ellerman * but not clear bits. If a task wants to be able to clear bits, ie. 6069de5cb0fSMichael Ellerman * unfreeze counters, it should not set exclude_xxx in its events and 6079de5cb0fSMichael Ellerman * instead manage the MMCR2 entirely by itself. 6089de5cb0fSMichael Ellerman */ 6099de5cb0fSMichael Ellerman mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2); 610330a1eb7SMichael Ellerman out: 611330a1eb7SMichael Ellerman return mmcr0; 612330a1eb7SMichael Ellerman } 613c2e37a26SMichael Ellerman 614c2e37a26SMichael Ellerman static void pmao_restore_workaround(bool ebb) 615c2e37a26SMichael Ellerman { 616c2e37a26SMichael Ellerman unsigned pmcs[6]; 617c2e37a26SMichael Ellerman 618c2e37a26SMichael Ellerman if (!cpu_has_feature(CPU_FTR_PMAO_BUG)) 619c2e37a26SMichael Ellerman return; 620c2e37a26SMichael Ellerman 621c2e37a26SMichael Ellerman /* 622c2e37a26SMichael Ellerman * On POWER8E there is a hardware defect which affects the PMU context 623c2e37a26SMichael Ellerman * switch logic, ie. power_pmu_disable/enable(). 624c2e37a26SMichael Ellerman * 625c2e37a26SMichael Ellerman * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0 626c2e37a26SMichael Ellerman * by the hardware. Sometime later the actual PMU exception is 627c2e37a26SMichael Ellerman * delivered. 628c2e37a26SMichael Ellerman * 629c2e37a26SMichael Ellerman * If we context switch, or simply disable/enable, the PMU prior to the 630c2e37a26SMichael Ellerman * exception arriving, the exception will be lost when we clear PMAO. 631c2e37a26SMichael Ellerman * 632c2e37a26SMichael Ellerman * When we reenable the PMU, we will write the saved MMCR0 with PMAO 633c2e37a26SMichael Ellerman * set, and this _should_ generate an exception. However because of the 634c2e37a26SMichael Ellerman * defect no exception is generated when we write PMAO, and we get 635c2e37a26SMichael Ellerman * stuck with no counters counting but no exception delivered. 636c2e37a26SMichael Ellerman * 637c2e37a26SMichael Ellerman * The workaround is to detect this case and tweak the hardware to 638c2e37a26SMichael Ellerman * create another pending PMU exception. 639c2e37a26SMichael Ellerman * 640c2e37a26SMichael Ellerman * We do that by setting up PMC6 (cycles) for an imminent overflow and 641c2e37a26SMichael Ellerman * enabling the PMU. That causes a new exception to be generated in the 642c2e37a26SMichael Ellerman * chip, but we don't take it yet because we have interrupts hard 643c2e37a26SMichael Ellerman * disabled. We then write back the PMU state as we want it to be seen 644c2e37a26SMichael Ellerman * by the exception handler. When we reenable interrupts the exception 645c2e37a26SMichael Ellerman * handler will be called and see the correct state. 646c2e37a26SMichael Ellerman * 647c2e37a26SMichael Ellerman * The logic is the same for EBB, except that the exception is gated by 648c2e37a26SMichael Ellerman * us having interrupts hard disabled as well as the fact that we are 649c2e37a26SMichael Ellerman * not in userspace. The exception is finally delivered when we return 650c2e37a26SMichael Ellerman * to userspace. 651c2e37a26SMichael Ellerman */ 652c2e37a26SMichael Ellerman 653c2e37a26SMichael Ellerman /* Only if PMAO is set and PMAO_SYNC is clear */ 654c2e37a26SMichael Ellerman if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO) 655c2e37a26SMichael Ellerman return; 656c2e37a26SMichael Ellerman 657c2e37a26SMichael Ellerman /* If we're doing EBB, only if BESCR[GE] is set */ 658c2e37a26SMichael Ellerman if (ebb && !(current->thread.bescr & BESCR_GE)) 659c2e37a26SMichael Ellerman return; 660c2e37a26SMichael Ellerman 661c2e37a26SMichael Ellerman /* 662c2e37a26SMichael Ellerman * We are already soft-disabled in power_pmu_enable(). We need to hard 66358bffb5bSMadhavan Srinivasan * disable to actually prevent the PMU exception from firing. 664c2e37a26SMichael Ellerman */ 665c2e37a26SMichael Ellerman hard_irq_disable(); 666c2e37a26SMichael Ellerman 667c2e37a26SMichael Ellerman /* 668c2e37a26SMichael Ellerman * This is a bit gross, but we know we're on POWER8E and have 6 PMCs. 669c2e37a26SMichael Ellerman * Using read/write_pmc() in a for loop adds 12 function calls and 670c2e37a26SMichael Ellerman * almost doubles our code size. 671c2e37a26SMichael Ellerman */ 672c2e37a26SMichael Ellerman pmcs[0] = mfspr(SPRN_PMC1); 673c2e37a26SMichael Ellerman pmcs[1] = mfspr(SPRN_PMC2); 674c2e37a26SMichael Ellerman pmcs[2] = mfspr(SPRN_PMC3); 675c2e37a26SMichael Ellerman pmcs[3] = mfspr(SPRN_PMC4); 676c2e37a26SMichael Ellerman pmcs[4] = mfspr(SPRN_PMC5); 677c2e37a26SMichael Ellerman pmcs[5] = mfspr(SPRN_PMC6); 678c2e37a26SMichael Ellerman 679c2e37a26SMichael Ellerman /* Ensure all freeze bits are unset */ 680c2e37a26SMichael Ellerman mtspr(SPRN_MMCR2, 0); 681c2e37a26SMichael Ellerman 682c2e37a26SMichael Ellerman /* Set up PMC6 to overflow in one cycle */ 683c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, 0x7FFFFFFE); 684c2e37a26SMichael Ellerman 685c2e37a26SMichael Ellerman /* Enable exceptions and unfreeze PMC6 */ 686c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO); 687c2e37a26SMichael Ellerman 688c2e37a26SMichael Ellerman /* Now we need to refreeze and restore the PMCs */ 689c2e37a26SMichael Ellerman mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO); 690c2e37a26SMichael Ellerman 691c2e37a26SMichael Ellerman mtspr(SPRN_PMC1, pmcs[0]); 692c2e37a26SMichael Ellerman mtspr(SPRN_PMC2, pmcs[1]); 693c2e37a26SMichael Ellerman mtspr(SPRN_PMC3, pmcs[2]); 694c2e37a26SMichael Ellerman mtspr(SPRN_PMC4, pmcs[3]); 695c2e37a26SMichael Ellerman mtspr(SPRN_PMC5, pmcs[4]); 696c2e37a26SMichael Ellerman mtspr(SPRN_PMC6, pmcs[5]); 697c2e37a26SMichael Ellerman } 698356d8ce3SMadhavan Srinivasan 699356d8ce3SMadhavan Srinivasan static bool use_ic(u64 event) 700356d8ce3SMadhavan Srinivasan { 701356d8ce3SMadhavan Srinivasan if (cpu_has_feature(CPU_FTR_POWER9_DD1) && 702356d8ce3SMadhavan Srinivasan (event == 0x200f2 || event == 0x300f2)) 703356d8ce3SMadhavan Srinivasan return true; 704356d8ce3SMadhavan Srinivasan 705356d8ce3SMadhavan Srinivasan return false; 706356d8ce3SMadhavan Srinivasan } 707f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 708f2699491SMichael Ellerman 709f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs); 710f2699491SMichael Ellerman 711f2699491SMichael Ellerman /* 712f2699491SMichael Ellerman * Read one performance monitor counter (PMC). 713f2699491SMichael Ellerman */ 714f2699491SMichael Ellerman static unsigned long read_pmc(int idx) 715f2699491SMichael Ellerman { 716f2699491SMichael Ellerman unsigned long val; 717f2699491SMichael Ellerman 718f2699491SMichael Ellerman switch (idx) { 719f2699491SMichael Ellerman case 1: 720f2699491SMichael Ellerman val = mfspr(SPRN_PMC1); 721f2699491SMichael Ellerman break; 722f2699491SMichael Ellerman case 2: 723f2699491SMichael Ellerman val = mfspr(SPRN_PMC2); 724f2699491SMichael Ellerman break; 725f2699491SMichael Ellerman case 3: 726f2699491SMichael Ellerman val = mfspr(SPRN_PMC3); 727f2699491SMichael Ellerman break; 728f2699491SMichael Ellerman case 4: 729f2699491SMichael Ellerman val = mfspr(SPRN_PMC4); 730f2699491SMichael Ellerman break; 731f2699491SMichael Ellerman case 5: 732f2699491SMichael Ellerman val = mfspr(SPRN_PMC5); 733f2699491SMichael Ellerman break; 734f2699491SMichael Ellerman case 6: 735f2699491SMichael Ellerman val = mfspr(SPRN_PMC6); 736f2699491SMichael Ellerman break; 737f2699491SMichael Ellerman #ifdef CONFIG_PPC64 738f2699491SMichael Ellerman case 7: 739f2699491SMichael Ellerman val = mfspr(SPRN_PMC7); 740f2699491SMichael Ellerman break; 741f2699491SMichael Ellerman case 8: 742f2699491SMichael Ellerman val = mfspr(SPRN_PMC8); 743f2699491SMichael Ellerman break; 744f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 745f2699491SMichael Ellerman default: 746f2699491SMichael Ellerman printk(KERN_ERR "oops trying to read PMC%d\n", idx); 747f2699491SMichael Ellerman val = 0; 748f2699491SMichael Ellerman } 749f2699491SMichael Ellerman return val; 750f2699491SMichael Ellerman } 751f2699491SMichael Ellerman 752f2699491SMichael Ellerman /* 753f2699491SMichael Ellerman * Write one PMC. 754f2699491SMichael Ellerman */ 755f2699491SMichael Ellerman static void write_pmc(int idx, unsigned long val) 756f2699491SMichael Ellerman { 757f2699491SMichael Ellerman switch (idx) { 758f2699491SMichael Ellerman case 1: 759f2699491SMichael Ellerman mtspr(SPRN_PMC1, val); 760f2699491SMichael Ellerman break; 761f2699491SMichael Ellerman case 2: 762f2699491SMichael Ellerman mtspr(SPRN_PMC2, val); 763f2699491SMichael Ellerman break; 764f2699491SMichael Ellerman case 3: 765f2699491SMichael Ellerman mtspr(SPRN_PMC3, val); 766f2699491SMichael Ellerman break; 767f2699491SMichael Ellerman case 4: 768f2699491SMichael Ellerman mtspr(SPRN_PMC4, val); 769f2699491SMichael Ellerman break; 770f2699491SMichael Ellerman case 5: 771f2699491SMichael Ellerman mtspr(SPRN_PMC5, val); 772f2699491SMichael Ellerman break; 773f2699491SMichael Ellerman case 6: 774f2699491SMichael Ellerman mtspr(SPRN_PMC6, val); 775f2699491SMichael Ellerman break; 776f2699491SMichael Ellerman #ifdef CONFIG_PPC64 777f2699491SMichael Ellerman case 7: 778f2699491SMichael Ellerman mtspr(SPRN_PMC7, val); 779f2699491SMichael Ellerman break; 780f2699491SMichael Ellerman case 8: 781f2699491SMichael Ellerman mtspr(SPRN_PMC8, val); 782f2699491SMichael Ellerman break; 783f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 784f2699491SMichael Ellerman default: 785f2699491SMichael Ellerman printk(KERN_ERR "oops trying to write PMC%d\n", idx); 786f2699491SMichael Ellerman } 787f2699491SMichael Ellerman } 788f2699491SMichael Ellerman 7895f6d0380SAnshuman Khandual /* Called from sysrq_handle_showregs() */ 7905f6d0380SAnshuman Khandual void perf_event_print_debug(void) 7915f6d0380SAnshuman Khandual { 7925f6d0380SAnshuman Khandual unsigned long sdar, sier, flags; 7935f6d0380SAnshuman Khandual u32 pmcs[MAX_HWEVENTS]; 7945f6d0380SAnshuman Khandual int i; 7955f6d0380SAnshuman Khandual 7964917fcb5SRavi Bangoria if (!ppmu) { 7974917fcb5SRavi Bangoria pr_info("Performance monitor hardware not registered.\n"); 7984917fcb5SRavi Bangoria return; 7994917fcb5SRavi Bangoria } 8004917fcb5SRavi Bangoria 8015f6d0380SAnshuman Khandual if (!ppmu->n_counter) 8025f6d0380SAnshuman Khandual return; 8035f6d0380SAnshuman Khandual 8045f6d0380SAnshuman Khandual local_irq_save(flags); 8055f6d0380SAnshuman Khandual 8065f6d0380SAnshuman Khandual pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d", 8075f6d0380SAnshuman Khandual smp_processor_id(), ppmu->name, ppmu->n_counter); 8085f6d0380SAnshuman Khandual 8095f6d0380SAnshuman Khandual for (i = 0; i < ppmu->n_counter; i++) 8105f6d0380SAnshuman Khandual pmcs[i] = read_pmc(i + 1); 8115f6d0380SAnshuman Khandual 8125f6d0380SAnshuman Khandual for (; i < MAX_HWEVENTS; i++) 8135f6d0380SAnshuman Khandual pmcs[i] = 0xdeadbeef; 8145f6d0380SAnshuman Khandual 8155f6d0380SAnshuman Khandual pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n", 8165f6d0380SAnshuman Khandual pmcs[0], pmcs[1], pmcs[2], pmcs[3]); 8175f6d0380SAnshuman Khandual 8185f6d0380SAnshuman Khandual if (ppmu->n_counter > 4) 8195f6d0380SAnshuman Khandual pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n", 8205f6d0380SAnshuman Khandual pmcs[4], pmcs[5], pmcs[6], pmcs[7]); 8215f6d0380SAnshuman Khandual 8225f6d0380SAnshuman Khandual pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n", 8235f6d0380SAnshuman Khandual mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA)); 8245f6d0380SAnshuman Khandual 8255f6d0380SAnshuman Khandual sdar = sier = 0; 8265f6d0380SAnshuman Khandual #ifdef CONFIG_PPC64 8275f6d0380SAnshuman Khandual sdar = mfspr(SPRN_SDAR); 8285f6d0380SAnshuman Khandual 8295f6d0380SAnshuman Khandual if (ppmu->flags & PPMU_HAS_SIER) 8305f6d0380SAnshuman Khandual sier = mfspr(SPRN_SIER); 8315f6d0380SAnshuman Khandual 8324d9690ddSJoel Stanley if (ppmu->flags & PPMU_ARCH_207S) { 8335f6d0380SAnshuman Khandual pr_info("MMCR2: %016lx EBBHR: %016lx\n", 8345f6d0380SAnshuman Khandual mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR)); 8355f6d0380SAnshuman Khandual pr_info("EBBRR: %016lx BESCR: %016lx\n", 8365f6d0380SAnshuman Khandual mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR)); 8375f6d0380SAnshuman Khandual } 8385f6d0380SAnshuman Khandual #endif 8395f6d0380SAnshuman Khandual pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n", 8405f6d0380SAnshuman Khandual mfspr(SPRN_SIAR), sdar, sier); 8415f6d0380SAnshuman Khandual 8425f6d0380SAnshuman Khandual local_irq_restore(flags); 8435f6d0380SAnshuman Khandual } 8445f6d0380SAnshuman Khandual 845f2699491SMichael Ellerman /* 846f2699491SMichael Ellerman * Check if a set of events can all go on the PMU at once. 847f2699491SMichael Ellerman * If they can't, this will look at alternative codes for the events 848f2699491SMichael Ellerman * and see if any combination of alternative codes is feasible. 849f2699491SMichael Ellerman * The feasible set is returned in event_id[]. 850f2699491SMichael Ellerman */ 851f2699491SMichael Ellerman static int power_check_constraints(struct cpu_hw_events *cpuhw, 852f2699491SMichael Ellerman u64 event_id[], unsigned int cflags[], 853f2699491SMichael Ellerman int n_ev) 854f2699491SMichael Ellerman { 855f2699491SMichael Ellerman unsigned long mask, value, nv; 856f2699491SMichael Ellerman unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS]; 857f2699491SMichael Ellerman int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS]; 858f2699491SMichael Ellerman int i, j; 859f2699491SMichael Ellerman unsigned long addf = ppmu->add_fields; 860f2699491SMichael Ellerman unsigned long tadd = ppmu->test_adder; 861f2699491SMichael Ellerman 862f2699491SMichael Ellerman if (n_ev > ppmu->n_counter) 863f2699491SMichael Ellerman return -1; 864f2699491SMichael Ellerman 865f2699491SMichael Ellerman /* First see if the events will go on as-is */ 866f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 867f2699491SMichael Ellerman if ((cflags[i] & PPMU_LIMITED_PMC_REQD) 868f2699491SMichael Ellerman && !ppmu->limited_pmc_event(event_id[i])) { 869f2699491SMichael Ellerman ppmu->get_alternatives(event_id[i], cflags[i], 870f2699491SMichael Ellerman cpuhw->alternatives[i]); 871f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][0]; 872f2699491SMichael Ellerman } 873f2699491SMichael Ellerman if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0], 874f2699491SMichael Ellerman &cpuhw->avalues[i][0])) 875f2699491SMichael Ellerman return -1; 876f2699491SMichael Ellerman } 877f2699491SMichael Ellerman value = mask = 0; 878f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 879f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][0]) + 880f2699491SMichael Ellerman (value & cpuhw->avalues[i][0] & addf); 881f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) != 0 || 882f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][0]) & 883f2699491SMichael Ellerman cpuhw->amasks[i][0]) != 0) 884f2699491SMichael Ellerman break; 885f2699491SMichael Ellerman value = nv; 886f2699491SMichael Ellerman mask |= cpuhw->amasks[i][0]; 887f2699491SMichael Ellerman } 888f2699491SMichael Ellerman if (i == n_ev) 889f2699491SMichael Ellerman return 0; /* all OK */ 890f2699491SMichael Ellerman 891f2699491SMichael Ellerman /* doesn't work, gather alternatives... */ 892f2699491SMichael Ellerman if (!ppmu->get_alternatives) 893f2699491SMichael Ellerman return -1; 894f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) { 895f2699491SMichael Ellerman choice[i] = 0; 896f2699491SMichael Ellerman n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i], 897f2699491SMichael Ellerman cpuhw->alternatives[i]); 898f2699491SMichael Ellerman for (j = 1; j < n_alt[i]; ++j) 899f2699491SMichael Ellerman ppmu->get_constraint(cpuhw->alternatives[i][j], 900f2699491SMichael Ellerman &cpuhw->amasks[i][j], 901f2699491SMichael Ellerman &cpuhw->avalues[i][j]); 902f2699491SMichael Ellerman } 903f2699491SMichael Ellerman 904f2699491SMichael Ellerman /* enumerate all possibilities and see if any will work */ 905f2699491SMichael Ellerman i = 0; 906f2699491SMichael Ellerman j = -1; 907f2699491SMichael Ellerman value = mask = nv = 0; 908f2699491SMichael Ellerman while (i < n_ev) { 909f2699491SMichael Ellerman if (j >= 0) { 910f2699491SMichael Ellerman /* we're backtracking, restore context */ 911f2699491SMichael Ellerman value = svalues[i]; 912f2699491SMichael Ellerman mask = smasks[i]; 913f2699491SMichael Ellerman j = choice[i]; 914f2699491SMichael Ellerman } 915f2699491SMichael Ellerman /* 916f2699491SMichael Ellerman * See if any alternative k for event_id i, 917f2699491SMichael Ellerman * where k > j, will satisfy the constraints. 918f2699491SMichael Ellerman */ 919f2699491SMichael Ellerman while (++j < n_alt[i]) { 920f2699491SMichael Ellerman nv = (value | cpuhw->avalues[i][j]) + 921f2699491SMichael Ellerman (value & cpuhw->avalues[i][j] & addf); 922f2699491SMichael Ellerman if ((((nv + tadd) ^ value) & mask) == 0 && 923f2699491SMichael Ellerman (((nv + tadd) ^ cpuhw->avalues[i][j]) 924f2699491SMichael Ellerman & cpuhw->amasks[i][j]) == 0) 925f2699491SMichael Ellerman break; 926f2699491SMichael Ellerman } 927f2699491SMichael Ellerman if (j >= n_alt[i]) { 928f2699491SMichael Ellerman /* 929f2699491SMichael Ellerman * No feasible alternative, backtrack 930f2699491SMichael Ellerman * to event_id i-1 and continue enumerating its 931f2699491SMichael Ellerman * alternatives from where we got up to. 932f2699491SMichael Ellerman */ 933f2699491SMichael Ellerman if (--i < 0) 934f2699491SMichael Ellerman return -1; 935f2699491SMichael Ellerman } else { 936f2699491SMichael Ellerman /* 937f2699491SMichael Ellerman * Found a feasible alternative for event_id i, 938f2699491SMichael Ellerman * remember where we got up to with this event_id, 939f2699491SMichael Ellerman * go on to the next event_id, and start with 940f2699491SMichael Ellerman * the first alternative for it. 941f2699491SMichael Ellerman */ 942f2699491SMichael Ellerman choice[i] = j; 943f2699491SMichael Ellerman svalues[i] = value; 944f2699491SMichael Ellerman smasks[i] = mask; 945f2699491SMichael Ellerman value = nv; 946f2699491SMichael Ellerman mask |= cpuhw->amasks[i][j]; 947f2699491SMichael Ellerman ++i; 948f2699491SMichael Ellerman j = -1; 949f2699491SMichael Ellerman } 950f2699491SMichael Ellerman } 951f2699491SMichael Ellerman 952f2699491SMichael Ellerman /* OK, we have a feasible combination, tell the caller the solution */ 953f2699491SMichael Ellerman for (i = 0; i < n_ev; ++i) 954f2699491SMichael Ellerman event_id[i] = cpuhw->alternatives[i][choice[i]]; 955f2699491SMichael Ellerman return 0; 956f2699491SMichael Ellerman } 957f2699491SMichael Ellerman 958f2699491SMichael Ellerman /* 959f2699491SMichael Ellerman * Check if newly-added events have consistent settings for 960f2699491SMichael Ellerman * exclude_{user,kernel,hv} with each other and any previously 961f2699491SMichael Ellerman * added events. 962f2699491SMichael Ellerman */ 963f2699491SMichael Ellerman static int check_excludes(struct perf_event **ctrs, unsigned int cflags[], 964f2699491SMichael Ellerman int n_prev, int n_new) 965f2699491SMichael Ellerman { 966f2699491SMichael Ellerman int eu = 0, ek = 0, eh = 0; 967f2699491SMichael Ellerman int i, n, first; 968f2699491SMichael Ellerman struct perf_event *event; 969f2699491SMichael Ellerman 9709de5cb0fSMichael Ellerman /* 9719de5cb0fSMichael Ellerman * If the PMU we're on supports per event exclude settings then we 9729de5cb0fSMichael Ellerman * don't need to do any of this logic. NB. This assumes no PMU has both 9739de5cb0fSMichael Ellerman * per event exclude and limited PMCs. 9749de5cb0fSMichael Ellerman */ 9759de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 9769de5cb0fSMichael Ellerman return 0; 9779de5cb0fSMichael Ellerman 978f2699491SMichael Ellerman n = n_prev + n_new; 979f2699491SMichael Ellerman if (n <= 1) 980f2699491SMichael Ellerman return 0; 981f2699491SMichael Ellerman 982f2699491SMichael Ellerman first = 1; 983f2699491SMichael Ellerman for (i = 0; i < n; ++i) { 984f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) { 985f2699491SMichael Ellerman cflags[i] &= ~PPMU_LIMITED_PMC_REQD; 986f2699491SMichael Ellerman continue; 987f2699491SMichael Ellerman } 988f2699491SMichael Ellerman event = ctrs[i]; 989f2699491SMichael Ellerman if (first) { 990f2699491SMichael Ellerman eu = event->attr.exclude_user; 991f2699491SMichael Ellerman ek = event->attr.exclude_kernel; 992f2699491SMichael Ellerman eh = event->attr.exclude_hv; 993f2699491SMichael Ellerman first = 0; 994f2699491SMichael Ellerman } else if (event->attr.exclude_user != eu || 995f2699491SMichael Ellerman event->attr.exclude_kernel != ek || 996f2699491SMichael Ellerman event->attr.exclude_hv != eh) { 997f2699491SMichael Ellerman return -EAGAIN; 998f2699491SMichael Ellerman } 999f2699491SMichael Ellerman } 1000f2699491SMichael Ellerman 1001f2699491SMichael Ellerman if (eu || ek || eh) 1002f2699491SMichael Ellerman for (i = 0; i < n; ++i) 1003f2699491SMichael Ellerman if (cflags[i] & PPMU_LIMITED_PMC_OK) 1004f2699491SMichael Ellerman cflags[i] |= PPMU_LIMITED_PMC_REQD; 1005f2699491SMichael Ellerman 1006f2699491SMichael Ellerman return 0; 1007f2699491SMichael Ellerman } 1008f2699491SMichael Ellerman 1009f2699491SMichael Ellerman static u64 check_and_compute_delta(u64 prev, u64 val) 1010f2699491SMichael Ellerman { 1011f2699491SMichael Ellerman u64 delta = (val - prev) & 0xfffffffful; 1012f2699491SMichael Ellerman 1013f2699491SMichael Ellerman /* 1014f2699491SMichael Ellerman * POWER7 can roll back counter values, if the new value is smaller 1015f2699491SMichael Ellerman * than the previous value it will cause the delta and the counter to 1016f2699491SMichael Ellerman * have bogus values unless we rolled a counter over. If a coutner is 1017f2699491SMichael Ellerman * rolled back, it will be smaller, but within 256, which is the maximum 1018027dfac6SMichael Ellerman * number of events to rollback at once. If we detect a rollback 1019f2699491SMichael Ellerman * return 0. This can lead to a small lack of precision in the 1020f2699491SMichael Ellerman * counters. 1021f2699491SMichael Ellerman */ 1022f2699491SMichael Ellerman if (prev > val && (prev - val) < 256) 1023f2699491SMichael Ellerman delta = 0; 1024f2699491SMichael Ellerman 1025f2699491SMichael Ellerman return delta; 1026f2699491SMichael Ellerman } 1027f2699491SMichael Ellerman 1028f2699491SMichael Ellerman static void power_pmu_read(struct perf_event *event) 1029f2699491SMichael Ellerman { 1030f2699491SMichael Ellerman s64 val, delta, prev; 1031356d8ce3SMadhavan Srinivasan struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1032f2699491SMichael Ellerman 1033f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1034f2699491SMichael Ellerman return; 1035f2699491SMichael Ellerman 1036f2699491SMichael Ellerman if (!event->hw.idx) 1037f2699491SMichael Ellerman return; 1038330a1eb7SMichael Ellerman 1039330a1eb7SMichael Ellerman if (is_ebb_event(event)) { 1040330a1eb7SMichael Ellerman val = read_pmc(event->hw.idx); 1041356d8ce3SMadhavan Srinivasan if (use_ic(event->attr.config)) { 1042356d8ce3SMadhavan Srinivasan val = mfspr(SPRN_IC); 1043356d8ce3SMadhavan Srinivasan if (val > cpuhw->ic_init) 1044356d8ce3SMadhavan Srinivasan val = val - cpuhw->ic_init; 1045356d8ce3SMadhavan Srinivasan else 1046356d8ce3SMadhavan Srinivasan val = val + (0 - cpuhw->ic_init); 1047356d8ce3SMadhavan Srinivasan } 1048330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, val); 1049330a1eb7SMichael Ellerman return; 1050330a1eb7SMichael Ellerman } 1051330a1eb7SMichael Ellerman 1052f2699491SMichael Ellerman /* 1053f2699491SMichael Ellerman * Performance monitor interrupts come even when interrupts 1054f2699491SMichael Ellerman * are soft-disabled, as long as interrupts are hard-enabled. 1055f2699491SMichael Ellerman * Therefore we treat them like NMIs. 1056f2699491SMichael Ellerman */ 1057f2699491SMichael Ellerman do { 1058f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1059f2699491SMichael Ellerman barrier(); 1060f2699491SMichael Ellerman val = read_pmc(event->hw.idx); 1061356d8ce3SMadhavan Srinivasan if (use_ic(event->attr.config)) { 1062356d8ce3SMadhavan Srinivasan val = mfspr(SPRN_IC); 1063356d8ce3SMadhavan Srinivasan if (val > cpuhw->ic_init) 1064356d8ce3SMadhavan Srinivasan val = val - cpuhw->ic_init; 1065356d8ce3SMadhavan Srinivasan else 1066356d8ce3SMadhavan Srinivasan val = val + (0 - cpuhw->ic_init); 1067356d8ce3SMadhavan Srinivasan } 1068f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1069f2699491SMichael Ellerman if (!delta) 1070f2699491SMichael Ellerman return; 1071f2699491SMichael Ellerman } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev); 1072f2699491SMichael Ellerman 1073f2699491SMichael Ellerman local64_add(delta, &event->count); 1074f5602941SAnton Blanchard 1075f5602941SAnton Blanchard /* 1076f5602941SAnton Blanchard * A number of places program the PMC with (0x80000000 - period_left). 1077f5602941SAnton Blanchard * We never want period_left to be less than 1 because we will program 1078f5602941SAnton Blanchard * the PMC with a value >= 0x800000000 and an edge detected PMC will 1079f5602941SAnton Blanchard * roll around to 0 before taking an exception. We have seen this 1080f5602941SAnton Blanchard * on POWER8. 1081f5602941SAnton Blanchard * 1082f5602941SAnton Blanchard * To fix this, clamp the minimum value of period_left to 1. 1083f5602941SAnton Blanchard */ 1084f5602941SAnton Blanchard do { 1085f5602941SAnton Blanchard prev = local64_read(&event->hw.period_left); 1086f5602941SAnton Blanchard val = prev - delta; 1087f5602941SAnton Blanchard if (val < 1) 1088f5602941SAnton Blanchard val = 1; 1089f5602941SAnton Blanchard } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev); 1090f2699491SMichael Ellerman } 1091f2699491SMichael Ellerman 1092f2699491SMichael Ellerman /* 1093f2699491SMichael Ellerman * On some machines, PMC5 and PMC6 can't be written, don't respect 1094f2699491SMichael Ellerman * the freeze conditions, and don't generate interrupts. This tells 1095f2699491SMichael Ellerman * us if `event' is using such a PMC. 1096f2699491SMichael Ellerman */ 1097f2699491SMichael Ellerman static int is_limited_pmc(int pmcnum) 1098f2699491SMichael Ellerman { 1099f2699491SMichael Ellerman return (ppmu->flags & PPMU_LIMITED_PMC5_6) 1100f2699491SMichael Ellerman && (pmcnum == 5 || pmcnum == 6); 1101f2699491SMichael Ellerman } 1102f2699491SMichael Ellerman 1103f2699491SMichael Ellerman static void freeze_limited_counters(struct cpu_hw_events *cpuhw, 1104f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1105f2699491SMichael Ellerman { 1106f2699491SMichael Ellerman struct perf_event *event; 1107f2699491SMichael Ellerman u64 val, prev, delta; 1108f2699491SMichael Ellerman int i; 1109f2699491SMichael Ellerman 1110f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1111f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1112f2699491SMichael Ellerman if (!event->hw.idx) 1113f2699491SMichael Ellerman continue; 1114f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1115f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1116f2699491SMichael Ellerman event->hw.idx = 0; 1117f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 1118f2699491SMichael Ellerman if (delta) 1119f2699491SMichael Ellerman local64_add(delta, &event->count); 1120f2699491SMichael Ellerman } 1121f2699491SMichael Ellerman } 1122f2699491SMichael Ellerman 1123f2699491SMichael Ellerman static void thaw_limited_counters(struct cpu_hw_events *cpuhw, 1124f2699491SMichael Ellerman unsigned long pmc5, unsigned long pmc6) 1125f2699491SMichael Ellerman { 1126f2699491SMichael Ellerman struct perf_event *event; 1127f2699491SMichael Ellerman u64 val, prev; 1128f2699491SMichael Ellerman int i; 1129f2699491SMichael Ellerman 1130f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) { 1131f2699491SMichael Ellerman event = cpuhw->limited_counter[i]; 1132f2699491SMichael Ellerman event->hw.idx = cpuhw->limited_hwidx[i]; 1133f2699491SMichael Ellerman val = (event->hw.idx == 5) ? pmc5 : pmc6; 1134f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 1135f2699491SMichael Ellerman if (check_and_compute_delta(prev, val)) 1136f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1137f2699491SMichael Ellerman perf_event_update_userpage(event); 1138f2699491SMichael Ellerman } 1139f2699491SMichael Ellerman } 1140f2699491SMichael Ellerman 1141f2699491SMichael Ellerman /* 1142f2699491SMichael Ellerman * Since limited events don't respect the freeze conditions, we 1143f2699491SMichael Ellerman * have to read them immediately after freezing or unfreezing the 1144f2699491SMichael Ellerman * other events. We try to keep the values from the limited 1145f2699491SMichael Ellerman * events as consistent as possible by keeping the delay (in 1146f2699491SMichael Ellerman * cycles and instructions) between freezing/unfreezing and reading 1147f2699491SMichael Ellerman * the limited events as small and consistent as possible. 1148f2699491SMichael Ellerman * Therefore, if any limited events are in use, we read them 1149f2699491SMichael Ellerman * both, and always in the same order, to minimize variability, 1150f2699491SMichael Ellerman * and do it inside the same asm that writes MMCR0. 1151f2699491SMichael Ellerman */ 1152f2699491SMichael Ellerman static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0) 1153f2699491SMichael Ellerman { 1154f2699491SMichael Ellerman unsigned long pmc5, pmc6; 1155f2699491SMichael Ellerman 1156f2699491SMichael Ellerman if (!cpuhw->n_limited) { 1157f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1158f2699491SMichael Ellerman return; 1159f2699491SMichael Ellerman } 1160f2699491SMichael Ellerman 1161f2699491SMichael Ellerman /* 1162f2699491SMichael Ellerman * Write MMCR0, then read PMC5 and PMC6 immediately. 1163f2699491SMichael Ellerman * To ensure we don't get a performance monitor interrupt 1164f2699491SMichael Ellerman * between writing MMCR0 and freezing/thawing the limited 1165f2699491SMichael Ellerman * events, we first write MMCR0 with the event overflow 1166f2699491SMichael Ellerman * interrupt enable bits turned off. 1167f2699491SMichael Ellerman */ 1168f2699491SMichael Ellerman asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5" 1169f2699491SMichael Ellerman : "=&r" (pmc5), "=&r" (pmc6) 1170f2699491SMichael Ellerman : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)), 1171f2699491SMichael Ellerman "i" (SPRN_MMCR0), 1172f2699491SMichael Ellerman "i" (SPRN_PMC5), "i" (SPRN_PMC6)); 1173f2699491SMichael Ellerman 1174f2699491SMichael Ellerman if (mmcr0 & MMCR0_FC) 1175f2699491SMichael Ellerman freeze_limited_counters(cpuhw, pmc5, pmc6); 1176f2699491SMichael Ellerman else 1177f2699491SMichael Ellerman thaw_limited_counters(cpuhw, pmc5, pmc6); 1178f2699491SMichael Ellerman 1179f2699491SMichael Ellerman /* 1180f2699491SMichael Ellerman * Write the full MMCR0 including the event overflow interrupt 1181f2699491SMichael Ellerman * enable bits, if necessary. 1182f2699491SMichael Ellerman */ 1183f2699491SMichael Ellerman if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE)) 1184f2699491SMichael Ellerman mtspr(SPRN_MMCR0, mmcr0); 1185f2699491SMichael Ellerman } 1186f2699491SMichael Ellerman 1187f2699491SMichael Ellerman /* 1188f2699491SMichael Ellerman * Disable all events to prevent PMU interrupts and to allow 1189f2699491SMichael Ellerman * events to be added or removed. 1190f2699491SMichael Ellerman */ 1191f2699491SMichael Ellerman static void power_pmu_disable(struct pmu *pmu) 1192f2699491SMichael Ellerman { 1193f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1194330a1eb7SMichael Ellerman unsigned long flags, mmcr0, val; 1195f2699491SMichael Ellerman 1196f2699491SMichael Ellerman if (!ppmu) 1197f2699491SMichael Ellerman return; 1198f2699491SMichael Ellerman local_irq_save(flags); 119969111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1200f2699491SMichael Ellerman 1201f2699491SMichael Ellerman if (!cpuhw->disabled) { 1202f2699491SMichael Ellerman /* 1203f2699491SMichael Ellerman * Check if we ever enabled the PMU on this cpu. 1204f2699491SMichael Ellerman */ 1205f2699491SMichael Ellerman if (!cpuhw->pmcs_enabled) { 1206f2699491SMichael Ellerman ppc_enable_pmcs(); 1207f2699491SMichael Ellerman cpuhw->pmcs_enabled = 1; 1208f2699491SMichael Ellerman } 1209f2699491SMichael Ellerman 1210f2699491SMichael Ellerman /* 121176cb8a78SMichael Ellerman * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56 1212378a6ee9SMichael Ellerman */ 1213330a1eb7SMichael Ellerman val = mmcr0 = mfspr(SPRN_MMCR0); 1214378a6ee9SMichael Ellerman val |= MMCR0_FC; 121576cb8a78SMichael Ellerman val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO | 121676cb8a78SMichael Ellerman MMCR0_FC56); 1217378a6ee9SMichael Ellerman 1218378a6ee9SMichael Ellerman /* 1219378a6ee9SMichael Ellerman * The barrier is to make sure the mtspr has been 1220378a6ee9SMichael Ellerman * executed and the PMU has frozen the events etc. 1221378a6ee9SMichael Ellerman * before we return. 1222378a6ee9SMichael Ellerman */ 1223378a6ee9SMichael Ellerman write_mmcr0(cpuhw, val); 1224378a6ee9SMichael Ellerman mb(); 1225378a6ee9SMichael Ellerman 1226378a6ee9SMichael Ellerman /* 1227f2699491SMichael Ellerman * Disable instruction sampling if it was enabled 1228f2699491SMichael Ellerman */ 1229f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1230f2699491SMichael Ellerman mtspr(SPRN_MMCRA, 1231f2699491SMichael Ellerman cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1232f2699491SMichael Ellerman mb(); 1233f2699491SMichael Ellerman } 1234f2699491SMichael Ellerman 1235378a6ee9SMichael Ellerman cpuhw->disabled = 1; 1236378a6ee9SMichael Ellerman cpuhw->n_added = 0; 1237330a1eb7SMichael Ellerman 1238330a1eb7SMichael Ellerman ebb_switch_out(mmcr0); 1239f2699491SMichael Ellerman } 1240330a1eb7SMichael Ellerman 1241f2699491SMichael Ellerman local_irq_restore(flags); 1242f2699491SMichael Ellerman } 1243f2699491SMichael Ellerman 1244f2699491SMichael Ellerman /* 1245f2699491SMichael Ellerman * Re-enable all events if disable == 0. 1246f2699491SMichael Ellerman * If we were previously disabled and events were added, then 1247f2699491SMichael Ellerman * put the new config on the PMU. 1248f2699491SMichael Ellerman */ 1249f2699491SMichael Ellerman static void power_pmu_enable(struct pmu *pmu) 1250f2699491SMichael Ellerman { 1251f2699491SMichael Ellerman struct perf_event *event; 1252f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1253f2699491SMichael Ellerman unsigned long flags; 1254f2699491SMichael Ellerman long i; 1255330a1eb7SMichael Ellerman unsigned long val, mmcr0; 1256f2699491SMichael Ellerman s64 left; 1257f2699491SMichael Ellerman unsigned int hwc_index[MAX_HWEVENTS]; 1258f2699491SMichael Ellerman int n_lim; 1259f2699491SMichael Ellerman int idx; 1260330a1eb7SMichael Ellerman bool ebb; 1261f2699491SMichael Ellerman 1262f2699491SMichael Ellerman if (!ppmu) 1263f2699491SMichael Ellerman return; 1264f2699491SMichael Ellerman local_irq_save(flags); 12650a48843dSMichael Ellerman 126669111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 12670a48843dSMichael Ellerman if (!cpuhw->disabled) 12680a48843dSMichael Ellerman goto out; 12690a48843dSMichael Ellerman 12704ea355b5SMichael Ellerman if (cpuhw->n_events == 0) { 12714ea355b5SMichael Ellerman ppc_set_pmu_inuse(0); 12724ea355b5SMichael Ellerman goto out; 12734ea355b5SMichael Ellerman } 12744ea355b5SMichael Ellerman 1275f2699491SMichael Ellerman cpuhw->disabled = 0; 1276f2699491SMichael Ellerman 1277f2699491SMichael Ellerman /* 1278330a1eb7SMichael Ellerman * EBB requires an exclusive group and all events must have the EBB 1279330a1eb7SMichael Ellerman * flag set, or not set, so we can just check a single event. Also we 1280330a1eb7SMichael Ellerman * know we have at least one event. 1281330a1eb7SMichael Ellerman */ 1282330a1eb7SMichael Ellerman ebb = is_ebb_event(cpuhw->event[0]); 1283330a1eb7SMichael Ellerman 1284330a1eb7SMichael Ellerman /* 1285f2699491SMichael Ellerman * If we didn't change anything, or only removed events, 1286f2699491SMichael Ellerman * no need to recalculate MMCR* settings and reset the PMCs. 1287f2699491SMichael Ellerman * Just reenable the PMU with the current MMCR* settings 1288f2699491SMichael Ellerman * (possibly updated for removal of events). 1289f2699491SMichael Ellerman */ 1290f2699491SMichael Ellerman if (!cpuhw->n_added) { 1291f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1292f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1293f2699491SMichael Ellerman goto out_enable; 1294f2699491SMichael Ellerman } 1295f2699491SMichael Ellerman 1296f2699491SMichael Ellerman /* 129779a4cb28SMichael Ellerman * Clear all MMCR settings and recompute them for the new set of events. 1298f2699491SMichael Ellerman */ 129979a4cb28SMichael Ellerman memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr)); 130079a4cb28SMichael Ellerman 1301f2699491SMichael Ellerman if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index, 13028abd818fSMichael Ellerman cpuhw->mmcr, cpuhw->event)) { 1303f2699491SMichael Ellerman /* shouldn't ever get here */ 1304f2699491SMichael Ellerman printk(KERN_ERR "oops compute_mmcr failed\n"); 1305f2699491SMichael Ellerman goto out; 1306f2699491SMichael Ellerman } 1307f2699491SMichael Ellerman 13089de5cb0fSMichael Ellerman if (!(ppmu->flags & PPMU_ARCH_207S)) { 1309f2699491SMichael Ellerman /* 13109de5cb0fSMichael Ellerman * Add in MMCR0 freeze bits corresponding to the attr.exclude_* 13119de5cb0fSMichael Ellerman * bits for the first event. We have already checked that all 13129de5cb0fSMichael Ellerman * events have the same value for these bits as the first event. 1313f2699491SMichael Ellerman */ 1314f2699491SMichael Ellerman event = cpuhw->event[0]; 1315f2699491SMichael Ellerman if (event->attr.exclude_user) 1316f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCP; 1317f2699491SMichael Ellerman if (event->attr.exclude_kernel) 1318f2699491SMichael Ellerman cpuhw->mmcr[0] |= freeze_events_kernel; 1319f2699491SMichael Ellerman if (event->attr.exclude_hv) 1320f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_FCHV; 13219de5cb0fSMichael Ellerman } 1322f2699491SMichael Ellerman 1323f2699491SMichael Ellerman /* 1324f2699491SMichael Ellerman * Write the new configuration to MMCR* with the freeze 1325f2699491SMichael Ellerman * bit set and set the hardware events to their initial values. 1326f2699491SMichael Ellerman * Then unfreeze the events. 1327f2699491SMichael Ellerman */ 1328f2699491SMichael Ellerman ppc_set_pmu_inuse(1); 1329f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE); 1330f2699491SMichael Ellerman mtspr(SPRN_MMCR1, cpuhw->mmcr[1]); 1331f2699491SMichael Ellerman mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)) 1332f2699491SMichael Ellerman | MMCR0_FC); 13339de5cb0fSMichael Ellerman if (ppmu->flags & PPMU_ARCH_207S) 13349de5cb0fSMichael Ellerman mtspr(SPRN_MMCR2, cpuhw->mmcr[3]); 1335f2699491SMichael Ellerman 1336f2699491SMichael Ellerman /* 1337f2699491SMichael Ellerman * Read off any pre-existing events that need to move 1338f2699491SMichael Ellerman * to another PMC. 1339f2699491SMichael Ellerman */ 1340f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1341f2699491SMichael Ellerman event = cpuhw->event[i]; 1342f2699491SMichael Ellerman if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) { 1343f2699491SMichael Ellerman power_pmu_read(event); 1344f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1345f2699491SMichael Ellerman event->hw.idx = 0; 1346f2699491SMichael Ellerman } 1347f2699491SMichael Ellerman } 1348f2699491SMichael Ellerman 1349f2699491SMichael Ellerman /* 1350f2699491SMichael Ellerman * Initialize the PMCs for all the new and moved events. 1351f2699491SMichael Ellerman */ 1352f2699491SMichael Ellerman cpuhw->n_limited = n_lim = 0; 1353f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1354f2699491SMichael Ellerman event = cpuhw->event[i]; 1355f2699491SMichael Ellerman if (event->hw.idx) 1356f2699491SMichael Ellerman continue; 1357f2699491SMichael Ellerman idx = hwc_index[i] + 1; 1358f2699491SMichael Ellerman if (is_limited_pmc(idx)) { 1359f2699491SMichael Ellerman cpuhw->limited_counter[n_lim] = event; 1360f2699491SMichael Ellerman cpuhw->limited_hwidx[n_lim] = idx; 1361f2699491SMichael Ellerman ++n_lim; 1362f2699491SMichael Ellerman continue; 1363f2699491SMichael Ellerman } 1364330a1eb7SMichael Ellerman 1365330a1eb7SMichael Ellerman if (ebb) 1366330a1eb7SMichael Ellerman val = local64_read(&event->hw.prev_count); 1367330a1eb7SMichael Ellerman else { 1368f2699491SMichael Ellerman val = 0; 1369f2699491SMichael Ellerman if (event->hw.sample_period) { 1370f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1371f2699491SMichael Ellerman if (left < 0x80000000L) 1372f2699491SMichael Ellerman val = 0x80000000L - left; 1373f2699491SMichael Ellerman } 1374f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 1375330a1eb7SMichael Ellerman } 1376330a1eb7SMichael Ellerman 1377f2699491SMichael Ellerman event->hw.idx = idx; 1378f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1379f2699491SMichael Ellerman val = 0; 1380f2699491SMichael Ellerman write_pmc(idx, val); 1381330a1eb7SMichael Ellerman 1382f2699491SMichael Ellerman perf_event_update_userpage(event); 1383f2699491SMichael Ellerman } 1384f2699491SMichael Ellerman cpuhw->n_limited = n_lim; 1385f2699491SMichael Ellerman cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE; 1386f2699491SMichael Ellerman 1387f2699491SMichael Ellerman out_enable: 1388c2e37a26SMichael Ellerman pmao_restore_workaround(ebb); 1389c2e37a26SMichael Ellerman 13909de5cb0fSMichael Ellerman mmcr0 = ebb_switch_in(ebb, cpuhw); 1391330a1eb7SMichael Ellerman 1392f2699491SMichael Ellerman mb(); 1393b4d6c06cSAnshuman Khandual if (cpuhw->bhrb_users) 1394b4d6c06cSAnshuman Khandual ppmu->config_bhrb(cpuhw->bhrb_filter); 1395b4d6c06cSAnshuman Khandual 1396330a1eb7SMichael Ellerman write_mmcr0(cpuhw, mmcr0); 1397f2699491SMichael Ellerman 1398f2699491SMichael Ellerman /* 1399f2699491SMichael Ellerman * Enable instruction sampling if necessary 1400f2699491SMichael Ellerman */ 1401f2699491SMichael Ellerman if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) { 1402f2699491SMichael Ellerman mb(); 1403f2699491SMichael Ellerman mtspr(SPRN_MMCRA, cpuhw->mmcr[2]); 1404f2699491SMichael Ellerman } 1405f2699491SMichael Ellerman 1406f2699491SMichael Ellerman out: 14073925f46bSAnshuman Khandual 1408f2699491SMichael Ellerman local_irq_restore(flags); 1409f2699491SMichael Ellerman } 1410f2699491SMichael Ellerman 1411f2699491SMichael Ellerman static int collect_events(struct perf_event *group, int max_count, 1412f2699491SMichael Ellerman struct perf_event *ctrs[], u64 *events, 1413f2699491SMichael Ellerman unsigned int *flags) 1414f2699491SMichael Ellerman { 1415f2699491SMichael Ellerman int n = 0; 1416f2699491SMichael Ellerman struct perf_event *event; 1417f2699491SMichael Ellerman 1418f2699491SMichael Ellerman if (!is_software_event(group)) { 1419f2699491SMichael Ellerman if (n >= max_count) 1420f2699491SMichael Ellerman return -1; 1421f2699491SMichael Ellerman ctrs[n] = group; 1422f2699491SMichael Ellerman flags[n] = group->hw.event_base; 1423f2699491SMichael Ellerman events[n++] = group->hw.config; 1424f2699491SMichael Ellerman } 1425f2699491SMichael Ellerman list_for_each_entry(event, &group->sibling_list, group_entry) { 1426f2699491SMichael Ellerman if (!is_software_event(event) && 1427f2699491SMichael Ellerman event->state != PERF_EVENT_STATE_OFF) { 1428f2699491SMichael Ellerman if (n >= max_count) 1429f2699491SMichael Ellerman return -1; 1430f2699491SMichael Ellerman ctrs[n] = event; 1431f2699491SMichael Ellerman flags[n] = event->hw.event_base; 1432f2699491SMichael Ellerman events[n++] = event->hw.config; 1433f2699491SMichael Ellerman } 1434f2699491SMichael Ellerman } 1435f2699491SMichael Ellerman return n; 1436f2699491SMichael Ellerman } 1437f2699491SMichael Ellerman 1438f2699491SMichael Ellerman /* 1439f2699491SMichael Ellerman * Add a event to the PMU. 1440f2699491SMichael Ellerman * If all events are not already frozen, then we disable and 1441f2699491SMichael Ellerman * re-enable the PMU in order to get hw_perf_enable to do the 1442f2699491SMichael Ellerman * actual work of reconfiguring the PMU. 1443f2699491SMichael Ellerman */ 1444f2699491SMichael Ellerman static int power_pmu_add(struct perf_event *event, int ef_flags) 1445f2699491SMichael Ellerman { 1446f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1447f2699491SMichael Ellerman unsigned long flags; 1448f2699491SMichael Ellerman int n0; 1449f2699491SMichael Ellerman int ret = -EAGAIN; 1450f2699491SMichael Ellerman 1451f2699491SMichael Ellerman local_irq_save(flags); 1452f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1453f2699491SMichael Ellerman 1454f2699491SMichael Ellerman /* 1455f2699491SMichael Ellerman * Add the event to the list (if there is room) 1456f2699491SMichael Ellerman * and check whether the total set is still feasible. 1457f2699491SMichael Ellerman */ 145869111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1459f2699491SMichael Ellerman n0 = cpuhw->n_events; 1460f2699491SMichael Ellerman if (n0 >= ppmu->n_counter) 1461f2699491SMichael Ellerman goto out; 1462f2699491SMichael Ellerman cpuhw->event[n0] = event; 1463f2699491SMichael Ellerman cpuhw->events[n0] = event->hw.config; 1464f2699491SMichael Ellerman cpuhw->flags[n0] = event->hw.event_base; 1465f2699491SMichael Ellerman 1466f53d168cSsukadev@linux.vnet.ibm.com /* 1467f53d168cSsukadev@linux.vnet.ibm.com * This event may have been disabled/stopped in record_and_restart() 1468f53d168cSsukadev@linux.vnet.ibm.com * because we exceeded the ->event_limit. If re-starting the event, 1469f53d168cSsukadev@linux.vnet.ibm.com * clear the ->hw.state (STOPPED and UPTODATE flags), so the user 1470f53d168cSsukadev@linux.vnet.ibm.com * notification is re-enabled. 1471f53d168cSsukadev@linux.vnet.ibm.com */ 1472f2699491SMichael Ellerman if (!(ef_flags & PERF_EF_START)) 1473f2699491SMichael Ellerman event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 1474f53d168cSsukadev@linux.vnet.ibm.com else 1475f53d168cSsukadev@linux.vnet.ibm.com event->hw.state = 0; 1476f2699491SMichael Ellerman 1477f2699491SMichael Ellerman /* 1478f2699491SMichael Ellerman * If group events scheduling transaction was started, 1479f2699491SMichael Ellerman * skip the schedulability test here, it will be performed 1480f2699491SMichael Ellerman * at commit time(->commit_txn) as a whole 1481f2699491SMichael Ellerman */ 14828f3e5684SSukadev Bhattiprolu if (cpuhw->txn_flags & PERF_PMU_TXN_ADD) 1483f2699491SMichael Ellerman goto nocheck; 1484f2699491SMichael Ellerman 1485f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1)) 1486f2699491SMichael Ellerman goto out; 1487f2699491SMichael Ellerman if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1)) 1488f2699491SMichael Ellerman goto out; 1489f2699491SMichael Ellerman event->hw.config = cpuhw->events[n0]; 1490f2699491SMichael Ellerman 1491f2699491SMichael Ellerman nocheck: 1492330a1eb7SMichael Ellerman ebb_event_add(event); 1493330a1eb7SMichael Ellerman 1494f2699491SMichael Ellerman ++cpuhw->n_events; 1495f2699491SMichael Ellerman ++cpuhw->n_added; 1496f2699491SMichael Ellerman 1497f2699491SMichael Ellerman ret = 0; 1498f2699491SMichael Ellerman out: 1499ff3d79dcSAnshuman Khandual if (has_branch_stack(event)) { 15003925f46bSAnshuman Khandual power_pmu_bhrb_enable(event); 1501ff3d79dcSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 1502ff3d79dcSAnshuman Khandual event->attr.branch_sample_type); 1503ff3d79dcSAnshuman Khandual } 15043925f46bSAnshuman Khandual 1505356d8ce3SMadhavan Srinivasan /* 1506356d8ce3SMadhavan Srinivasan * Workaround for POWER9 DD1 to use the Instruction Counter 1507356d8ce3SMadhavan Srinivasan * register value for instruction counting 1508356d8ce3SMadhavan Srinivasan */ 1509356d8ce3SMadhavan Srinivasan if (use_ic(event->attr.config)) 1510356d8ce3SMadhavan Srinivasan cpuhw->ic_init = mfspr(SPRN_IC); 1511356d8ce3SMadhavan Srinivasan 1512f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1513f2699491SMichael Ellerman local_irq_restore(flags); 1514f2699491SMichael Ellerman return ret; 1515f2699491SMichael Ellerman } 1516f2699491SMichael Ellerman 1517f2699491SMichael Ellerman /* 1518f2699491SMichael Ellerman * Remove a event from the PMU. 1519f2699491SMichael Ellerman */ 1520f2699491SMichael Ellerman static void power_pmu_del(struct perf_event *event, int ef_flags) 1521f2699491SMichael Ellerman { 1522f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1523f2699491SMichael Ellerman long i; 1524f2699491SMichael Ellerman unsigned long flags; 1525f2699491SMichael Ellerman 1526f2699491SMichael Ellerman local_irq_save(flags); 1527f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1528f2699491SMichael Ellerman 1529f2699491SMichael Ellerman power_pmu_read(event); 1530f2699491SMichael Ellerman 153169111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1532f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 1533f2699491SMichael Ellerman if (event == cpuhw->event[i]) { 1534f2699491SMichael Ellerman while (++i < cpuhw->n_events) { 1535f2699491SMichael Ellerman cpuhw->event[i-1] = cpuhw->event[i]; 1536f2699491SMichael Ellerman cpuhw->events[i-1] = cpuhw->events[i]; 1537f2699491SMichael Ellerman cpuhw->flags[i-1] = cpuhw->flags[i]; 1538f2699491SMichael Ellerman } 1539f2699491SMichael Ellerman --cpuhw->n_events; 1540f2699491SMichael Ellerman ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); 1541f2699491SMichael Ellerman if (event->hw.idx) { 1542f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1543f2699491SMichael Ellerman event->hw.idx = 0; 1544f2699491SMichael Ellerman } 1545f2699491SMichael Ellerman perf_event_update_userpage(event); 1546f2699491SMichael Ellerman break; 1547f2699491SMichael Ellerman } 1548f2699491SMichael Ellerman } 1549f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_limited; ++i) 1550f2699491SMichael Ellerman if (event == cpuhw->limited_counter[i]) 1551f2699491SMichael Ellerman break; 1552f2699491SMichael Ellerman if (i < cpuhw->n_limited) { 1553f2699491SMichael Ellerman while (++i < cpuhw->n_limited) { 1554f2699491SMichael Ellerman cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i]; 1555f2699491SMichael Ellerman cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i]; 1556f2699491SMichael Ellerman } 1557f2699491SMichael Ellerman --cpuhw->n_limited; 1558f2699491SMichael Ellerman } 1559f2699491SMichael Ellerman if (cpuhw->n_events == 0) { 1560f2699491SMichael Ellerman /* disable exceptions if no events are running */ 1561f2699491SMichael Ellerman cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE); 1562f2699491SMichael Ellerman } 1563f2699491SMichael Ellerman 15643925f46bSAnshuman Khandual if (has_branch_stack(event)) 15653925f46bSAnshuman Khandual power_pmu_bhrb_disable(event); 15663925f46bSAnshuman Khandual 1567f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1568f2699491SMichael Ellerman local_irq_restore(flags); 1569f2699491SMichael Ellerman } 1570f2699491SMichael Ellerman 1571f2699491SMichael Ellerman /* 1572f2699491SMichael Ellerman * POWER-PMU does not support disabling individual counters, hence 1573f2699491SMichael Ellerman * program their cycle counter to their max value and ignore the interrupts. 1574f2699491SMichael Ellerman */ 1575f2699491SMichael Ellerman 1576f2699491SMichael Ellerman static void power_pmu_start(struct perf_event *event, int ef_flags) 1577f2699491SMichael Ellerman { 1578f2699491SMichael Ellerman unsigned long flags; 1579f2699491SMichael Ellerman s64 left; 1580f2699491SMichael Ellerman unsigned long val; 1581f2699491SMichael Ellerman 1582f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1583f2699491SMichael Ellerman return; 1584f2699491SMichael Ellerman 1585f2699491SMichael Ellerman if (!(event->hw.state & PERF_HES_STOPPED)) 1586f2699491SMichael Ellerman return; 1587f2699491SMichael Ellerman 1588f2699491SMichael Ellerman if (ef_flags & PERF_EF_RELOAD) 1589f2699491SMichael Ellerman WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); 1590f2699491SMichael Ellerman 1591f2699491SMichael Ellerman local_irq_save(flags); 1592f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1593f2699491SMichael Ellerman 1594f2699491SMichael Ellerman event->hw.state = 0; 1595f2699491SMichael Ellerman left = local64_read(&event->hw.period_left); 1596f2699491SMichael Ellerman 1597f2699491SMichael Ellerman val = 0; 1598f2699491SMichael Ellerman if (left < 0x80000000L) 1599f2699491SMichael Ellerman val = 0x80000000L - left; 1600f2699491SMichael Ellerman 1601f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 1602f2699491SMichael Ellerman 1603f2699491SMichael Ellerman perf_event_update_userpage(event); 1604f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1605f2699491SMichael Ellerman local_irq_restore(flags); 1606f2699491SMichael Ellerman } 1607f2699491SMichael Ellerman 1608f2699491SMichael Ellerman static void power_pmu_stop(struct perf_event *event, int ef_flags) 1609f2699491SMichael Ellerman { 1610f2699491SMichael Ellerman unsigned long flags; 1611f2699491SMichael Ellerman 1612f2699491SMichael Ellerman if (!event->hw.idx || !event->hw.sample_period) 1613f2699491SMichael Ellerman return; 1614f2699491SMichael Ellerman 1615f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) 1616f2699491SMichael Ellerman return; 1617f2699491SMichael Ellerman 1618f2699491SMichael Ellerman local_irq_save(flags); 1619f2699491SMichael Ellerman perf_pmu_disable(event->pmu); 1620f2699491SMichael Ellerman 1621f2699491SMichael Ellerman power_pmu_read(event); 1622f2699491SMichael Ellerman event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE; 1623f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 1624f2699491SMichael Ellerman 1625f2699491SMichael Ellerman perf_event_update_userpage(event); 1626f2699491SMichael Ellerman perf_pmu_enable(event->pmu); 1627f2699491SMichael Ellerman local_irq_restore(flags); 1628f2699491SMichael Ellerman } 1629f2699491SMichael Ellerman 1630f2699491SMichael Ellerman /* 1631f2699491SMichael Ellerman * Start group events scheduling transaction 1632f2699491SMichael Ellerman * Set the flag to make pmu::enable() not perform the 1633f2699491SMichael Ellerman * schedulability test, it will be performed at commit time 1634fbbe0701SSukadev Bhattiprolu * 1635fbbe0701SSukadev Bhattiprolu * We only support PERF_PMU_TXN_ADD transactions. Save the 1636fbbe0701SSukadev Bhattiprolu * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD 1637fbbe0701SSukadev Bhattiprolu * transactions. 1638f2699491SMichael Ellerman */ 1639fbbe0701SSukadev Bhattiprolu static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags) 1640f2699491SMichael Ellerman { 164169111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1642f2699491SMichael Ellerman 1643fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */ 1644fbbe0701SSukadev Bhattiprolu 1645fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = txn_flags; 1646fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1647fbbe0701SSukadev Bhattiprolu return; 1648fbbe0701SSukadev Bhattiprolu 1649f2699491SMichael Ellerman perf_pmu_disable(pmu); 1650f2699491SMichael Ellerman cpuhw->n_txn_start = cpuhw->n_events; 1651f2699491SMichael Ellerman } 1652f2699491SMichael Ellerman 1653f2699491SMichael Ellerman /* 1654f2699491SMichael Ellerman * Stop group events scheduling transaction 1655f2699491SMichael Ellerman * Clear the flag and pmu::enable() will perform the 1656f2699491SMichael Ellerman * schedulability test. 1657f2699491SMichael Ellerman */ 1658e51df2c1SAnton Blanchard static void power_pmu_cancel_txn(struct pmu *pmu) 1659f2699491SMichael Ellerman { 166069111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 1661fbbe0701SSukadev Bhattiprolu unsigned int txn_flags; 1662fbbe0701SSukadev Bhattiprolu 1663fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1664fbbe0701SSukadev Bhattiprolu 1665fbbe0701SSukadev Bhattiprolu txn_flags = cpuhw->txn_flags; 1666fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1667fbbe0701SSukadev Bhattiprolu if (txn_flags & ~PERF_PMU_TXN_ADD) 1668fbbe0701SSukadev Bhattiprolu return; 1669f2699491SMichael Ellerman 1670f2699491SMichael Ellerman perf_pmu_enable(pmu); 1671f2699491SMichael Ellerman } 1672f2699491SMichael Ellerman 1673f2699491SMichael Ellerman /* 1674f2699491SMichael Ellerman * Commit group events scheduling transaction 1675f2699491SMichael Ellerman * Perform the group schedulability test as a whole 1676f2699491SMichael Ellerman * Return 0 if success 1677f2699491SMichael Ellerman */ 1678e51df2c1SAnton Blanchard static int power_pmu_commit_txn(struct pmu *pmu) 1679f2699491SMichael Ellerman { 1680f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1681f2699491SMichael Ellerman long i, n; 1682f2699491SMichael Ellerman 1683f2699491SMichael Ellerman if (!ppmu) 1684f2699491SMichael Ellerman return -EAGAIN; 1685fbbe0701SSukadev Bhattiprolu 168669111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 1687fbbe0701SSukadev Bhattiprolu WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */ 1688fbbe0701SSukadev Bhattiprolu 1689fbbe0701SSukadev Bhattiprolu if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) { 1690fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1691fbbe0701SSukadev Bhattiprolu return 0; 1692fbbe0701SSukadev Bhattiprolu } 1693fbbe0701SSukadev Bhattiprolu 1694f2699491SMichael Ellerman n = cpuhw->n_events; 1695f2699491SMichael Ellerman if (check_excludes(cpuhw->event, cpuhw->flags, 0, n)) 1696f2699491SMichael Ellerman return -EAGAIN; 1697f2699491SMichael Ellerman i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n); 1698f2699491SMichael Ellerman if (i < 0) 1699f2699491SMichael Ellerman return -EAGAIN; 1700f2699491SMichael Ellerman 1701f2699491SMichael Ellerman for (i = cpuhw->n_txn_start; i < n; ++i) 1702f2699491SMichael Ellerman cpuhw->event[i]->hw.config = cpuhw->events[i]; 1703f2699491SMichael Ellerman 1704fbbe0701SSukadev Bhattiprolu cpuhw->txn_flags = 0; 1705f2699491SMichael Ellerman perf_pmu_enable(pmu); 1706f2699491SMichael Ellerman return 0; 1707f2699491SMichael Ellerman } 1708f2699491SMichael Ellerman 1709f2699491SMichael Ellerman /* 1710f2699491SMichael Ellerman * Return 1 if we might be able to put event on a limited PMC, 1711f2699491SMichael Ellerman * or 0 if not. 1712f2699491SMichael Ellerman * A event can only go on a limited PMC if it counts something 1713f2699491SMichael Ellerman * that a limited PMC can count, doesn't require interrupts, and 1714f2699491SMichael Ellerman * doesn't exclude any processor mode. 1715f2699491SMichael Ellerman */ 1716f2699491SMichael Ellerman static int can_go_on_limited_pmc(struct perf_event *event, u64 ev, 1717f2699491SMichael Ellerman unsigned int flags) 1718f2699491SMichael Ellerman { 1719f2699491SMichael Ellerman int n; 1720f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1721f2699491SMichael Ellerman 1722f2699491SMichael Ellerman if (event->attr.exclude_user 1723f2699491SMichael Ellerman || event->attr.exclude_kernel 1724f2699491SMichael Ellerman || event->attr.exclude_hv 1725f2699491SMichael Ellerman || event->attr.sample_period) 1726f2699491SMichael Ellerman return 0; 1727f2699491SMichael Ellerman 1728f2699491SMichael Ellerman if (ppmu->limited_pmc_event(ev)) 1729f2699491SMichael Ellerman return 1; 1730f2699491SMichael Ellerman 1731f2699491SMichael Ellerman /* 1732f2699491SMichael Ellerman * The requested event_id isn't on a limited PMC already; 1733f2699491SMichael Ellerman * see if any alternative code goes on a limited PMC. 1734f2699491SMichael Ellerman */ 1735f2699491SMichael Ellerman if (!ppmu->get_alternatives) 1736f2699491SMichael Ellerman return 0; 1737f2699491SMichael Ellerman 1738f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD; 1739f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1740f2699491SMichael Ellerman 1741f2699491SMichael Ellerman return n > 0; 1742f2699491SMichael Ellerman } 1743f2699491SMichael Ellerman 1744f2699491SMichael Ellerman /* 1745f2699491SMichael Ellerman * Find an alternative event_id that goes on a normal PMC, if possible, 1746f2699491SMichael Ellerman * and return the event_id code, or 0 if there is no such alternative. 1747f2699491SMichael Ellerman * (Note: event_id code 0 is "don't count" on all machines.) 1748f2699491SMichael Ellerman */ 1749f2699491SMichael Ellerman static u64 normal_pmc_alternative(u64 ev, unsigned long flags) 1750f2699491SMichael Ellerman { 1751f2699491SMichael Ellerman u64 alt[MAX_EVENT_ALTERNATIVES]; 1752f2699491SMichael Ellerman int n; 1753f2699491SMichael Ellerman 1754f2699491SMichael Ellerman flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD); 1755f2699491SMichael Ellerman n = ppmu->get_alternatives(ev, flags, alt); 1756f2699491SMichael Ellerman if (!n) 1757f2699491SMichael Ellerman return 0; 1758f2699491SMichael Ellerman return alt[0]; 1759f2699491SMichael Ellerman } 1760f2699491SMichael Ellerman 1761f2699491SMichael Ellerman /* Number of perf_events counting hardware events */ 1762f2699491SMichael Ellerman static atomic_t num_events; 1763f2699491SMichael Ellerman /* Used to avoid races in calling reserve/release_pmc_hardware */ 1764f2699491SMichael Ellerman static DEFINE_MUTEX(pmc_reserve_mutex); 1765f2699491SMichael Ellerman 1766f2699491SMichael Ellerman /* 1767f2699491SMichael Ellerman * Release the PMU if this is the last perf_event. 1768f2699491SMichael Ellerman */ 1769f2699491SMichael Ellerman static void hw_perf_event_destroy(struct perf_event *event) 1770f2699491SMichael Ellerman { 1771f2699491SMichael Ellerman if (!atomic_add_unless(&num_events, -1, 1)) { 1772f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1773f2699491SMichael Ellerman if (atomic_dec_return(&num_events) == 0) 1774f2699491SMichael Ellerman release_pmc_hardware(); 1775f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1776f2699491SMichael Ellerman } 1777f2699491SMichael Ellerman } 1778f2699491SMichael Ellerman 1779f2699491SMichael Ellerman /* 1780f2699491SMichael Ellerman * Translate a generic cache event_id config to a raw event_id code. 1781f2699491SMichael Ellerman */ 1782f2699491SMichael Ellerman static int hw_perf_cache_event(u64 config, u64 *eventp) 1783f2699491SMichael Ellerman { 1784f2699491SMichael Ellerman unsigned long type, op, result; 1785f2699491SMichael Ellerman int ev; 1786f2699491SMichael Ellerman 1787f2699491SMichael Ellerman if (!ppmu->cache_events) 1788f2699491SMichael Ellerman return -EINVAL; 1789f2699491SMichael Ellerman 1790f2699491SMichael Ellerman /* unpack config */ 1791f2699491SMichael Ellerman type = config & 0xff; 1792f2699491SMichael Ellerman op = (config >> 8) & 0xff; 1793f2699491SMichael Ellerman result = (config >> 16) & 0xff; 1794f2699491SMichael Ellerman 1795f2699491SMichael Ellerman if (type >= PERF_COUNT_HW_CACHE_MAX || 1796f2699491SMichael Ellerman op >= PERF_COUNT_HW_CACHE_OP_MAX || 1797f2699491SMichael Ellerman result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 1798f2699491SMichael Ellerman return -EINVAL; 1799f2699491SMichael Ellerman 1800f2699491SMichael Ellerman ev = (*ppmu->cache_events)[type][op][result]; 1801f2699491SMichael Ellerman if (ev == 0) 1802f2699491SMichael Ellerman return -EOPNOTSUPP; 1803f2699491SMichael Ellerman if (ev == -1) 1804f2699491SMichael Ellerman return -EINVAL; 1805f2699491SMichael Ellerman *eventp = ev; 1806f2699491SMichael Ellerman return 0; 1807f2699491SMichael Ellerman } 1808f2699491SMichael Ellerman 1809f2699491SMichael Ellerman static int power_pmu_event_init(struct perf_event *event) 1810f2699491SMichael Ellerman { 1811f2699491SMichael Ellerman u64 ev; 1812f2699491SMichael Ellerman unsigned long flags; 1813f2699491SMichael Ellerman struct perf_event *ctrs[MAX_HWEVENTS]; 1814f2699491SMichael Ellerman u64 events[MAX_HWEVENTS]; 1815f2699491SMichael Ellerman unsigned int cflags[MAX_HWEVENTS]; 1816f2699491SMichael Ellerman int n; 1817f2699491SMichael Ellerman int err; 1818f2699491SMichael Ellerman struct cpu_hw_events *cpuhw; 1819f2699491SMichael Ellerman 1820f2699491SMichael Ellerman if (!ppmu) 1821f2699491SMichael Ellerman return -ENOENT; 1822f2699491SMichael Ellerman 18233925f46bSAnshuman Khandual if (has_branch_stack(event)) { 18243925f46bSAnshuman Khandual /* PMU has BHRB enabled */ 18254d9690ddSJoel Stanley if (!(ppmu->flags & PPMU_ARCH_207S)) 18265375871dSLinus Torvalds return -EOPNOTSUPP; 18273925f46bSAnshuman Khandual } 18285375871dSLinus Torvalds 1829f2699491SMichael Ellerman switch (event->attr.type) { 1830f2699491SMichael Ellerman case PERF_TYPE_HARDWARE: 1831f2699491SMichael Ellerman ev = event->attr.config; 1832f2699491SMichael Ellerman if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0) 1833f2699491SMichael Ellerman return -EOPNOTSUPP; 1834f2699491SMichael Ellerman ev = ppmu->generic_events[ev]; 1835f2699491SMichael Ellerman break; 1836f2699491SMichael Ellerman case PERF_TYPE_HW_CACHE: 1837f2699491SMichael Ellerman err = hw_perf_cache_event(event->attr.config, &ev); 1838f2699491SMichael Ellerman if (err) 1839f2699491SMichael Ellerman return err; 1840f2699491SMichael Ellerman break; 1841f2699491SMichael Ellerman case PERF_TYPE_RAW: 1842f2699491SMichael Ellerman ev = event->attr.config; 1843f2699491SMichael Ellerman break; 1844f2699491SMichael Ellerman default: 1845f2699491SMichael Ellerman return -ENOENT; 1846f2699491SMichael Ellerman } 1847f2699491SMichael Ellerman 1848f2699491SMichael Ellerman event->hw.config_base = ev; 1849f2699491SMichael Ellerman event->hw.idx = 0; 1850f2699491SMichael Ellerman 1851f2699491SMichael Ellerman /* 1852f2699491SMichael Ellerman * If we are not running on a hypervisor, force the 1853f2699491SMichael Ellerman * exclude_hv bit to 0 so that we don't care what 1854f2699491SMichael Ellerman * the user set it to. 1855f2699491SMichael Ellerman */ 1856f2699491SMichael Ellerman if (!firmware_has_feature(FW_FEATURE_LPAR)) 1857f2699491SMichael Ellerman event->attr.exclude_hv = 0; 1858f2699491SMichael Ellerman 1859f2699491SMichael Ellerman /* 1860f2699491SMichael Ellerman * If this is a per-task event, then we can use 1861f2699491SMichael Ellerman * PM_RUN_* events interchangeably with their non RUN_* 1862f2699491SMichael Ellerman * equivalents, e.g. PM_RUN_CYC instead of PM_CYC. 1863f2699491SMichael Ellerman * XXX we should check if the task is an idle task. 1864f2699491SMichael Ellerman */ 1865f2699491SMichael Ellerman flags = 0; 1866f2699491SMichael Ellerman if (event->attach_state & PERF_ATTACH_TASK) 1867f2699491SMichael Ellerman flags |= PPMU_ONLY_COUNT_RUN; 1868f2699491SMichael Ellerman 1869f2699491SMichael Ellerman /* 1870f2699491SMichael Ellerman * If this machine has limited events, check whether this 1871f2699491SMichael Ellerman * event_id could go on a limited event. 1872f2699491SMichael Ellerman */ 1873f2699491SMichael Ellerman if (ppmu->flags & PPMU_LIMITED_PMC5_6) { 1874f2699491SMichael Ellerman if (can_go_on_limited_pmc(event, ev, flags)) { 1875f2699491SMichael Ellerman flags |= PPMU_LIMITED_PMC_OK; 1876f2699491SMichael Ellerman } else if (ppmu->limited_pmc_event(ev)) { 1877f2699491SMichael Ellerman /* 1878f2699491SMichael Ellerman * The requested event_id is on a limited PMC, 1879f2699491SMichael Ellerman * but we can't use a limited PMC; see if any 1880f2699491SMichael Ellerman * alternative goes on a normal PMC. 1881f2699491SMichael Ellerman */ 1882f2699491SMichael Ellerman ev = normal_pmc_alternative(ev, flags); 1883f2699491SMichael Ellerman if (!ev) 1884f2699491SMichael Ellerman return -EINVAL; 1885f2699491SMichael Ellerman } 1886f2699491SMichael Ellerman } 1887f2699491SMichael Ellerman 1888330a1eb7SMichael Ellerman /* Extra checks for EBB */ 1889330a1eb7SMichael Ellerman err = ebb_event_check(event); 1890330a1eb7SMichael Ellerman if (err) 1891330a1eb7SMichael Ellerman return err; 1892330a1eb7SMichael Ellerman 1893f2699491SMichael Ellerman /* 1894f2699491SMichael Ellerman * If this is in a group, check if it can go on with all the 1895f2699491SMichael Ellerman * other hardware events in the group. We assume the event 1896f2699491SMichael Ellerman * hasn't been linked into its leader's sibling list at this point. 1897f2699491SMichael Ellerman */ 1898f2699491SMichael Ellerman n = 0; 1899f2699491SMichael Ellerman if (event->group_leader != event) { 1900f2699491SMichael Ellerman n = collect_events(event->group_leader, ppmu->n_counter - 1, 1901f2699491SMichael Ellerman ctrs, events, cflags); 1902f2699491SMichael Ellerman if (n < 0) 1903f2699491SMichael Ellerman return -EINVAL; 1904f2699491SMichael Ellerman } 1905f2699491SMichael Ellerman events[n] = ev; 1906f2699491SMichael Ellerman ctrs[n] = event; 1907f2699491SMichael Ellerman cflags[n] = flags; 1908f2699491SMichael Ellerman if (check_excludes(ctrs, cflags, n, 1)) 1909f2699491SMichael Ellerman return -EINVAL; 1910f2699491SMichael Ellerman 1911f2699491SMichael Ellerman cpuhw = &get_cpu_var(cpu_hw_events); 1912f2699491SMichael Ellerman err = power_check_constraints(cpuhw, events, cflags, n + 1); 19133925f46bSAnshuman Khandual 19143925f46bSAnshuman Khandual if (has_branch_stack(event)) { 19153925f46bSAnshuman Khandual cpuhw->bhrb_filter = ppmu->bhrb_filter_map( 19163925f46bSAnshuman Khandual event->attr.branch_sample_type); 19173925f46bSAnshuman Khandual 191868de8867SJan Stancek if (cpuhw->bhrb_filter == -1) { 191968de8867SJan Stancek put_cpu_var(cpu_hw_events); 19203925f46bSAnshuman Khandual return -EOPNOTSUPP; 19213925f46bSAnshuman Khandual } 192268de8867SJan Stancek } 19233925f46bSAnshuman Khandual 1924f2699491SMichael Ellerman put_cpu_var(cpu_hw_events); 1925f2699491SMichael Ellerman if (err) 1926f2699491SMichael Ellerman return -EINVAL; 1927f2699491SMichael Ellerman 1928f2699491SMichael Ellerman event->hw.config = events[n]; 1929f2699491SMichael Ellerman event->hw.event_base = cflags[n]; 1930f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 1931f2699491SMichael Ellerman local64_set(&event->hw.period_left, event->hw.last_period); 1932f2699491SMichael Ellerman 1933f2699491SMichael Ellerman /* 1934330a1eb7SMichael Ellerman * For EBB events we just context switch the PMC value, we don't do any 1935330a1eb7SMichael Ellerman * of the sample_period logic. We use hw.prev_count for this. 1936330a1eb7SMichael Ellerman */ 1937330a1eb7SMichael Ellerman if (is_ebb_event(event)) 1938330a1eb7SMichael Ellerman local64_set(&event->hw.prev_count, 0); 1939330a1eb7SMichael Ellerman 1940330a1eb7SMichael Ellerman /* 1941f2699491SMichael Ellerman * See if we need to reserve the PMU. 1942f2699491SMichael Ellerman * If no events are currently in use, then we have to take a 1943f2699491SMichael Ellerman * mutex to ensure that we don't race with another task doing 1944f2699491SMichael Ellerman * reserve_pmc_hardware or release_pmc_hardware. 1945f2699491SMichael Ellerman */ 1946f2699491SMichael Ellerman err = 0; 1947f2699491SMichael Ellerman if (!atomic_inc_not_zero(&num_events)) { 1948f2699491SMichael Ellerman mutex_lock(&pmc_reserve_mutex); 1949f2699491SMichael Ellerman if (atomic_read(&num_events) == 0 && 1950f2699491SMichael Ellerman reserve_pmc_hardware(perf_event_interrupt)) 1951f2699491SMichael Ellerman err = -EBUSY; 1952f2699491SMichael Ellerman else 1953f2699491SMichael Ellerman atomic_inc(&num_events); 1954f2699491SMichael Ellerman mutex_unlock(&pmc_reserve_mutex); 1955f2699491SMichael Ellerman } 1956f2699491SMichael Ellerman event->destroy = hw_perf_event_destroy; 1957f2699491SMichael Ellerman 1958f2699491SMichael Ellerman return err; 1959f2699491SMichael Ellerman } 1960f2699491SMichael Ellerman 19615375871dSLinus Torvalds static int power_pmu_event_idx(struct perf_event *event) 19625375871dSLinus Torvalds { 19635375871dSLinus Torvalds return event->hw.idx; 19645375871dSLinus Torvalds } 19655375871dSLinus Torvalds 19661c53a270SSukadev Bhattiprolu ssize_t power_events_sysfs_show(struct device *dev, 19671c53a270SSukadev Bhattiprolu struct device_attribute *attr, char *page) 19681c53a270SSukadev Bhattiprolu { 19691c53a270SSukadev Bhattiprolu struct perf_pmu_events_attr *pmu_attr; 19701c53a270SSukadev Bhattiprolu 19711c53a270SSukadev Bhattiprolu pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr); 19721c53a270SSukadev Bhattiprolu 19731c53a270SSukadev Bhattiprolu return sprintf(page, "event=0x%02llx\n", pmu_attr->id); 19741c53a270SSukadev Bhattiprolu } 19751c53a270SSukadev Bhattiprolu 1976e51df2c1SAnton Blanchard static struct pmu power_pmu = { 1977f2699491SMichael Ellerman .pmu_enable = power_pmu_enable, 1978f2699491SMichael Ellerman .pmu_disable = power_pmu_disable, 1979f2699491SMichael Ellerman .event_init = power_pmu_event_init, 1980f2699491SMichael Ellerman .add = power_pmu_add, 1981f2699491SMichael Ellerman .del = power_pmu_del, 1982f2699491SMichael Ellerman .start = power_pmu_start, 1983f2699491SMichael Ellerman .stop = power_pmu_stop, 1984f2699491SMichael Ellerman .read = power_pmu_read, 1985f2699491SMichael Ellerman .start_txn = power_pmu_start_txn, 1986f2699491SMichael Ellerman .cancel_txn = power_pmu_cancel_txn, 1987f2699491SMichael Ellerman .commit_txn = power_pmu_commit_txn, 19885375871dSLinus Torvalds .event_idx = power_pmu_event_idx, 1989acba3c7eSPeter Zijlstra .sched_task = power_pmu_sched_task, 1990f2699491SMichael Ellerman }; 1991f2699491SMichael Ellerman 1992f2699491SMichael Ellerman /* 1993f2699491SMichael Ellerman * A counter has overflowed; update its count and record 1994f2699491SMichael Ellerman * things if requested. Note that interrupts are hard-disabled 1995f2699491SMichael Ellerman * here so there is no possibility of being interrupted. 1996f2699491SMichael Ellerman */ 1997f2699491SMichael Ellerman static void record_and_restart(struct perf_event *event, unsigned long val, 1998f2699491SMichael Ellerman struct pt_regs *regs) 1999f2699491SMichael Ellerman { 2000f2699491SMichael Ellerman u64 period = event->hw.sample_period; 2001f2699491SMichael Ellerman s64 prev, delta, left; 2002f2699491SMichael Ellerman int record = 0; 2003f2699491SMichael Ellerman 2004f2699491SMichael Ellerman if (event->hw.state & PERF_HES_STOPPED) { 2005f2699491SMichael Ellerman write_pmc(event->hw.idx, 0); 2006f2699491SMichael Ellerman return; 2007f2699491SMichael Ellerman } 2008f2699491SMichael Ellerman 2009f2699491SMichael Ellerman /* we don't have to worry about interrupts here */ 2010f2699491SMichael Ellerman prev = local64_read(&event->hw.prev_count); 2011f2699491SMichael Ellerman delta = check_and_compute_delta(prev, val); 2012f2699491SMichael Ellerman local64_add(delta, &event->count); 2013f2699491SMichael Ellerman 2014f2699491SMichael Ellerman /* 2015f2699491SMichael Ellerman * See if the total period for this event has expired, 2016f2699491SMichael Ellerman * and update for the next period. 2017f2699491SMichael Ellerman */ 2018f2699491SMichael Ellerman val = 0; 2019f2699491SMichael Ellerman left = local64_read(&event->hw.period_left) - delta; 2020e13e895fSMichael Neuling if (delta == 0) 2021e13e895fSMichael Neuling left++; 2022f2699491SMichael Ellerman if (period) { 2023f2699491SMichael Ellerman if (left <= 0) { 2024f2699491SMichael Ellerman left += period; 2025f2699491SMichael Ellerman if (left <= 0) 2026f2699491SMichael Ellerman left = period; 2027e6878835Ssukadev@linux.vnet.ibm.com record = siar_valid(regs); 2028f2699491SMichael Ellerman event->hw.last_period = event->hw.sample_period; 2029f2699491SMichael Ellerman } 2030f2699491SMichael Ellerman if (left < 0x80000000LL) 2031f2699491SMichael Ellerman val = 0x80000000LL - left; 2032f2699491SMichael Ellerman } 2033f2699491SMichael Ellerman 2034f2699491SMichael Ellerman write_pmc(event->hw.idx, val); 2035f2699491SMichael Ellerman local64_set(&event->hw.prev_count, val); 2036f2699491SMichael Ellerman local64_set(&event->hw.period_left, left); 2037f2699491SMichael Ellerman perf_event_update_userpage(event); 2038f2699491SMichael Ellerman 2039f2699491SMichael Ellerman /* 2040f2699491SMichael Ellerman * Finally record data if requested. 2041f2699491SMichael Ellerman */ 2042f2699491SMichael Ellerman if (record) { 2043f2699491SMichael Ellerman struct perf_sample_data data; 2044f2699491SMichael Ellerman 2045fd0d000bSRobert Richter perf_sample_data_init(&data, ~0ULL, event->hw.last_period); 2046f2699491SMichael Ellerman 2047fc7ce9c7SKan Liang if (event->attr.sample_type & 2048fc7ce9c7SKan Liang (PERF_SAMPLE_ADDR | PERF_SAMPLE_PHYS_ADDR)) 2049f2699491SMichael Ellerman perf_get_data_addr(regs, &data.addr); 2050f2699491SMichael Ellerman 20513925f46bSAnshuman Khandual if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) { 20523925f46bSAnshuman Khandual struct cpu_hw_events *cpuhw; 205369111bacSChristoph Lameter cpuhw = this_cpu_ptr(&cpu_hw_events); 20543925f46bSAnshuman Khandual power_pmu_bhrb_read(cpuhw); 20553925f46bSAnshuman Khandual data.br_stack = &cpuhw->bhrb_stack; 20563925f46bSAnshuman Khandual } 20573925f46bSAnshuman Khandual 205879e96f8fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && 205979e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src) 206079e96f8fSMadhavan Srinivasan ppmu->get_mem_data_src(&data.data_src, ppmu->flags, regs); 206179e96f8fSMadhavan Srinivasan 2062170a315fSMadhavan Srinivasan if (event->attr.sample_type & PERF_SAMPLE_WEIGHT && 2063170a315fSMadhavan Srinivasan ppmu->get_mem_weight) 2064170a315fSMadhavan Srinivasan ppmu->get_mem_weight(&data.weight); 2065170a315fSMadhavan Srinivasan 2066f2699491SMichael Ellerman if (perf_event_overflow(event, &data, regs)) 2067f2699491SMichael Ellerman power_pmu_stop(event, 0); 2068f2699491SMichael Ellerman } 2069f2699491SMichael Ellerman } 2070f2699491SMichael Ellerman 2071f2699491SMichael Ellerman /* 2072f2699491SMichael Ellerman * Called from generic code to get the misc flags (i.e. processor mode) 2073f2699491SMichael Ellerman * for an event_id. 2074f2699491SMichael Ellerman */ 2075f2699491SMichael Ellerman unsigned long perf_misc_flags(struct pt_regs *regs) 2076f2699491SMichael Ellerman { 2077f2699491SMichael Ellerman u32 flags = perf_get_misc_flags(regs); 2078f2699491SMichael Ellerman 2079f2699491SMichael Ellerman if (flags) 2080f2699491SMichael Ellerman return flags; 2081f2699491SMichael Ellerman return user_mode(regs) ? PERF_RECORD_MISC_USER : 2082f2699491SMichael Ellerman PERF_RECORD_MISC_KERNEL; 2083f2699491SMichael Ellerman } 2084f2699491SMichael Ellerman 2085f2699491SMichael Ellerman /* 2086f2699491SMichael Ellerman * Called from generic code to get the instruction pointer 2087f2699491SMichael Ellerman * for an event_id. 2088f2699491SMichael Ellerman */ 2089f2699491SMichael Ellerman unsigned long perf_instruction_pointer(struct pt_regs *regs) 2090f2699491SMichael Ellerman { 209133904054SMichael Ellerman bool use_siar = regs_use_siar(regs); 2092f2699491SMichael Ellerman 2093e6878835Ssukadev@linux.vnet.ibm.com if (use_siar && siar_valid(regs)) 20941ce447b9SBenjamin Herrenschmidt return mfspr(SPRN_SIAR) + perf_ip_adjust(regs); 2095e6878835Ssukadev@linux.vnet.ibm.com else if (use_siar) 2096e6878835Ssukadev@linux.vnet.ibm.com return 0; // no valid instruction pointer 209775382aa7SAnton Blanchard else 209875382aa7SAnton Blanchard return regs->nip; 2099f2699491SMichael Ellerman } 2100f2699491SMichael Ellerman 2101bc09c219SMichael Neuling static bool pmc_overflow_power7(unsigned long val) 2102f2699491SMichael Ellerman { 2103f2699491SMichael Ellerman /* 2104f2699491SMichael Ellerman * Events on POWER7 can roll back if a speculative event doesn't 2105f2699491SMichael Ellerman * eventually complete. Unfortunately in some rare cases they will 2106f2699491SMichael Ellerman * raise a performance monitor exception. We need to catch this to 2107f2699491SMichael Ellerman * ensure we reset the PMC. In all cases the PMC will be 256 or less 2108f2699491SMichael Ellerman * cycles from overflow. 2109f2699491SMichael Ellerman * 2110f2699491SMichael Ellerman * We only do this if the first pass fails to find any overflowing 2111f2699491SMichael Ellerman * PMCs because a user might set a period of less than 256 and we 2112f2699491SMichael Ellerman * don't want to mistakenly reset them. 2113f2699491SMichael Ellerman */ 2114bc09c219SMichael Neuling if ((0x80000000 - val) <= 256) 2115bc09c219SMichael Neuling return true; 2116bc09c219SMichael Neuling 2117bc09c219SMichael Neuling return false; 2118bc09c219SMichael Neuling } 2119bc09c219SMichael Neuling 2120bc09c219SMichael Neuling static bool pmc_overflow(unsigned long val) 2121bc09c219SMichael Neuling { 2122bc09c219SMichael Neuling if ((int)val < 0) 2123f2699491SMichael Ellerman return true; 2124f2699491SMichael Ellerman 2125f2699491SMichael Ellerman return false; 2126f2699491SMichael Ellerman } 2127f2699491SMichael Ellerman 2128f2699491SMichael Ellerman /* 2129f2699491SMichael Ellerman * Performance monitor interrupt stuff 2130f2699491SMichael Ellerman */ 2131f2699491SMichael Ellerman static void perf_event_interrupt(struct pt_regs *regs) 2132f2699491SMichael Ellerman { 2133bc09c219SMichael Neuling int i, j; 213469111bacSChristoph Lameter struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events); 2135f2699491SMichael Ellerman struct perf_event *event; 2136bc09c219SMichael Neuling unsigned long val[8]; 2137bc09c219SMichael Neuling int found, active; 2138f2699491SMichael Ellerman int nmi; 2139f2699491SMichael Ellerman 2140f2699491SMichael Ellerman if (cpuhw->n_limited) 2141f2699491SMichael Ellerman freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5), 2142f2699491SMichael Ellerman mfspr(SPRN_PMC6)); 2143f2699491SMichael Ellerman 2144f2699491SMichael Ellerman perf_read_regs(regs); 2145f2699491SMichael Ellerman 2146f2699491SMichael Ellerman nmi = perf_intr_is_nmi(regs); 2147f2699491SMichael Ellerman if (nmi) 2148f2699491SMichael Ellerman nmi_enter(); 2149f2699491SMichael Ellerman else 2150f2699491SMichael Ellerman irq_enter(); 2151f2699491SMichael Ellerman 2152bc09c219SMichael Neuling /* Read all the PMCs since we'll need them a bunch of times */ 2153bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) 2154bc09c219SMichael Neuling val[i] = read_pmc(i + 1); 2155bc09c219SMichael Neuling 2156bc09c219SMichael Neuling /* Try to find what caused the IRQ */ 2157bc09c219SMichael Neuling found = 0; 2158bc09c219SMichael Neuling for (i = 0; i < ppmu->n_counter; ++i) { 2159bc09c219SMichael Neuling if (!pmc_overflow(val[i])) 2160bc09c219SMichael Neuling continue; 2161bc09c219SMichael Neuling if (is_limited_pmc(i + 1)) 2162bc09c219SMichael Neuling continue; /* these won't generate IRQs */ 2163bc09c219SMichael Neuling /* 2164bc09c219SMichael Neuling * We've found one that's overflowed. For active 2165bc09c219SMichael Neuling * counters we need to log this. For inactive 2166bc09c219SMichael Neuling * counters, we need to reset it anyway 2167bc09c219SMichael Neuling */ 2168bc09c219SMichael Neuling found = 1; 2169bc09c219SMichael Neuling active = 0; 2170bc09c219SMichael Neuling for (j = 0; j < cpuhw->n_events; ++j) { 2171bc09c219SMichael Neuling event = cpuhw->event[j]; 2172bc09c219SMichael Neuling if (event->hw.idx == (i + 1)) { 2173bc09c219SMichael Neuling active = 1; 2174bc09c219SMichael Neuling record_and_restart(event, val[i], regs); 2175bc09c219SMichael Neuling break; 2176bc09c219SMichael Neuling } 2177bc09c219SMichael Neuling } 2178bc09c219SMichael Neuling if (!active) 2179bc09c219SMichael Neuling /* reset non active counters that have overflowed */ 2180bc09c219SMichael Neuling write_pmc(i + 1, 0); 2181bc09c219SMichael Neuling } 2182bc09c219SMichael Neuling if (!found && pvr_version_is(PVR_POWER7)) { 2183bc09c219SMichael Neuling /* check active counters for special buggy p7 overflow */ 2184f2699491SMichael Ellerman for (i = 0; i < cpuhw->n_events; ++i) { 2185f2699491SMichael Ellerman event = cpuhw->event[i]; 2186f2699491SMichael Ellerman if (!event->hw.idx || is_limited_pmc(event->hw.idx)) 2187f2699491SMichael Ellerman continue; 2188bc09c219SMichael Neuling if (pmc_overflow_power7(val[event->hw.idx - 1])) { 2189bc09c219SMichael Neuling /* event has overflowed in a buggy way*/ 2190f2699491SMichael Ellerman found = 1; 2191bc09c219SMichael Neuling record_and_restart(event, 2192bc09c219SMichael Neuling val[event->hw.idx - 1], 2193bc09c219SMichael Neuling regs); 2194f2699491SMichael Ellerman } 2195f2699491SMichael Ellerman } 2196f2699491SMichael Ellerman } 21976772faa1SMichael Ellerman if (!found && !nmi && printk_ratelimit()) 2198bc09c219SMichael Neuling printk(KERN_WARNING "Can't find PMC that caused IRQ\n"); 2199f2699491SMichael Ellerman 2200f2699491SMichael Ellerman /* 2201f2699491SMichael Ellerman * Reset MMCR0 to its normal value. This will set PMXE and 2202f2699491SMichael Ellerman * clear FC (freeze counters) and PMAO (perf mon alert occurred) 2203f2699491SMichael Ellerman * and thus allow interrupts to occur again. 2204f2699491SMichael Ellerman * XXX might want to use MSR.PM to keep the events frozen until 2205f2699491SMichael Ellerman * we get back out of this interrupt. 2206f2699491SMichael Ellerman */ 2207f2699491SMichael Ellerman write_mmcr0(cpuhw, cpuhw->mmcr[0]); 2208f2699491SMichael Ellerman 2209f2699491SMichael Ellerman if (nmi) 2210f2699491SMichael Ellerman nmi_exit(); 2211f2699491SMichael Ellerman else 2212f2699491SMichael Ellerman irq_exit(); 2213f2699491SMichael Ellerman } 2214f2699491SMichael Ellerman 22157c98bd72SDaniel Axtens static int power_pmu_prepare_cpu(unsigned int cpu) 2216f2699491SMichael Ellerman { 2217f2699491SMichael Ellerman struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu); 2218f2699491SMichael Ellerman 221957ecde42SThomas Gleixner if (ppmu) { 2220f2699491SMichael Ellerman memset(cpuhw, 0, sizeof(*cpuhw)); 2221f2699491SMichael Ellerman cpuhw->mmcr[0] = MMCR0_FC; 2222f2699491SMichael Ellerman } 222357ecde42SThomas Gleixner return 0; 2224f2699491SMichael Ellerman } 2225f2699491SMichael Ellerman 2226061d19f2SPaul Gortmaker int register_power_pmu(struct power_pmu *pmu) 2227f2699491SMichael Ellerman { 2228f2699491SMichael Ellerman if (ppmu) 2229f2699491SMichael Ellerman return -EBUSY; /* something's already registered */ 2230f2699491SMichael Ellerman 2231f2699491SMichael Ellerman ppmu = pmu; 2232f2699491SMichael Ellerman pr_info("%s performance monitor hardware support registered\n", 2233f2699491SMichael Ellerman pmu->name); 2234f2699491SMichael Ellerman 22351c53a270SSukadev Bhattiprolu power_pmu.attr_groups = ppmu->attr_groups; 22361c53a270SSukadev Bhattiprolu 2237f2699491SMichael Ellerman #ifdef MSR_HV 2238f2699491SMichael Ellerman /* 2239f2699491SMichael Ellerman * Use FCHV to ignore kernel events if MSR.HV is set. 2240f2699491SMichael Ellerman */ 2241f2699491SMichael Ellerman if (mfmsr() & MSR_HV) 2242f2699491SMichael Ellerman freeze_events_kernel = MMCR0_FCHV; 2243f2699491SMichael Ellerman #endif /* CONFIG_PPC64 */ 2244f2699491SMichael Ellerman 2245f2699491SMichael Ellerman perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW); 224673c1b41eSThomas Gleixner cpuhp_setup_state(CPUHP_PERF_POWER, "perf/powerpc:prepare", 224757ecde42SThomas Gleixner power_pmu_prepare_cpu, NULL); 2248f2699491SMichael Ellerman return 0; 2249f2699491SMichael Ellerman } 2250