1 /* bpf_jit.h: BPF JIT compiler for PPC64 2 * 3 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; version 2 8 * of the License. 9 */ 10 #ifndef _BPF_JIT_H 11 #define _BPF_JIT_H 12 13 #define BPF_PPC_STACK_LOCALS 32 14 #define BPF_PPC_STACK_BASIC (48+64) 15 #define BPF_PPC_STACK_SAVE (18*8) 16 #define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \ 17 BPF_PPC_STACK_SAVE) 18 #define BPF_PPC_SLOWPATH_FRAME (48+64) 19 20 /* 21 * Generated code register usage: 22 * 23 * As normal PPC C ABI (e.g. r1=sp, r2=TOC), with: 24 * 25 * skb r3 (Entry parameter) 26 * A register r4 27 * X register r5 28 * addr param r6 29 * r7-r10 scratch 30 * skb->data r14 31 * skb headlen r15 (skb->len - skb->data_len) 32 * m[0] r16 33 * m[...] ... 34 * m[15] r31 35 */ 36 #define r_skb 3 37 #define r_ret 3 38 #define r_A 4 39 #define r_X 5 40 #define r_addr 6 41 #define r_scratch1 7 42 #define r_scratch2 8 43 #define r_D 14 44 #define r_HL 15 45 #define r_M 16 46 47 #ifndef __ASSEMBLY__ 48 49 /* 50 * Assembly helpers from arch/powerpc/net/bpf_jit.S: 51 */ 52 #define DECLARE_LOAD_FUNC(func) \ 53 extern u8 func[], func##_negative_offset[], func##_positive_offset[] 54 55 DECLARE_LOAD_FUNC(sk_load_word); 56 DECLARE_LOAD_FUNC(sk_load_half); 57 DECLARE_LOAD_FUNC(sk_load_byte); 58 DECLARE_LOAD_FUNC(sk_load_byte_msh); 59 60 #define FUNCTION_DESCR_SIZE 24 61 62 /* 63 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs 64 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the 65 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000). 66 */ 67 #define IMM_H(i) ((uintptr_t)(i)>>16) 68 #define IMM_HA(i) (((uintptr_t)(i)>>16) + \ 69 (((uintptr_t)(i) & 0x8000) >> 15)) 70 #define IMM_L(i) ((uintptr_t)(i) & 0xffff) 71 72 #define PLANT_INSTR(d, idx, instr) \ 73 do { if (d) { (d)[idx] = instr; } idx++; } while (0) 74 #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr) 75 76 #define PPC_NOP() EMIT(PPC_INST_NOP) 77 #define PPC_BLR() EMIT(PPC_INST_BLR) 78 #define PPC_BLRL() EMIT(PPC_INST_BLRL) 79 #define PPC_MTLR(r) EMIT(PPC_INST_MTLR | ___PPC_RT(r)) 80 #define PPC_ADDI(d, a, i) EMIT(PPC_INST_ADDI | ___PPC_RT(d) | \ 81 ___PPC_RA(a) | IMM_L(i)) 82 #define PPC_MR(d, a) PPC_OR(d, a, a) 83 #define PPC_LI(r, i) PPC_ADDI(r, 0, i) 84 #define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \ 85 ___PPC_RS(d) | ___PPC_RA(a) | IMM_L(i)) 86 #define PPC_LIS(r, i) PPC_ADDIS(r, 0, i) 87 #define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \ 88 ___PPC_RA(base) | ((i) & 0xfffc)) 89 90 91 #define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ | ___PPC_RT(r) | \ 92 ___PPC_RA(base) | IMM_L(i)) 93 #define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \ 94 ___PPC_RA(base) | IMM_L(i)) 95 #define PPC_LWZ(r, base, i) EMIT(PPC_INST_LWZ | ___PPC_RT(r) | \ 96 ___PPC_RA(base) | IMM_L(i)) 97 #define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \ 98 ___PPC_RA(base) | IMM_L(i)) 99 #define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \ 100 ___PPC_RA(base) | ___PPC_RB(b)) 101 /* Convenience helpers for the above with 'far' offsets: */ 102 #define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i); \ 103 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 104 PPC_LBZ(r, r, IMM_L(i)); } } while(0) 105 106 #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \ 107 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 108 PPC_LD(r, r, IMM_L(i)); } } while(0) 109 110 #define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \ 111 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 112 PPC_LWZ(r, r, IMM_L(i)); } } while(0) 113 114 #define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \ 115 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 116 PPC_LHZ(r, r, IMM_L(i)); } } while(0) 117 118 #define PPC_CMPWI(a, i) EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i)) 119 #define PPC_CMPDI(a, i) EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i)) 120 #define PPC_CMPLWI(a, i) EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i)) 121 #define PPC_CMPLW(a, b) EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | ___PPC_RB(b)) 122 123 #define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) | \ 124 ___PPC_RB(a) | ___PPC_RA(b)) 125 #define PPC_ADD(d, a, b) EMIT(PPC_INST_ADD | ___PPC_RT(d) | \ 126 ___PPC_RA(a) | ___PPC_RB(b)) 127 #define PPC_MUL(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \ 128 ___PPC_RA(a) | ___PPC_RB(b)) 129 #define PPC_MULHWU(d, a, b) EMIT(PPC_INST_MULHWU | ___PPC_RT(d) | \ 130 ___PPC_RA(a) | ___PPC_RB(b)) 131 #define PPC_MULI(d, a, i) EMIT(PPC_INST_MULLI | ___PPC_RT(d) | \ 132 ___PPC_RA(a) | IMM_L(i)) 133 #define PPC_DIVWU(d, a, b) EMIT(PPC_INST_DIVWU | ___PPC_RT(d) | \ 134 ___PPC_RA(a) | ___PPC_RB(b)) 135 #define PPC_AND(d, a, b) EMIT(PPC_INST_AND | ___PPC_RA(d) | \ 136 ___PPC_RS(a) | ___PPC_RB(b)) 137 #define PPC_ANDI(d, a, i) EMIT(PPC_INST_ANDI | ___PPC_RA(d) | \ 138 ___PPC_RS(a) | IMM_L(i)) 139 #define PPC_AND_DOT(d, a, b) EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) | \ 140 ___PPC_RS(a) | ___PPC_RB(b)) 141 #define PPC_OR(d, a, b) EMIT(PPC_INST_OR | ___PPC_RA(d) | \ 142 ___PPC_RS(a) | ___PPC_RB(b)) 143 #define PPC_ORI(d, a, i) EMIT(PPC_INST_ORI | ___PPC_RA(d) | \ 144 ___PPC_RS(a) | IMM_L(i)) 145 #define PPC_ORIS(d, a, i) EMIT(PPC_INST_ORIS | ___PPC_RA(d) | \ 146 ___PPC_RS(a) | IMM_L(i)) 147 #define PPC_XOR(d, a, b) EMIT(PPC_INST_XOR | ___PPC_RA(d) | \ 148 ___PPC_RS(a) | ___PPC_RB(b)) 149 #define PPC_XORI(d, a, i) EMIT(PPC_INST_XORI | ___PPC_RA(d) | \ 150 ___PPC_RS(a) | IMM_L(i)) 151 #define PPC_XORIS(d, a, i) EMIT(PPC_INST_XORIS | ___PPC_RA(d) | \ 152 ___PPC_RS(a) | IMM_L(i)) 153 #define PPC_SLW(d, a, s) EMIT(PPC_INST_SLW | ___PPC_RA(d) | \ 154 ___PPC_RS(a) | ___PPC_RB(s)) 155 #define PPC_SRW(d, a, s) EMIT(PPC_INST_SRW | ___PPC_RA(d) | \ 156 ___PPC_RS(a) | ___PPC_RB(s)) 157 /* slwi = rlwinm Rx, Ry, n, 0, 31-n */ 158 #define PPC_SLWI(d, a, i) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \ 159 ___PPC_RS(a) | __PPC_SH(i) | \ 160 __PPC_MB(0) | __PPC_ME(31-(i))) 161 /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */ 162 #define PPC_SRWI(d, a, i) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \ 163 ___PPC_RS(a) | __PPC_SH(32-(i)) | \ 164 __PPC_MB(i) | __PPC_ME(31)) 165 /* sldi = rldicr Rx, Ry, n, 63-n */ 166 #define PPC_SLDI(d, a, i) EMIT(PPC_INST_RLDICR | ___PPC_RA(d) | \ 167 ___PPC_RS(a) | __PPC_SH(i) | \ 168 __PPC_MB(63-(i)) | (((i) & 0x20) >> 4)) 169 #define PPC_NEG(d, a) EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a)) 170 171 /* Long jump; (unconditional 'branch') */ 172 #define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \ 173 (((dest) - (ctx->idx * 4)) & 0x03fffffc)) 174 /* "cond" here covers BO:BI fields. */ 175 #define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \ 176 (((cond) & 0x3ff) << 16) | \ 177 (((dest) - (ctx->idx * 4)) & \ 178 0xfffc)) 179 #define PPC_LI32(d, i) do { PPC_LI(d, IMM_L(i)); \ 180 if ((u32)(uintptr_t)(i) >= 32768) { \ 181 PPC_ADDIS(d, d, IMM_HA(i)); \ 182 } } while(0) 183 #define PPC_LI64(d, i) do { \ 184 if (!((uintptr_t)(i) & 0xffffffff00000000ULL)) \ 185 PPC_LI32(d, i); \ 186 else { \ 187 PPC_LIS(d, ((uintptr_t)(i) >> 48)); \ 188 if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \ 189 PPC_ORI(d, d, \ 190 ((uintptr_t)(i) >> 32) & 0xffff); \ 191 PPC_SLDI(d, d, 32); \ 192 if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \ 193 PPC_ORIS(d, d, \ 194 ((uintptr_t)(i) >> 16) & 0xffff); \ 195 if ((uintptr_t)(i) & 0x000000000000ffffULL) \ 196 PPC_ORI(d, d, (uintptr_t)(i) & 0xffff); \ 197 } } while (0); 198 199 #define PPC_LHBRX_OFFS(r, base, i) \ 200 do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0) 201 #ifdef __LITTLE_ENDIAN__ 202 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i) 203 #else 204 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i) 205 #endif 206 207 static inline bool is_nearbranch(int offset) 208 { 209 return (offset < 32768) && (offset >= -32768); 210 } 211 212 /* 213 * The fly in the ointment of code size changing from pass to pass is 214 * avoided by padding the short branch case with a NOP. If code size differs 215 * with different branch reaches we will have the issue of code moving from 216 * one pass to the next and will need a few passes to converge on a stable 217 * state. 218 */ 219 #define PPC_BCC(cond, dest) do { \ 220 if (is_nearbranch((dest) - (ctx->idx * 4))) { \ 221 PPC_BCC_SHORT(cond, dest); \ 222 PPC_NOP(); \ 223 } else { \ 224 /* Flip the 'T or F' bit to invert comparison */ \ 225 PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \ 226 PPC_JMP(dest); \ 227 } } while(0) 228 229 /* To create a branch condition, select a bit of cr0... */ 230 #define CR0_LT 0 231 #define CR0_GT 1 232 #define CR0_EQ 2 233 /* ...and modify BO[3] */ 234 #define COND_CMP_TRUE 0x100 235 #define COND_CMP_FALSE 0x000 236 /* Together, they make all required comparisons: */ 237 #define COND_GT (CR0_GT | COND_CMP_TRUE) 238 #define COND_GE (CR0_LT | COND_CMP_FALSE) 239 #define COND_EQ (CR0_EQ | COND_CMP_TRUE) 240 #define COND_NE (CR0_EQ | COND_CMP_FALSE) 241 #define COND_LT (CR0_LT | COND_CMP_TRUE) 242 243 #define SEEN_DATAREF 0x10000 /* might call external helpers */ 244 #define SEEN_XREG 0x20000 /* X reg is used */ 245 #define SEEN_MEM 0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary 246 * storage */ 247 #define SEEN_MEM_MSK 0x0ffff 248 249 struct codegen_context { 250 unsigned int seen; 251 unsigned int idx; 252 int pc_ret0; /* bpf index of first RET #0 instruction (if any) */ 253 }; 254 255 #endif 256 257 #endif 258