1 /* bpf_jit.h: BPF JIT compiler for PPC64 2 * 3 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; version 2 8 * of the License. 9 */ 10 #ifndef _BPF_JIT_H 11 #define _BPF_JIT_H 12 13 #ifdef CONFIG_PPC64 14 #define BPF_PPC_STACK_R3_OFF 48 15 #define BPF_PPC_STACK_LOCALS 32 16 #define BPF_PPC_STACK_BASIC (48+64) 17 #define BPF_PPC_STACK_SAVE (18*8) 18 #define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \ 19 BPF_PPC_STACK_SAVE) 20 #define BPF_PPC_SLOWPATH_FRAME (48+64) 21 #else 22 #define BPF_PPC_STACK_R3_OFF 24 23 #define BPF_PPC_STACK_LOCALS 16 24 #define BPF_PPC_STACK_BASIC (24+32) 25 #define BPF_PPC_STACK_SAVE (18*4) 26 #define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \ 27 BPF_PPC_STACK_SAVE) 28 #define BPF_PPC_SLOWPATH_FRAME (24+32) 29 #endif 30 31 #define REG_SZ (BITS_PER_LONG/8) 32 33 /* 34 * Generated code register usage: 35 * 36 * As normal PPC C ABI (e.g. r1=sp, r2=TOC), with: 37 * 38 * skb r3 (Entry parameter) 39 * A register r4 40 * X register r5 41 * addr param r6 42 * r7-r10 scratch 43 * skb->data r14 44 * skb headlen r15 (skb->len - skb->data_len) 45 * m[0] r16 46 * m[...] ... 47 * m[15] r31 48 */ 49 #define r_skb 3 50 #define r_ret 3 51 #define r_A 4 52 #define r_X 5 53 #define r_addr 6 54 #define r_scratch1 7 55 #define r_scratch2 8 56 #define r_D 14 57 #define r_HL 15 58 #define r_M 16 59 60 #ifndef __ASSEMBLY__ 61 62 /* 63 * Assembly helpers from arch/powerpc/net/bpf_jit.S: 64 */ 65 #define DECLARE_LOAD_FUNC(func) \ 66 extern u8 func[], func##_negative_offset[], func##_positive_offset[] 67 68 DECLARE_LOAD_FUNC(sk_load_word); 69 DECLARE_LOAD_FUNC(sk_load_half); 70 DECLARE_LOAD_FUNC(sk_load_byte); 71 DECLARE_LOAD_FUNC(sk_load_byte_msh); 72 73 #ifdef CONFIG_PPC64 74 #define FUNCTION_DESCR_SIZE 24 75 #else 76 #define FUNCTION_DESCR_SIZE 0 77 #endif 78 79 /* 80 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs 81 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the 82 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000). 83 */ 84 #define IMM_H(i) ((uintptr_t)(i)>>16) 85 #define IMM_HA(i) (((uintptr_t)(i)>>16) + \ 86 (((uintptr_t)(i) & 0x8000) >> 15)) 87 #define IMM_L(i) ((uintptr_t)(i) & 0xffff) 88 89 #define PLANT_INSTR(d, idx, instr) \ 90 do { if (d) { (d)[idx] = instr; } idx++; } while (0) 91 #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr) 92 93 #define PPC_NOP() EMIT(PPC_INST_NOP) 94 #define PPC_BLR() EMIT(PPC_INST_BLR) 95 #define PPC_BLRL() EMIT(PPC_INST_BLRL) 96 #define PPC_MTLR(r) EMIT(PPC_INST_MTLR | ___PPC_RT(r)) 97 #define PPC_ADDI(d, a, i) EMIT(PPC_INST_ADDI | ___PPC_RT(d) | \ 98 ___PPC_RA(a) | IMM_L(i)) 99 #define PPC_MR(d, a) PPC_OR(d, a, a) 100 #define PPC_LI(r, i) PPC_ADDI(r, 0, i) 101 #define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \ 102 ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) 103 #define PPC_LIS(r, i) PPC_ADDIS(r, 0, i) 104 #define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \ 105 ___PPC_RA(base) | ((i) & 0xfffc)) 106 #define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \ 107 ___PPC_RA(base) | ((i) & 0xfffc)) 108 #define PPC_STW(r, base, i) EMIT(PPC_INST_STW | ___PPC_RS(r) | \ 109 ___PPC_RA(base) | IMM_L(i)) 110 #define PPC_STWU(r, base, i) EMIT(PPC_INST_STWU | ___PPC_RS(r) | \ 111 ___PPC_RA(base) | IMM_L(i)) 112 113 #define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ | ___PPC_RT(r) | \ 114 ___PPC_RA(base) | IMM_L(i)) 115 #define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \ 116 ___PPC_RA(base) | IMM_L(i)) 117 #define PPC_LWZ(r, base, i) EMIT(PPC_INST_LWZ | ___PPC_RT(r) | \ 118 ___PPC_RA(base) | IMM_L(i)) 119 #define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \ 120 ___PPC_RA(base) | IMM_L(i)) 121 #define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \ 122 ___PPC_RA(base) | ___PPC_RB(b)) 123 124 #ifdef CONFIG_PPC64 125 #define PPC_BPF_LL(r, base, i) do { PPC_LD(r, base, i); } while(0) 126 #define PPC_BPF_STL(r, base, i) do { PPC_STD(r, base, i); } while(0) 127 #define PPC_BPF_STLU(r, base, i) do { PPC_STDU(r, base, i); } while(0) 128 #else 129 #define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0) 130 #define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0) 131 #define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0) 132 #endif 133 134 /* Convenience helpers for the above with 'far' offsets: */ 135 #define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LBZ(r, base, i); \ 136 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 137 PPC_LBZ(r, r, IMM_L(i)); } } while(0) 138 139 #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) PPC_LD(r, base, i); \ 140 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 141 PPC_LD(r, r, IMM_L(i)); } } while(0) 142 143 #define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LWZ(r, base, i); \ 144 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 145 PPC_LWZ(r, r, IMM_L(i)); } } while(0) 146 147 #define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) PPC_LHZ(r, base, i); \ 148 else { PPC_ADDIS(r, base, IMM_HA(i)); \ 149 PPC_LHZ(r, r, IMM_L(i)); } } while(0) 150 151 #ifdef CONFIG_PPC64 152 #define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0) 153 #else 154 #define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0) 155 #endif 156 157 #ifdef CONFIG_SMP 158 #ifdef CONFIG_PPC64 159 #define PPC_BPF_LOAD_CPU(r) \ 160 do { BUILD_BUG_ON(FIELD_SIZEOF(struct paca_struct, paca_index) != 2); \ 161 PPC_LHZ_OFFS(r, 13, offsetof(struct paca_struct, paca_index)); \ 162 } while (0) 163 #else 164 #define PPC_BPF_LOAD_CPU(r) \ 165 do { BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, cpu) != 4); \ 166 PPC_LHZ_OFFS(r, (1 & ~(THREAD_SIZE - 1)), \ 167 offsetof(struct thread_info, cpu)); \ 168 } while(0) 169 #endif 170 #else 171 #define PPC_BPF_LOAD_CPU(r) do { PPC_LI(r, 0); } while(0) 172 #endif 173 174 #define PPC_CMPWI(a, i) EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i)) 175 #define PPC_CMPDI(a, i) EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i)) 176 #define PPC_CMPLWI(a, i) EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i)) 177 #define PPC_CMPLW(a, b) EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | \ 178 ___PPC_RB(b)) 179 180 #define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) | \ 181 ___PPC_RB(a) | ___PPC_RA(b)) 182 #define PPC_ADD(d, a, b) EMIT(PPC_INST_ADD | ___PPC_RT(d) | \ 183 ___PPC_RA(a) | ___PPC_RB(b)) 184 #define PPC_MULW(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \ 185 ___PPC_RA(a) | ___PPC_RB(b)) 186 #define PPC_MULHWU(d, a, b) EMIT(PPC_INST_MULHWU | ___PPC_RT(d) | \ 187 ___PPC_RA(a) | ___PPC_RB(b)) 188 #define PPC_MULI(d, a, i) EMIT(PPC_INST_MULLI | ___PPC_RT(d) | \ 189 ___PPC_RA(a) | IMM_L(i)) 190 #define PPC_DIVWU(d, a, b) EMIT(PPC_INST_DIVWU | ___PPC_RT(d) | \ 191 ___PPC_RA(a) | ___PPC_RB(b)) 192 #define PPC_AND(d, a, b) EMIT(PPC_INST_AND | ___PPC_RA(d) | \ 193 ___PPC_RS(a) | ___PPC_RB(b)) 194 #define PPC_ANDI(d, a, i) EMIT(PPC_INST_ANDI | ___PPC_RA(d) | \ 195 ___PPC_RS(a) | IMM_L(i)) 196 #define PPC_AND_DOT(d, a, b) EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) | \ 197 ___PPC_RS(a) | ___PPC_RB(b)) 198 #define PPC_OR(d, a, b) EMIT(PPC_INST_OR | ___PPC_RA(d) | \ 199 ___PPC_RS(a) | ___PPC_RB(b)) 200 #define PPC_ORI(d, a, i) EMIT(PPC_INST_ORI | ___PPC_RA(d) | \ 201 ___PPC_RS(a) | IMM_L(i)) 202 #define PPC_ORIS(d, a, i) EMIT(PPC_INST_ORIS | ___PPC_RA(d) | \ 203 ___PPC_RS(a) | IMM_L(i)) 204 #define PPC_XOR(d, a, b) EMIT(PPC_INST_XOR | ___PPC_RA(d) | \ 205 ___PPC_RS(a) | ___PPC_RB(b)) 206 #define PPC_XORI(d, a, i) EMIT(PPC_INST_XORI | ___PPC_RA(d) | \ 207 ___PPC_RS(a) | IMM_L(i)) 208 #define PPC_XORIS(d, a, i) EMIT(PPC_INST_XORIS | ___PPC_RA(d) | \ 209 ___PPC_RS(a) | IMM_L(i)) 210 #define PPC_SLW(d, a, s) EMIT(PPC_INST_SLW | ___PPC_RA(d) | \ 211 ___PPC_RS(a) | ___PPC_RB(s)) 212 #define PPC_SRW(d, a, s) EMIT(PPC_INST_SRW | ___PPC_RA(d) | \ 213 ___PPC_RS(a) | ___PPC_RB(s)) 214 #define PPC_RLWINM(d, a, i, mb, me) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \ 215 ___PPC_RS(a) | __PPC_SH(i) | \ 216 __PPC_MB(mb) | __PPC_ME(me)) 217 #define PPC_RLDICR(d, a, i, me) EMIT(PPC_INST_RLDICR | ___PPC_RA(d) | \ 218 ___PPC_RS(a) | __PPC_SH(i) | \ 219 __PPC_ME64(me) | (((i) & 0x20) >> 4)) 220 221 /* slwi = rlwinm Rx, Ry, n, 0, 31-n */ 222 #define PPC_SLWI(d, a, i) PPC_RLWINM(d, a, i, 0, 31-(i)) 223 /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */ 224 #define PPC_SRWI(d, a, i) PPC_RLWINM(d, a, 32-(i), i, 31) 225 /* sldi = rldicr Rx, Ry, n, 63-n */ 226 #define PPC_SLDI(d, a, i) PPC_RLDICR(d, a, i, 63-(i)) 227 228 #define PPC_NEG(d, a) EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a)) 229 230 /* Long jump; (unconditional 'branch') */ 231 #define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \ 232 (((dest) - (ctx->idx * 4)) & 0x03fffffc)) 233 /* "cond" here covers BO:BI fields. */ 234 #define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \ 235 (((cond) & 0x3ff) << 16) | \ 236 (((dest) - (ctx->idx * 4)) & \ 237 0xfffc)) 238 /* Sign-extended 32-bit immediate load */ 239 #define PPC_LI32(d, i) do { \ 240 if ((int)(uintptr_t)(i) >= -32768 && \ 241 (int)(uintptr_t)(i) < 32768) \ 242 PPC_LI(d, i); \ 243 else { \ 244 PPC_LIS(d, IMM_H(i)); \ 245 if (IMM_L(i)) \ 246 PPC_ORI(d, d, IMM_L(i)); \ 247 } } while(0) 248 249 #define PPC_LI64(d, i) do { \ 250 if ((long)(i) >= -2147483648 && \ 251 (long)(i) < 2147483648) \ 252 PPC_LI32(d, i); \ 253 else { \ 254 if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \ 255 PPC_LI(d, ((uintptr_t)(i) >> 32) & 0xffff); \ 256 else { \ 257 PPC_LIS(d, ((uintptr_t)(i) >> 48)); \ 258 if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \ 259 PPC_ORI(d, d, \ 260 ((uintptr_t)(i) >> 32) & 0xffff); \ 261 } \ 262 PPC_SLDI(d, d, 32); \ 263 if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \ 264 PPC_ORIS(d, d, \ 265 ((uintptr_t)(i) >> 16) & 0xffff); \ 266 if ((uintptr_t)(i) & 0x000000000000ffffULL) \ 267 PPC_ORI(d, d, (uintptr_t)(i) & 0xffff); \ 268 } } while (0) 269 270 #ifdef CONFIG_PPC64 271 #define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0) 272 #else 273 #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0) 274 #endif 275 276 #define PPC_LHBRX_OFFS(r, base, i) \ 277 do { PPC_LI32(r, i); PPC_LHBRX(r, r, base); } while(0) 278 #ifdef __LITTLE_ENDIAN__ 279 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i) 280 #else 281 #define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i) 282 #endif 283 284 static inline bool is_nearbranch(int offset) 285 { 286 return (offset < 32768) && (offset >= -32768); 287 } 288 289 /* 290 * The fly in the ointment of code size changing from pass to pass is 291 * avoided by padding the short branch case with a NOP. If code size differs 292 * with different branch reaches we will have the issue of code moving from 293 * one pass to the next and will need a few passes to converge on a stable 294 * state. 295 */ 296 #define PPC_BCC(cond, dest) do { \ 297 if (is_nearbranch((dest) - (ctx->idx * 4))) { \ 298 PPC_BCC_SHORT(cond, dest); \ 299 PPC_NOP(); \ 300 } else { \ 301 /* Flip the 'T or F' bit to invert comparison */ \ 302 PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \ 303 PPC_JMP(dest); \ 304 } } while(0) 305 306 /* To create a branch condition, select a bit of cr0... */ 307 #define CR0_LT 0 308 #define CR0_GT 1 309 #define CR0_EQ 2 310 /* ...and modify BO[3] */ 311 #define COND_CMP_TRUE 0x100 312 #define COND_CMP_FALSE 0x000 313 /* Together, they make all required comparisons: */ 314 #define COND_GT (CR0_GT | COND_CMP_TRUE) 315 #define COND_GE (CR0_LT | COND_CMP_FALSE) 316 #define COND_EQ (CR0_EQ | COND_CMP_TRUE) 317 #define COND_NE (CR0_EQ | COND_CMP_FALSE) 318 #define COND_LT (CR0_LT | COND_CMP_TRUE) 319 320 #define SEEN_DATAREF 0x10000 /* might call external helpers */ 321 #define SEEN_XREG 0x20000 /* X reg is used */ 322 #define SEEN_MEM 0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary 323 * storage */ 324 #define SEEN_MEM_MSK 0x0ffff 325 326 struct codegen_context { 327 unsigned int seen; 328 unsigned int idx; 329 int pc_ret0; /* bpf index of first RET #0 instruction (if any) */ 330 }; 331 332 #endif 333 334 #endif 335