1 /* 2 * bpf_jit.h: BPF JIT compiler for PPC 3 * 4 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; version 2 9 * of the License. 10 */ 11 #ifndef _BPF_JIT_H 12 #define _BPF_JIT_H 13 14 #ifndef __ASSEMBLY__ 15 16 #ifdef CONFIG_PPC64 17 #define FUNCTION_DESCR_SIZE 24 18 #else 19 #define FUNCTION_DESCR_SIZE 0 20 #endif 21 22 /* 23 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs 24 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the 25 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000). 26 */ 27 #define IMM_H(i) ((uintptr_t)(i)>>16) 28 #define IMM_HA(i) (((uintptr_t)(i)>>16) + \ 29 (((uintptr_t)(i) & 0x8000) >> 15)) 30 #define IMM_L(i) ((uintptr_t)(i) & 0xffff) 31 32 #define PLANT_INSTR(d, idx, instr) \ 33 do { if (d) { (d)[idx] = instr; } idx++; } while (0) 34 #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr) 35 36 #define PPC_NOP() EMIT(PPC_INST_NOP) 37 #define PPC_BLR() EMIT(PPC_INST_BLR) 38 #define PPC_BLRL() EMIT(PPC_INST_BLRL) 39 #define PPC_MTLR(r) EMIT(PPC_INST_MTLR | ___PPC_RT(r)) 40 #define PPC_ADDI(d, a, i) EMIT(PPC_INST_ADDI | ___PPC_RT(d) | \ 41 ___PPC_RA(a) | IMM_L(i)) 42 #define PPC_MR(d, a) PPC_OR(d, a, a) 43 #define PPC_LI(r, i) PPC_ADDI(r, 0, i) 44 #define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \ 45 ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) 46 #define PPC_LIS(r, i) PPC_ADDIS(r, 0, i) 47 #define PPC_STD(r, base, i) EMIT(PPC_INST_STD | ___PPC_RS(r) | \ 48 ___PPC_RA(base) | ((i) & 0xfffc)) 49 #define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \ 50 ___PPC_RA(base) | ((i) & 0xfffc)) 51 #define PPC_STW(r, base, i) EMIT(PPC_INST_STW | ___PPC_RS(r) | \ 52 ___PPC_RA(base) | IMM_L(i)) 53 #define PPC_STWU(r, base, i) EMIT(PPC_INST_STWU | ___PPC_RS(r) | \ 54 ___PPC_RA(base) | IMM_L(i)) 55 56 #define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ | ___PPC_RT(r) | \ 57 ___PPC_RA(base) | IMM_L(i)) 58 #define PPC_LD(r, base, i) EMIT(PPC_INST_LD | ___PPC_RT(r) | \ 59 ___PPC_RA(base) | IMM_L(i)) 60 #define PPC_LWZ(r, base, i) EMIT(PPC_INST_LWZ | ___PPC_RT(r) | \ 61 ___PPC_RA(base) | IMM_L(i)) 62 #define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \ 63 ___PPC_RA(base) | IMM_L(i)) 64 #define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \ 65 ___PPC_RA(base) | ___PPC_RB(b)) 66 67 #ifdef CONFIG_PPC64 68 #define PPC_BPF_LL(r, base, i) do { PPC_LD(r, base, i); } while(0) 69 #define PPC_BPF_STL(r, base, i) do { PPC_STD(r, base, i); } while(0) 70 #define PPC_BPF_STLU(r, base, i) do { PPC_STDU(r, base, i); } while(0) 71 #else 72 #define PPC_BPF_LL(r, base, i) do { PPC_LWZ(r, base, i); } while(0) 73 #define PPC_BPF_STL(r, base, i) do { PPC_STW(r, base, i); } while(0) 74 #define PPC_BPF_STLU(r, base, i) do { PPC_STWU(r, base, i); } while(0) 75 #endif 76 77 #define PPC_CMPWI(a, i) EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i)) 78 #define PPC_CMPDI(a, i) EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i)) 79 #define PPC_CMPLWI(a, i) EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i)) 80 #define PPC_CMPLW(a, b) EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | \ 81 ___PPC_RB(b)) 82 83 #define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) | \ 84 ___PPC_RB(a) | ___PPC_RA(b)) 85 #define PPC_ADD(d, a, b) EMIT(PPC_INST_ADD | ___PPC_RT(d) | \ 86 ___PPC_RA(a) | ___PPC_RB(b)) 87 #define PPC_MULW(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \ 88 ___PPC_RA(a) | ___PPC_RB(b)) 89 #define PPC_MULHWU(d, a, b) EMIT(PPC_INST_MULHWU | ___PPC_RT(d) | \ 90 ___PPC_RA(a) | ___PPC_RB(b)) 91 #define PPC_MULI(d, a, i) EMIT(PPC_INST_MULLI | ___PPC_RT(d) | \ 92 ___PPC_RA(a) | IMM_L(i)) 93 #define PPC_DIVWU(d, a, b) EMIT(PPC_INST_DIVWU | ___PPC_RT(d) | \ 94 ___PPC_RA(a) | ___PPC_RB(b)) 95 #define PPC_AND(d, a, b) EMIT(PPC_INST_AND | ___PPC_RA(d) | \ 96 ___PPC_RS(a) | ___PPC_RB(b)) 97 #define PPC_ANDI(d, a, i) EMIT(PPC_INST_ANDI | ___PPC_RA(d) | \ 98 ___PPC_RS(a) | IMM_L(i)) 99 #define PPC_AND_DOT(d, a, b) EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) | \ 100 ___PPC_RS(a) | ___PPC_RB(b)) 101 #define PPC_OR(d, a, b) EMIT(PPC_INST_OR | ___PPC_RA(d) | \ 102 ___PPC_RS(a) | ___PPC_RB(b)) 103 #define PPC_ORI(d, a, i) EMIT(PPC_INST_ORI | ___PPC_RA(d) | \ 104 ___PPC_RS(a) | IMM_L(i)) 105 #define PPC_ORIS(d, a, i) EMIT(PPC_INST_ORIS | ___PPC_RA(d) | \ 106 ___PPC_RS(a) | IMM_L(i)) 107 #define PPC_XOR(d, a, b) EMIT(PPC_INST_XOR | ___PPC_RA(d) | \ 108 ___PPC_RS(a) | ___PPC_RB(b)) 109 #define PPC_XORI(d, a, i) EMIT(PPC_INST_XORI | ___PPC_RA(d) | \ 110 ___PPC_RS(a) | IMM_L(i)) 111 #define PPC_XORIS(d, a, i) EMIT(PPC_INST_XORIS | ___PPC_RA(d) | \ 112 ___PPC_RS(a) | IMM_L(i)) 113 #define PPC_SLW(d, a, s) EMIT(PPC_INST_SLW | ___PPC_RA(d) | \ 114 ___PPC_RS(a) | ___PPC_RB(s)) 115 #define PPC_SRW(d, a, s) EMIT(PPC_INST_SRW | ___PPC_RA(d) | \ 116 ___PPC_RS(a) | ___PPC_RB(s)) 117 #define PPC_RLWINM(d, a, i, mb, me) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \ 118 ___PPC_RS(a) | __PPC_SH(i) | \ 119 __PPC_MB(mb) | __PPC_ME(me)) 120 #define PPC_RLDICR(d, a, i, me) EMIT(PPC_INST_RLDICR | ___PPC_RA(d) | \ 121 ___PPC_RS(a) | __PPC_SH(i) | \ 122 __PPC_ME64(me) | (((i) & 0x20) >> 4)) 123 124 /* slwi = rlwinm Rx, Ry, n, 0, 31-n */ 125 #define PPC_SLWI(d, a, i) PPC_RLWINM(d, a, i, 0, 31-(i)) 126 /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */ 127 #define PPC_SRWI(d, a, i) PPC_RLWINM(d, a, 32-(i), i, 31) 128 /* sldi = rldicr Rx, Ry, n, 63-n */ 129 #define PPC_SLDI(d, a, i) PPC_RLDICR(d, a, i, 63-(i)) 130 131 #define PPC_NEG(d, a) EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a)) 132 133 /* Long jump; (unconditional 'branch') */ 134 #define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \ 135 (((dest) - (ctx->idx * 4)) & 0x03fffffc)) 136 /* "cond" here covers BO:BI fields. */ 137 #define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \ 138 (((cond) & 0x3ff) << 16) | \ 139 (((dest) - (ctx->idx * 4)) & \ 140 0xfffc)) 141 /* Sign-extended 32-bit immediate load */ 142 #define PPC_LI32(d, i) do { \ 143 if ((int)(uintptr_t)(i) >= -32768 && \ 144 (int)(uintptr_t)(i) < 32768) \ 145 PPC_LI(d, i); \ 146 else { \ 147 PPC_LIS(d, IMM_H(i)); \ 148 if (IMM_L(i)) \ 149 PPC_ORI(d, d, IMM_L(i)); \ 150 } } while(0) 151 152 #define PPC_LI64(d, i) do { \ 153 if ((long)(i) >= -2147483648 && \ 154 (long)(i) < 2147483648) \ 155 PPC_LI32(d, i); \ 156 else { \ 157 if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \ 158 PPC_LI(d, ((uintptr_t)(i) >> 32) & 0xffff); \ 159 else { \ 160 PPC_LIS(d, ((uintptr_t)(i) >> 48)); \ 161 if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \ 162 PPC_ORI(d, d, \ 163 ((uintptr_t)(i) >> 32) & 0xffff); \ 164 } \ 165 PPC_SLDI(d, d, 32); \ 166 if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \ 167 PPC_ORIS(d, d, \ 168 ((uintptr_t)(i) >> 16) & 0xffff); \ 169 if ((uintptr_t)(i) & 0x000000000000ffffULL) \ 170 PPC_ORI(d, d, (uintptr_t)(i) & 0xffff); \ 171 } } while (0) 172 173 #ifdef CONFIG_PPC64 174 #define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0) 175 #else 176 #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0) 177 #endif 178 179 static inline bool is_nearbranch(int offset) 180 { 181 return (offset < 32768) && (offset >= -32768); 182 } 183 184 /* 185 * The fly in the ointment of code size changing from pass to pass is 186 * avoided by padding the short branch case with a NOP. If code size differs 187 * with different branch reaches we will have the issue of code moving from 188 * one pass to the next and will need a few passes to converge on a stable 189 * state. 190 */ 191 #define PPC_BCC(cond, dest) do { \ 192 if (is_nearbranch((dest) - (ctx->idx * 4))) { \ 193 PPC_BCC_SHORT(cond, dest); \ 194 PPC_NOP(); \ 195 } else { \ 196 /* Flip the 'T or F' bit to invert comparison */ \ 197 PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \ 198 PPC_JMP(dest); \ 199 } } while(0) 200 201 /* To create a branch condition, select a bit of cr0... */ 202 #define CR0_LT 0 203 #define CR0_GT 1 204 #define CR0_EQ 2 205 /* ...and modify BO[3] */ 206 #define COND_CMP_TRUE 0x100 207 #define COND_CMP_FALSE 0x000 208 /* Together, they make all required comparisons: */ 209 #define COND_GT (CR0_GT | COND_CMP_TRUE) 210 #define COND_GE (CR0_LT | COND_CMP_FALSE) 211 #define COND_EQ (CR0_EQ | COND_CMP_TRUE) 212 #define COND_NE (CR0_EQ | COND_CMP_FALSE) 213 #define COND_LT (CR0_LT | COND_CMP_TRUE) 214 215 #endif 216 217 #endif 218