1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * bpf_jit.h: BPF JIT compiler for PPC 4 * 5 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation 6 * 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> 7 */ 8 #ifndef _BPF_JIT_H 9 #define _BPF_JIT_H 10 11 #ifndef __ASSEMBLY__ 12 13 #include <asm/types.h> 14 #include <asm/ppc-opcode.h> 15 16 #ifdef PPC64_ELF_ABI_v1 17 #define FUNCTION_DESCR_SIZE 24 18 #else 19 #define FUNCTION_DESCR_SIZE 0 20 #endif 21 22 #define PLANT_INSTR(d, idx, instr) \ 23 do { if (d) { (d)[idx] = instr; } idx++; } while (0) 24 #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr) 25 26 /* Long jump; (unconditional 'branch') */ 27 #define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \ 28 (((dest) - (ctx->idx * 4)) & 0x03fffffc)) 29 /* blr; (unconditional 'branch' with link) to absolute address */ 30 #define PPC_BL_ABS(dest) EMIT(PPC_INST_BL | \ 31 (((dest) - (unsigned long)(image + ctx->idx)) & 0x03fffffc)) 32 /* "cond" here covers BO:BI fields. */ 33 #define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \ 34 (((cond) & 0x3ff) << 16) | \ 35 (((dest) - (ctx->idx * 4)) & \ 36 0xfffc)) 37 /* Sign-extended 32-bit immediate load */ 38 #define PPC_LI32(d, i) do { \ 39 if ((int)(uintptr_t)(i) >= -32768 && \ 40 (int)(uintptr_t)(i) < 32768) \ 41 EMIT(PPC_RAW_LI(d, i)); \ 42 else { \ 43 EMIT(PPC_RAW_LIS(d, IMM_H(i))); \ 44 if (IMM_L(i)) \ 45 EMIT(PPC_RAW_ORI(d, d, IMM_L(i))); \ 46 } } while(0) 47 48 #ifdef CONFIG_PPC32 49 #define PPC_EX32(r, i) EMIT(PPC_RAW_LI((r), (i) < 0 ? -1 : 0)) 50 #endif 51 52 #define PPC_LI64(d, i) do { \ 53 if ((long)(i) >= -2147483648 && \ 54 (long)(i) < 2147483648) \ 55 PPC_LI32(d, i); \ 56 else { \ 57 if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \ 58 EMIT(PPC_RAW_LI(d, ((uintptr_t)(i) >> 32) & \ 59 0xffff)); \ 60 else { \ 61 EMIT(PPC_RAW_LIS(d, ((uintptr_t)(i) >> 48))); \ 62 if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \ 63 EMIT(PPC_RAW_ORI(d, d, \ 64 ((uintptr_t)(i) >> 32) & 0xffff)); \ 65 } \ 66 EMIT(PPC_RAW_SLDI(d, d, 32)); \ 67 if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \ 68 EMIT(PPC_RAW_ORIS(d, d, \ 69 ((uintptr_t)(i) >> 16) & 0xffff)); \ 70 if ((uintptr_t)(i) & 0x000000000000ffffULL) \ 71 EMIT(PPC_RAW_ORI(d, d, (uintptr_t)(i) & \ 72 0xffff)); \ 73 } } while (0) 74 75 #ifdef CONFIG_PPC64 76 #define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0) 77 #else 78 #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0) 79 #endif 80 81 /* 82 * The fly in the ointment of code size changing from pass to pass is 83 * avoided by padding the short branch case with a NOP. If code size differs 84 * with different branch reaches we will have the issue of code moving from 85 * one pass to the next and will need a few passes to converge on a stable 86 * state. 87 */ 88 #define PPC_BCC(cond, dest) do { \ 89 if (is_offset_in_cond_branch_range((long)(dest) - (ctx->idx * 4))) { \ 90 PPC_BCC_SHORT(cond, dest); \ 91 EMIT(PPC_RAW_NOP()); \ 92 } else { \ 93 /* Flip the 'T or F' bit to invert comparison */ \ 94 PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \ 95 PPC_JMP(dest); \ 96 } } while(0) 97 98 /* To create a branch condition, select a bit of cr0... */ 99 #define CR0_LT 0 100 #define CR0_GT 1 101 #define CR0_EQ 2 102 /* ...and modify BO[3] */ 103 #define COND_CMP_TRUE 0x100 104 #define COND_CMP_FALSE 0x000 105 /* Together, they make all required comparisons: */ 106 #define COND_GT (CR0_GT | COND_CMP_TRUE) 107 #define COND_GE (CR0_LT | COND_CMP_FALSE) 108 #define COND_EQ (CR0_EQ | COND_CMP_TRUE) 109 #define COND_NE (CR0_EQ | COND_CMP_FALSE) 110 #define COND_LT (CR0_LT | COND_CMP_TRUE) 111 #define COND_LE (CR0_GT | COND_CMP_FALSE) 112 113 #define SEEN_FUNC 0x20000000 /* might call external helpers */ 114 #define SEEN_STACK 0x40000000 /* uses BPF stack */ 115 #define SEEN_TAILCALL 0x80000000 /* uses tail calls */ 116 117 #define SEEN_VREG_MASK 0x1ff80000 /* Volatile registers r3-r12 */ 118 #define SEEN_NVREG_MASK 0x0003ffff /* Non volatile registers r14-r31 */ 119 120 #ifdef CONFIG_PPC64 121 extern const int b2p[MAX_BPF_JIT_REG + 2]; 122 #else 123 extern const int b2p[MAX_BPF_JIT_REG + 1]; 124 #endif 125 126 struct codegen_context { 127 /* 128 * This is used to track register usage as well 129 * as calls to external helpers. 130 * - register usage is tracked with corresponding 131 * bits (r3-r31) 132 * - rest of the bits can be used to track other 133 * things -- for now, we use bits 0 to 2 134 * encoded in SEEN_* macros above 135 */ 136 unsigned int seen; 137 unsigned int idx; 138 unsigned int stack_size; 139 int b2p[ARRAY_SIZE(b2p)]; 140 }; 141 142 static inline void bpf_flush_icache(void *start, void *end) 143 { 144 smp_wmb(); /* smp write barrier */ 145 flush_icache_range((unsigned long)start, (unsigned long)end); 146 } 147 148 static inline bool bpf_is_seen_register(struct codegen_context *ctx, int i) 149 { 150 return ctx->seen & (1 << (31 - i)); 151 } 152 153 static inline void bpf_set_seen_register(struct codegen_context *ctx, int i) 154 { 155 ctx->seen |= 1 << (31 - i); 156 } 157 158 static inline void bpf_clear_seen_register(struct codegen_context *ctx, int i) 159 { 160 ctx->seen &= ~(1 << (31 - i)); 161 } 162 163 void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func); 164 int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx, 165 u32 *addrs, bool extra_pass); 166 void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx); 167 void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx); 168 void bpf_jit_realloc_regs(struct codegen_context *ctx); 169 170 #endif 171 172 #endif 173