1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * bpf_jit.h: BPF JIT compiler for PPC 4 * 5 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation 6 * 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> 7 */ 8 #ifndef _BPF_JIT_H 9 #define _BPF_JIT_H 10 11 #ifndef __ASSEMBLY__ 12 13 #include <asm/types.h> 14 #include <asm/ppc-opcode.h> 15 16 #ifdef PPC64_ELF_ABI_v1 17 #define FUNCTION_DESCR_SIZE 24 18 #else 19 #define FUNCTION_DESCR_SIZE 0 20 #endif 21 22 /* 23 * 16-bit immediate helper macros: HA() is for use with sign-extending instrs 24 * (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the 25 * top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000). 26 */ 27 #define IMM_H(i) ((uintptr_t)(i)>>16) 28 #define IMM_HA(i) (((uintptr_t)(i)>>16) + \ 29 (((uintptr_t)(i) & 0x8000) >> 15)) 30 31 #define PLANT_INSTR(d, idx, instr) \ 32 do { if (d) { (d)[idx] = instr; } idx++; } while (0) 33 #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr) 34 35 #define PPC_NOP() EMIT(PPC_INST_NOP) 36 #define PPC_BLR() EMIT(PPC_INST_BLR) 37 #define PPC_BLRL() EMIT(PPC_INST_BLRL) 38 #define PPC_MTLR(r) EMIT(PPC_INST_MTLR | ___PPC_RT(r)) 39 #define PPC_BCTR() EMIT(PPC_INST_BCTR) 40 #define PPC_MTCTR(r) EMIT(PPC_INST_MTCTR | ___PPC_RT(r)) 41 #define PPC_ADDI(d, a, i) EMIT(PPC_INST_ADDI | ___PPC_RT(d) | \ 42 ___PPC_RA(a) | IMM_L(i)) 43 #define PPC_MR(d, a) PPC_OR(d, a, a) 44 #define PPC_LI(r, i) PPC_ADDI(r, 0, i) 45 #define PPC_ADDIS(d, a, i) EMIT(PPC_INST_ADDIS | \ 46 ___PPC_RT(d) | ___PPC_RA(a) | IMM_L(i)) 47 #define PPC_LIS(r, i) PPC_ADDIS(r, 0, i) 48 #define PPC_STDX(r, base, b) EMIT(PPC_INST_STDX | ___PPC_RS(r) | \ 49 ___PPC_RA(base) | ___PPC_RB(b)) 50 #define PPC_STDU(r, base, i) EMIT(PPC_INST_STDU | ___PPC_RS(r) | \ 51 ___PPC_RA(base) | ((i) & 0xfffc)) 52 #define PPC_STW(r, base, i) EMIT(PPC_INST_STW | ___PPC_RS(r) | \ 53 ___PPC_RA(base) | IMM_L(i)) 54 #define PPC_STWU(r, base, i) EMIT(PPC_INST_STWU | ___PPC_RS(r) | \ 55 ___PPC_RA(base) | IMM_L(i)) 56 #define PPC_STH(r, base, i) EMIT(PPC_INST_STH | ___PPC_RS(r) | \ 57 ___PPC_RA(base) | IMM_L(i)) 58 #define PPC_STB(r, base, i) EMIT(PPC_INST_STB | ___PPC_RS(r) | \ 59 ___PPC_RA(base) | IMM_L(i)) 60 61 #define PPC_LBZ(r, base, i) EMIT(PPC_INST_LBZ | ___PPC_RT(r) | \ 62 ___PPC_RA(base) | IMM_L(i)) 63 #define PPC_LDX(r, base, b) EMIT(PPC_INST_LDX | ___PPC_RT(r) | \ 64 ___PPC_RA(base) | ___PPC_RB(b)) 65 #define PPC_LHZ(r, base, i) EMIT(PPC_INST_LHZ | ___PPC_RT(r) | \ 66 ___PPC_RA(base) | IMM_L(i)) 67 #define PPC_LHBRX(r, base, b) EMIT(PPC_INST_LHBRX | ___PPC_RT(r) | \ 68 ___PPC_RA(base) | ___PPC_RB(b)) 69 #define PPC_LDBRX(r, base, b) EMIT(PPC_INST_LDBRX | ___PPC_RT(r) | \ 70 ___PPC_RA(base) | ___PPC_RB(b)) 71 72 #define PPC_BPF_STWCX(s, a, b) EMIT(PPC_INST_STWCX | ___PPC_RS(s) | \ 73 ___PPC_RA(a) | ___PPC_RB(b)) 74 #define PPC_CMPWI(a, i) EMIT(PPC_INST_CMPWI | ___PPC_RA(a) | IMM_L(i)) 75 #define PPC_CMPDI(a, i) EMIT(PPC_INST_CMPDI | ___PPC_RA(a) | IMM_L(i)) 76 #define PPC_CMPW(a, b) EMIT(PPC_INST_CMPW | ___PPC_RA(a) | \ 77 ___PPC_RB(b)) 78 #define PPC_CMPD(a, b) EMIT(PPC_INST_CMPD | ___PPC_RA(a) | \ 79 ___PPC_RB(b)) 80 #define PPC_CMPLWI(a, i) EMIT(PPC_INST_CMPLWI | ___PPC_RA(a) | IMM_L(i)) 81 #define PPC_CMPLDI(a, i) EMIT(PPC_INST_CMPLDI | ___PPC_RA(a) | IMM_L(i)) 82 #define PPC_CMPLW(a, b) EMIT(PPC_INST_CMPLW | ___PPC_RA(a) | \ 83 ___PPC_RB(b)) 84 #define PPC_CMPLD(a, b) EMIT(PPC_INST_CMPLD | ___PPC_RA(a) | \ 85 ___PPC_RB(b)) 86 87 #define PPC_SUB(d, a, b) EMIT(PPC_INST_SUB | ___PPC_RT(d) | \ 88 ___PPC_RB(a) | ___PPC_RA(b)) 89 #define PPC_MULD(d, a, b) EMIT(PPC_INST_MULLD | ___PPC_RT(d) | \ 90 ___PPC_RA(a) | ___PPC_RB(b)) 91 #define PPC_MULW(d, a, b) EMIT(PPC_INST_MULLW | ___PPC_RT(d) | \ 92 ___PPC_RA(a) | ___PPC_RB(b)) 93 #define PPC_MULHWU(d, a, b) EMIT(PPC_INST_MULHWU | ___PPC_RT(d) | \ 94 ___PPC_RA(a) | ___PPC_RB(b)) 95 #define PPC_MULI(d, a, i) EMIT(PPC_INST_MULLI | ___PPC_RT(d) | \ 96 ___PPC_RA(a) | IMM_L(i)) 97 #define PPC_DIVWU(d, a, b) EMIT(PPC_INST_DIVWU | ___PPC_RT(d) | \ 98 ___PPC_RA(a) | ___PPC_RB(b)) 99 #define PPC_DIVDU(d, a, b) EMIT(PPC_INST_DIVDU | ___PPC_RT(d) | \ 100 ___PPC_RA(a) | ___PPC_RB(b)) 101 #define PPC_AND(d, a, b) EMIT(PPC_INST_AND | ___PPC_RA(d) | \ 102 ___PPC_RS(a) | ___PPC_RB(b)) 103 #define PPC_ANDI(d, a, i) EMIT(PPC_INST_ANDI | ___PPC_RA(d) | \ 104 ___PPC_RS(a) | IMM_L(i)) 105 #define PPC_AND_DOT(d, a, b) EMIT(PPC_INST_ANDDOT | ___PPC_RA(d) | \ 106 ___PPC_RS(a) | ___PPC_RB(b)) 107 #define PPC_OR(d, a, b) EMIT(PPC_INST_OR | ___PPC_RA(d) | \ 108 ___PPC_RS(a) | ___PPC_RB(b)) 109 #define PPC_MR(d, a) PPC_OR(d, a, a) 110 #define PPC_ORI(d, a, i) EMIT(PPC_INST_ORI | ___PPC_RA(d) | \ 111 ___PPC_RS(a) | IMM_L(i)) 112 #define PPC_ORIS(d, a, i) EMIT(PPC_INST_ORIS | ___PPC_RA(d) | \ 113 ___PPC_RS(a) | IMM_L(i)) 114 #define PPC_XOR(d, a, b) EMIT(PPC_INST_XOR | ___PPC_RA(d) | \ 115 ___PPC_RS(a) | ___PPC_RB(b)) 116 #define PPC_XORI(d, a, i) EMIT(PPC_INST_XORI | ___PPC_RA(d) | \ 117 ___PPC_RS(a) | IMM_L(i)) 118 #define PPC_XORIS(d, a, i) EMIT(PPC_INST_XORIS | ___PPC_RA(d) | \ 119 ___PPC_RS(a) | IMM_L(i)) 120 #define PPC_EXTSW(d, a) EMIT(PPC_INST_EXTSW | ___PPC_RA(d) | \ 121 ___PPC_RS(a)) 122 #define PPC_SLW(d, a, s) EMIT(PPC_INST_SLW | ___PPC_RA(d) | \ 123 ___PPC_RS(a) | ___PPC_RB(s)) 124 #define PPC_SLD(d, a, s) EMIT(PPC_INST_SLD | ___PPC_RA(d) | \ 125 ___PPC_RS(a) | ___PPC_RB(s)) 126 #define PPC_SRW(d, a, s) EMIT(PPC_INST_SRW | ___PPC_RA(d) | \ 127 ___PPC_RS(a) | ___PPC_RB(s)) 128 #define PPC_SRAW(d, a, s) EMIT(PPC_INST_SRAW | ___PPC_RA(d) | \ 129 ___PPC_RS(a) | ___PPC_RB(s)) 130 #define PPC_SRAWI(d, a, i) EMIT(PPC_INST_SRAWI | ___PPC_RA(d) | \ 131 ___PPC_RS(a) | __PPC_SH(i)) 132 #define PPC_SRD(d, a, s) EMIT(PPC_INST_SRD | ___PPC_RA(d) | \ 133 ___PPC_RS(a) | ___PPC_RB(s)) 134 #define PPC_SRAD(d, a, s) EMIT(PPC_INST_SRAD | ___PPC_RA(d) | \ 135 ___PPC_RS(a) | ___PPC_RB(s)) 136 #define PPC_SRADI(d, a, i) EMIT(PPC_INST_SRADI | ___PPC_RA(d) | \ 137 ___PPC_RS(a) | __PPC_SH64(i)) 138 #define PPC_RLWINM(d, a, i, mb, me) EMIT(PPC_INST_RLWINM | ___PPC_RA(d) | \ 139 ___PPC_RS(a) | __PPC_SH(i) | \ 140 __PPC_MB(mb) | __PPC_ME(me)) 141 #define PPC_RLWINM_DOT(d, a, i, mb, me) EMIT(PPC_INST_RLWINM_DOT | \ 142 ___PPC_RA(d) | ___PPC_RS(a) | \ 143 __PPC_SH(i) | __PPC_MB(mb) | \ 144 __PPC_ME(me)) 145 #define PPC_RLWIMI(d, a, i, mb, me) EMIT(PPC_INST_RLWIMI | ___PPC_RA(d) | \ 146 ___PPC_RS(a) | __PPC_SH(i) | \ 147 __PPC_MB(mb) | __PPC_ME(me)) 148 #define PPC_RLDICL(d, a, i, mb) EMIT(PPC_INST_RLDICL | ___PPC_RA(d) | \ 149 ___PPC_RS(a) | __PPC_SH64(i) | \ 150 __PPC_MB64(mb)) 151 #define PPC_RLDICR(d, a, i, me) EMIT(PPC_INST_RLDICR | ___PPC_RA(d) | \ 152 ___PPC_RS(a) | __PPC_SH64(i) | \ 153 __PPC_ME64(me)) 154 155 /* slwi = rlwinm Rx, Ry, n, 0, 31-n */ 156 #define PPC_SLWI(d, a, i) PPC_RLWINM(d, a, i, 0, 31-(i)) 157 /* srwi = rlwinm Rx, Ry, 32-n, n, 31 */ 158 #define PPC_SRWI(d, a, i) PPC_RLWINM(d, a, 32-(i), i, 31) 159 /* sldi = rldicr Rx, Ry, n, 63-n */ 160 #define PPC_SLDI(d, a, i) PPC_RLDICR(d, a, i, 63-(i)) 161 /* sldi = rldicl Rx, Ry, 64-n, n */ 162 #define PPC_SRDI(d, a, i) PPC_RLDICL(d, a, 64-(i), i) 163 164 #define PPC_NEG(d, a) EMIT(PPC_INST_NEG | ___PPC_RT(d) | ___PPC_RA(a)) 165 166 /* Long jump; (unconditional 'branch') */ 167 #define PPC_JMP(dest) EMIT(PPC_INST_BRANCH | \ 168 (((dest) - (ctx->idx * 4)) & 0x03fffffc)) 169 /* "cond" here covers BO:BI fields. */ 170 #define PPC_BCC_SHORT(cond, dest) EMIT(PPC_INST_BRANCH_COND | \ 171 (((cond) & 0x3ff) << 16) | \ 172 (((dest) - (ctx->idx * 4)) & \ 173 0xfffc)) 174 /* Sign-extended 32-bit immediate load */ 175 #define PPC_LI32(d, i) do { \ 176 if ((int)(uintptr_t)(i) >= -32768 && \ 177 (int)(uintptr_t)(i) < 32768) \ 178 PPC_LI(d, i); \ 179 else { \ 180 PPC_LIS(d, IMM_H(i)); \ 181 if (IMM_L(i)) \ 182 PPC_ORI(d, d, IMM_L(i)); \ 183 } } while(0) 184 185 #define PPC_LI64(d, i) do { \ 186 if ((long)(i) >= -2147483648 && \ 187 (long)(i) < 2147483648) \ 188 PPC_LI32(d, i); \ 189 else { \ 190 if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \ 191 PPC_LI(d, ((uintptr_t)(i) >> 32) & 0xffff); \ 192 else { \ 193 PPC_LIS(d, ((uintptr_t)(i) >> 48)); \ 194 if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \ 195 PPC_ORI(d, d, \ 196 ((uintptr_t)(i) >> 32) & 0xffff); \ 197 } \ 198 PPC_SLDI(d, d, 32); \ 199 if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \ 200 PPC_ORIS(d, d, \ 201 ((uintptr_t)(i) >> 16) & 0xffff); \ 202 if ((uintptr_t)(i) & 0x000000000000ffffULL) \ 203 PPC_ORI(d, d, (uintptr_t)(i) & 0xffff); \ 204 } } while (0) 205 206 #ifdef CONFIG_PPC64 207 #define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0) 208 #else 209 #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0) 210 #endif 211 212 static inline bool is_nearbranch(int offset) 213 { 214 return (offset < 32768) && (offset >= -32768); 215 } 216 217 /* 218 * The fly in the ointment of code size changing from pass to pass is 219 * avoided by padding the short branch case with a NOP. If code size differs 220 * with different branch reaches we will have the issue of code moving from 221 * one pass to the next and will need a few passes to converge on a stable 222 * state. 223 */ 224 #define PPC_BCC(cond, dest) do { \ 225 if (is_nearbranch((dest) - (ctx->idx * 4))) { \ 226 PPC_BCC_SHORT(cond, dest); \ 227 PPC_NOP(); \ 228 } else { \ 229 /* Flip the 'T or F' bit to invert comparison */ \ 230 PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \ 231 PPC_JMP(dest); \ 232 } } while(0) 233 234 /* To create a branch condition, select a bit of cr0... */ 235 #define CR0_LT 0 236 #define CR0_GT 1 237 #define CR0_EQ 2 238 /* ...and modify BO[3] */ 239 #define COND_CMP_TRUE 0x100 240 #define COND_CMP_FALSE 0x000 241 /* Together, they make all required comparisons: */ 242 #define COND_GT (CR0_GT | COND_CMP_TRUE) 243 #define COND_GE (CR0_LT | COND_CMP_FALSE) 244 #define COND_EQ (CR0_EQ | COND_CMP_TRUE) 245 #define COND_NE (CR0_EQ | COND_CMP_FALSE) 246 #define COND_LT (CR0_LT | COND_CMP_TRUE) 247 #define COND_LE (CR0_GT | COND_CMP_FALSE) 248 249 #endif 250 251 #endif 252