1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * bpf_jit.h: BPF JIT compiler for PPC 4 * 5 * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation 6 * 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com> 7 */ 8 #ifndef _BPF_JIT_H 9 #define _BPF_JIT_H 10 11 #ifndef __ASSEMBLY__ 12 13 #include <asm/types.h> 14 #include <asm/ppc-opcode.h> 15 16 #ifdef PPC64_ELF_ABI_v1 17 #define FUNCTION_DESCR_SIZE 24 18 #else 19 #define FUNCTION_DESCR_SIZE 0 20 #endif 21 22 #define PLANT_INSTR(d, idx, instr) \ 23 do { if (d) { (d)[idx] = instr; } idx++; } while (0) 24 #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr) 25 26 /* Long jump; (unconditional 'branch') */ 27 #define PPC_JMP(dest) \ 28 do { \ 29 long offset = (long)(dest) - (ctx->idx * 4); \ 30 if (!is_offset_in_branch_range(offset)) { \ 31 pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \ 32 return -ERANGE; \ 33 } \ 34 EMIT(PPC_INST_BRANCH | (offset & 0x03fffffc)); \ 35 } while (0) 36 37 /* blr; (unconditional 'branch' with link) to absolute address */ 38 #define PPC_BL_ABS(dest) EMIT(PPC_INST_BL | \ 39 (((dest) - (unsigned long)(image + ctx->idx)) & 0x03fffffc)) 40 /* "cond" here covers BO:BI fields. */ 41 #define PPC_BCC_SHORT(cond, dest) \ 42 do { \ 43 long offset = (long)(dest) - (ctx->idx * 4); \ 44 if (!is_offset_in_cond_branch_range(offset)) { \ 45 pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \ 46 return -ERANGE; \ 47 } \ 48 EMIT(PPC_INST_BRANCH_COND | (((cond) & 0x3ff) << 16) | (offset & 0xfffc)); \ 49 } while (0) 50 51 /* Sign-extended 32-bit immediate load */ 52 #define PPC_LI32(d, i) do { \ 53 if ((int)(uintptr_t)(i) >= -32768 && \ 54 (int)(uintptr_t)(i) < 32768) \ 55 EMIT(PPC_RAW_LI(d, i)); \ 56 else { \ 57 EMIT(PPC_RAW_LIS(d, IMM_H(i))); \ 58 if (IMM_L(i)) \ 59 EMIT(PPC_RAW_ORI(d, d, IMM_L(i))); \ 60 } } while(0) 61 62 #ifdef CONFIG_PPC32 63 #define PPC_EX32(r, i) EMIT(PPC_RAW_LI((r), (i) < 0 ? -1 : 0)) 64 #endif 65 66 #define PPC_LI64(d, i) do { \ 67 if ((long)(i) >= -2147483648 && \ 68 (long)(i) < 2147483648) \ 69 PPC_LI32(d, i); \ 70 else { \ 71 if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \ 72 EMIT(PPC_RAW_LI(d, ((uintptr_t)(i) >> 32) & \ 73 0xffff)); \ 74 else { \ 75 EMIT(PPC_RAW_LIS(d, ((uintptr_t)(i) >> 48))); \ 76 if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \ 77 EMIT(PPC_RAW_ORI(d, d, \ 78 ((uintptr_t)(i) >> 32) & 0xffff)); \ 79 } \ 80 EMIT(PPC_RAW_SLDI(d, d, 32)); \ 81 if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \ 82 EMIT(PPC_RAW_ORIS(d, d, \ 83 ((uintptr_t)(i) >> 16) & 0xffff)); \ 84 if ((uintptr_t)(i) & 0x000000000000ffffULL) \ 85 EMIT(PPC_RAW_ORI(d, d, (uintptr_t)(i) & \ 86 0xffff)); \ 87 } } while (0) 88 89 #ifdef CONFIG_PPC64 90 #define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0) 91 #else 92 #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0) 93 #endif 94 95 /* 96 * The fly in the ointment of code size changing from pass to pass is 97 * avoided by padding the short branch case with a NOP. If code size differs 98 * with different branch reaches we will have the issue of code moving from 99 * one pass to the next and will need a few passes to converge on a stable 100 * state. 101 */ 102 #define PPC_BCC(cond, dest) do { \ 103 if (is_offset_in_cond_branch_range((long)(dest) - (ctx->idx * 4))) { \ 104 PPC_BCC_SHORT(cond, dest); \ 105 EMIT(PPC_RAW_NOP()); \ 106 } else { \ 107 /* Flip the 'T or F' bit to invert comparison */ \ 108 PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \ 109 PPC_JMP(dest); \ 110 } } while(0) 111 112 /* To create a branch condition, select a bit of cr0... */ 113 #define CR0_LT 0 114 #define CR0_GT 1 115 #define CR0_EQ 2 116 /* ...and modify BO[3] */ 117 #define COND_CMP_TRUE 0x100 118 #define COND_CMP_FALSE 0x000 119 /* Together, they make all required comparisons: */ 120 #define COND_GT (CR0_GT | COND_CMP_TRUE) 121 #define COND_GE (CR0_LT | COND_CMP_FALSE) 122 #define COND_EQ (CR0_EQ | COND_CMP_TRUE) 123 #define COND_NE (CR0_EQ | COND_CMP_FALSE) 124 #define COND_LT (CR0_LT | COND_CMP_TRUE) 125 #define COND_LE (CR0_GT | COND_CMP_FALSE) 126 127 #define SEEN_FUNC 0x20000000 /* might call external helpers */ 128 #define SEEN_TAILCALL 0x40000000 /* uses tail calls */ 129 130 #define SEEN_VREG_MASK 0x1ff80000 /* Volatile registers r3-r12 */ 131 #define SEEN_NVREG_MASK 0x0003ffff /* Non volatile registers r14-r31 */ 132 133 #ifdef CONFIG_PPC64 134 extern const int b2p[MAX_BPF_JIT_REG + 2]; 135 #else 136 extern const int b2p[MAX_BPF_JIT_REG + 1]; 137 #endif 138 139 struct codegen_context { 140 /* 141 * This is used to track register usage as well 142 * as calls to external helpers. 143 * - register usage is tracked with corresponding 144 * bits (r3-r31) 145 * - rest of the bits can be used to track other 146 * things -- for now, we use bits 0 to 2 147 * encoded in SEEN_* macros above 148 */ 149 unsigned int seen; 150 unsigned int idx; 151 unsigned int stack_size; 152 int b2p[ARRAY_SIZE(b2p)]; 153 }; 154 155 static inline void bpf_flush_icache(void *start, void *end) 156 { 157 smp_wmb(); /* smp write barrier */ 158 flush_icache_range((unsigned long)start, (unsigned long)end); 159 } 160 161 static inline bool bpf_is_seen_register(struct codegen_context *ctx, int i) 162 { 163 return ctx->seen & (1 << (31 - i)); 164 } 165 166 static inline void bpf_set_seen_register(struct codegen_context *ctx, int i) 167 { 168 ctx->seen |= 1 << (31 - i); 169 } 170 171 static inline void bpf_clear_seen_register(struct codegen_context *ctx, int i) 172 { 173 ctx->seen &= ~(1 << (31 - i)); 174 } 175 176 void bpf_jit_emit_func_call_rel(u32 *image, struct codegen_context *ctx, u64 func); 177 int bpf_jit_build_body(struct bpf_prog *fp, u32 *image, struct codegen_context *ctx, 178 u32 *addrs); 179 void bpf_jit_build_prologue(u32 *image, struct codegen_context *ctx); 180 void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx); 181 void bpf_jit_realloc_regs(struct codegen_context *ctx); 182 183 #endif 184 185 #endif 186